a Complete 14-Bit, 10 MSPS

Monolithic A/D Converter

AD9240
FEATURES FUNCTIONAL BLOCK DIAGRAM
Monolithic 14-Bit, 10 MSPS A/D Converter
Low Power Dissipation: 285 mW
CLK AVDD DVDD DRVDD
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB SHA
VINA MDAC1 MDAC2 MDAC3 BIAS
Differential Nonlinearity Error: 0.6 LSB VINB GAIN = 16 GAIN = 8 GAIN = 8
Input Referred Noise: 0.36 LSB CML
5 4 4
A/D A/D A/D A/D
Complete: On-Chip Sample-and-Hold Amplifier and CAPT 5 4 4 4
Voltage Reference CAPB DIGITAL CORRECTION LOGIC
Signal-to-Noise and Distortion Ratio: 77.5 dB 14
VREF
Spurious-Free Dynamic Range: 90 dB OUTPUT BUFFERS OTR
SENSE BIT 1
Out-of-Range Indicator 1V (MSB)
MODE
Straight Binary Output Data SELECT AD9240 BIT 14
(LSB)
44-Lead MQFP
REFCOM AVSS DVSS DRVSS

PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS

The AD9240 is a 10 MSPS, single supply, 14-bit analog-to- The AD9240 offers a complete single-chip sampling 14-bit,
digital converter (ADC). It combines a low cost, high speed analog-to-digital conversion function in a 44-lead Metric Quad
CMOS process and a novel architecture to achieve the resolution Flatpack.
and speed of existing hybrid implementations at a fraction of the Low Power and Single Supply
power consumption and cost. It is a complete, monolithic ADC The AD9240 consumes only 280 mW on a single +5 V power
with an on-chip, high performance, low noise sample-and-hold supply.
amplifier and programmable voltage reference. An external refer-
Excellent DC Performance Over Temperature
ence can also be chosen to suit the dc accuracy and temperature
The AD9240 provides no missing codes, and excellent tempera-
drift requirements of the application. The device uses a multistage
ture drift performance over the full operating temperature range.
differential pipelined architecture with digital output error correc-
tion logic to guarantee no missing codes over the full operating Excellent AC Performance and Low Noise
temperature range. The AD9240 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.
The input of the AD9240 is highly flexible, allowing for easy
interfacing to imaging, communications, medical and data- Flexible Analog Input Range
acquisition systems. A truly differential input structure allows The versatile onboard sample-and-hold (SHA) can be configured
for both single-ended and differential input interfaces of varying for either single ended or differential inputs of varying input spans.
input spans. The sample-and-hold amplifier (SHA) is equally Flexible Digital Outputs
suited for multiplexed systems that switch full-scale voltage The digital outputs can be configured to interface with +3 V and
levels in successive channels as well as sampling single-channel +5 V CMOS logic families.
inputs at frequencies up to and beyond the Nyquist rate. The Excellent Undersampling Performance
AD9240 also performs well in communication systems employ- The full power bandwidth and dynamic range of the AD9240
ing Direct-IF Down Conversion, since the SHA in the differen- make it well suited for Direct-IF Down Conversion extending to
tial input mode can achieve excellent dynamic performance well 45 MHz.
beyond its specified Nyquist frequency of 5 MHz.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an
overflow condition which can be used with the most significant
bit to determine low or high overflow.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781 /461-3113 © Analog Devices, Inc., 2010
AD9240–SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, fSAMPLE = 10 MSPS, RBIAS = 2 k⍀, VREF = 2.5 V, VINB = 2.5 V,
DC SPECIFICATIONS T MIN to TMAX unless otherwise noted)

Parameter AD9240 Units

RESOLUTION 14 Bits min
MAX CONVERSION RATE 10 MHz min
INPUT REFERRED NOISE
VREF = 1 V 0.9 LSB rms typ
VREF = 2.5 V 0.36 LSB rms typ
ACCURACY
Integral Nonlinearity (INL) ± 2.5 LSB typ
Differential Nonlinearity (DNL) ± 0.6 LSB typ
± 1.0 LSB max
INL1 ± 2.5 LSB typ
DNL1 ± 0.7 LSB typ
No Missing Codes 14 Bits Guaranteed
Zero Error (@ +25°C) 0.3 % FSR max
Gain Error (@ +25°C)2 1.5 % FSR max
Gain Error (@ +25°C)3 0.75 % FSR max
TEMPERATURE DRIFT
Zero Error 3.0 ppm/°C typ
Gain Error2 20.0 ppm/°C typ
Gain Error3 5.0 ppm/°C typ
POWER SUPPLY REJECTION 0.1 % FSR max
ANALOG INPUT
Input Span (with VREF = 1.0 V) 2 V p-p min
Input Span (with VREF = 2.5 V) 5 V p-p max
Input (VINA or VINB) Range 0 V min
AVDD V max
Input Capacitance 16 pF typ
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) 1 Volts typ
Output Voltage Tolerance (1 V Mode) ± 14 mV max
Output Voltage (2.5 V Mode) 2.5 Volts typ
Output Voltage Tolerance (2.5 V Mode) ± 35 mV max
Load Regulation4 5.0 mV max
REFERENCE INPUT RESISTANCE 5 kΩ typ
POWER SUPPLIES
Supply Voltages
AVDD +5 V (± 5% AVDD Operating)
DVDD +5 V (± 5% DVDD Operating)
DRVDD +5 V (± 5% DRVDD Operating)
Supply Current
IAVDD 50 mA max (46 mA typ)
IDRVDD 1 mA max (0.1 mA typ)
IDVDD 15 mA max (11 mA typ)
POWER CONSUMPTION 330 mW max (285 mW typ)
NOTES
1
VREF = 1 V.
2
Including internal reference.
3
Excluding internal reference.
4
Load regulation with 1 mA load current (in addition to that required by the AD9240).
Specification subject to change without notice.

–2– REV. B
 AD9240
(AVDD = +5 V, DVDD= +5 V, DRVDD = +5 V, fSAMPLE = 10 MSPS, RBIAS = 2 k⍀, VREF = 2.5 V, AIN = –0.5 dBFS,
AC SPECIFICATIONS AC Coupled/Differential Input, T MIN to TMAX unless otherwise noted)

Parameter AD9240 Units

SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
fINPUT = 500 kHz 75.0 dB min
77.5 dB typ
fINPUT = 1.0 MHz 77.5 dB typ
fINPUT = 5.0 MHz 75.0 dB typ
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 500 kHz 12.2 Bits min
12.6 Bits typ
fINPUT = 1.0 MHz 12.6 Bits typ
fINPUT = 5.0 MHz 12.2 Bits typ
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 500 kHz 76.0 dB min
78.5 dB typ
fINPUT = 1.0 MHz 78.5 dB typ
fINPUT = 5.0 MHz 78.5 dB typ
TOTAL HARMONIC DISTORTION (THD)
fINPUT = 500 kHz –78.0 dB max
–85.0 dB typ
fINPUT = 1.0 MHz –85.0 dB typ
fINPUT = 5.0 MHz –77.0 dB typ
SPURIOUS FREE DYNAMIC RANGE
fINPUT = 500 kHz 90.0 dB typ
fINPUT = 1.0 MHz 90.0 dB typ
fINPUT = 5.0 MHz 80.0 dB typ
DYNAMIC PERFORMANCE
Full Power Bandwidth 70 MHz typ
Small Signal Bandwidth 70 MHz typ
Aperture Delay 1 ns typ
Aperture Jitter 4 ps rms typ
Acquisition to Full-Scale Step (0.0025%) 45 ns typ
Overvoltage Recovery Time 167 ns typ
Specifications subject to change without notice.

DIGITAL SPECIFICATIONS (AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)

Parameters Symbol AD9240 Units
CLOCK INPUT
High Level Input Voltage VIH +3.5 V min
Low Level Input Voltage VIL +1.0 V max
High Level Input Current (VIN = DVDD) IIH ± 10 µA max
Low Level Input Current (VIN = 0 V) IIL ± 10 µA max
Input Capacitance CIN 5 pF typ
LOGIC OUTPUTS (with DRVDD = 5 V)
High Level Output Voltage (IOH = 50 µA) VOH +4.5 V min
High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V min
Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V max
Low Level Output Voltage (IOL = 50 µA) VOL +0.1 V max
Output Capacitance COUT 5 pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA) VOH +2.4 V min
Low Level Output Voltage (IOL = 50 µA) VOL +0.7 V max
Specifications subject to change without notice.

REV. B –3–
AD9240
SWITCHING SPECIFICATIONS (T MIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, RBIAS = 2 k⍀, CL = 20 pF)
Parameters Symbol AD9240 Units
1
Clock Period tC 100 ns min
CLOCK Pulsewidth High tCH 45 ns min
CLOCK Pulsewidth Low tCL 45 ns min
Output Delay tOD 8 ns min
13 ns typ
19 ns max
Pipeline Delay (Latency) 3 Clock Cycles
NOTES
1
The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.
Specifications subject to change without notice.

THERMAL CHARACTERISTICS
S1 S2 Thermal Resistance
ANALOG S4
INPUT
tC 44-Lead MQFP
S3
tCH tCL
θJA = 53.2°C/W
INPUT θJC = 19°C/W
CLOCK
tOD
DATA DATA 1
OUTPUT

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With
Respect
Parameter to Min Max Units
AVDD AVSS –0.3 +6.5 V PIN CONFIGURATION
DVDD DVSS –0.3 +6.5 V
AVSS DVSS –0.3 +0.3 V

CAPB
CAPT
VINB
VINA

BIAS
AVDD DVDD –6.5 +6.5 V
CML

NC
NC
NC

NC

NC

DRVDD DRVSS –0.3 +6.5 V

44 43 42 41 40 39 38 37 36 35 34
DRVSS AVSS –0.3 +0.3 V
REFCOM AVSS –0.3 +0.3 V DVSS 1
PIN 1
33 REFCOM
CLK AVSS –0.3 AVDD + 0.3 V AVSS 2 IDENTIFIER 32 VREF
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V DVDD 3 31 SENSE
VINA, VINB AVSS –0.3 AVDD + 0.3 V AVDD 4 30 NC
VREF AVSS –0.3 AVDD + 0.3 V DRVSS 5 AD9240 29 AVSS
SENSE AVSS –0.3 AVDD + 0.3 V DRVDD 6 TOP VIEW 28 AVDD
CAPB, CAPT AVSS –0.3 AVDD + 0.3 V (Not to Scale)
CLK 7 27 NC
BIAS AVSS –0.3 AVDD + 0.3 V NC 8 26 NC
Junction Temperature +150 °C NC 9 25 OTR
Storage Temperature –65 +150 °C NC 10 24 BIT 1 (MSB)
Lead Temperature (LSB) BIT 14 11 23 BIT 2
(10 sec) +300 °C
12 13 14 15 16 17 18 19 20 21 22
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
BIT 11

BIT 8
BIT 12
BIT 13

BIT 3
BIT 7
BIT 6
BIT 9
BIT 10

BIT 5
BIT 4

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings NC = NO CONNECT
for extended periods may effect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD9240 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD9240
PIN FUNCTION DESCRIPTIONS OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time
Pin required for the ADC to achieve a specified accuracy after an
Number Name Description overvoltage (50% greater than full-scale range), measured from
1 DVSS Digital Ground the time the overvoltage signal reenters the converter’s range.
2, 29 AVSS Analog Ground
TEMPERATURE DRIFT
3 DVDD +5 V Digital Supply
The temperature drift for zero error and gain error specifies the
4, 28 AVDD +5 V Analog Supply
maximum change from the initial (+25°C) value to the value at
5 DRVSS Digital Output Driver Ground
TMIN or TMAX.
6 DRVDD Digital Output Driver Supply
7 CLK Clock Input Pin POWER SUPPLY REJECTION
8–10 NC No Connect The specification shows the maximum change in full scale from
11 BIT 14 Least Significant Data Bit (LSB) the value with the supply at the minimum limit to the value
12–23 BIT 13–BIT 2 Data Output Bits with the supply at its maximum limit.
24 BIT 1 Most Significant Data Bit (MSB)
25 OTR Out of Range APERTURE JITTER
26, 27, 30 NC No Connect Aperture jitter is the variation in aperture delay for successive
31 SENSE Reference Select samples and is manifested as noise on the input to the A/D.
32 VREF Reference I/O
33 REFCOM Reference Common APERTURE DELAY
34, 38, 40, Aperture delay is a measure of the sample-and-hold amplifier
43, 44 NC No Connect (SHA) performance and is measured from the rising edge of the
35 BIAS* Power/Speed Programming clock input to when the input signal is held for conversion.
36 CAPB Noise Reduction Pin SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
37 CAPT Noise Reduction Pin RATIO
39 CML Common-Mode Level (Midsupply) S/N+D is the ratio of the rms value of the measured input sig-
41 VINA Analog Input Pin (+) nal to the rms sum of all other spectral components below the
42 VINB Analog Input Pin (–) Nyquist frequency, including harmonics but excluding dc.
*See Speed/Power Programmability section. The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

DEFINITIONS OF SPECIFICATION For a sine wave, SINAD can be expressed in terms of the num-
INTEGRAL NONLINEARITY (INL) ber of bits. Using the following formula,
INL refers to the deviation of each individual code from a line N = (SINAD – 1.76)/6.02
drawn from “negative full scale” through “positive full scale.”
it is possible to get a measure of performance expressed as N,
The point used as “negative full scale” occurs 1/2 LSB before
the effective number of bits.
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation Thus, an effective number of bits for a device for sine wave
is measured from the middle of each particular code to the true inputs at a given input frequency can be calculated directly
straight line. from its measured SINAD.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING TOTAL HARMONIC DISTORTION (THD)

CODES) THD is the ratio of the rms sum of the first six harmonic
An ideal ADC exhibits code transitions that are exactly 1 LSB components to the rms value of the measured input signal and
apart. DNL is the deviation from this ideal value. Guaranteed is expressed as a percentage or in decibels.
no missing codes to 14-bit resolution indicates that all 16384
SIGNAL-TO-NOISE RATIO (SNR)
codes, respectively, must be present over all operating ranges.
SNR is the ratio of the rms value of the measured input signal
ZERO ERROR to the rms sum of all other spectral components below the
The major carry transition should occur for an analog value Nyquist frequency, excluding the first six harmonics and dc.
1/2 LSB below VINA = VINB. Zero error is defined as the The value for SNR is expressed in decibels.
deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
GAIN ERROR SFDR is the difference in dB between the rms amplitude of the
The first code transition should occur at an analog value 1/2 LSB input signal and the peak spurious signal.
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error TWO-TONE SFDR
is the deviation of the actual difference between first and last The ratio of the rms value of either input tone to the rms value
code transitions and the ideal difference between first and last of the peak spurious component. The peak spurious component
code transitions. may or may not be an IMD product. Two-tone SFDR may be
reported in dBc (i.e., degrades as signal level is lowered), or in
dBFS (always related back to converter full scale).

REV. B –5–
AD9240
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, fSAMPLE =
Typical Differential AC Characterization Curves/Plots 10 MSPS, R BIAS = 2 k⍀, TA = +25ⴗC, Differential Input)

90 –40 0
1st
–10
85
–50 –20
80 –0.5dBFS –30

AMPLITUDE – dB
–60 –40
75
SINAD – dB

–6.0dBFS

THD – dB
–20.0dBFS –50
70 –70 –60

–6.0dBFS –70
65 2nd 3rd
–20.0dBFS –80 –80 5th
60 –90 9th 4th
8th
–90 –0.5dBFS 7th 6th
–100
55
–110
50 –100 –120
0.1 1 10 20 0.1 1 10 20 0 5.0
INPUT FREQUENCY – MHz FREQUENCY – MHz
INPUT FREQUENCY – MHz

Figure 2. SINAD vs. Input Frequency Figure 3. THD vs. Input Frequency Figure 4. Typical FFT, fIN = 1.0 MHz
(Input Span = 5 V, VCM = 2.5 V) (Input Span = 5 V, VCM = 2.5 V) (Input Span = 5 V, VCM = 2.5 V)

90 –40 0
1
85 –15
–50
–30
80
–45

AMPLITUDE – dB
–0.5dBFS –60
75
SINAD – dB

–60
THD – dB

–20.0dBFS
70 –6.0dBFS
–70 –75
2 3
4 5
65 –90 6 8 9 7
–80 –6.0dBFS
–105
60
–20.0dBFS –90 –120
55 –0.5dBFS
–135
50 –100 –150
0.1 1 10 20 0.1 1 10 20 0 5.0
INPUT FREQUENCY – MHz FREQUENCY – MHz
INPUT FREQUENCY – MHz

Figure 5. SINAD vs. Input Frequency Figure 6. THD vs. Input Frequency Figure 7. Typical FFT, fIN = 5.0 MHz
(Input Span = 2 V, VCM = 2.5 V) (Input Span = 2 V, VCM = 2.5 V) (Input Span = 2 V, VCM = 2.5 V)

–60 110 110

WORST CASE SPURIOUS – dBc AND dBFS

5V SPAN – dBFS
105
–65 100
5V SPAN – dBFS
100
SFDR – dBc AND dBFS

90
–70
5V SPAN 2V SPAN – dBFS 95
80 2V SPAN – dBFS
–75 90
THD – dB

70 5V SPAN – dBc
–80 2V SPAN 85
60
80
–85 2V SPAN – dBc
50 75 5V SPAN – dBc
–90 40 70 2V SPAN – dBc
–95 30 65

–100 20 60
0.1 1 10 –60 –50 –40 –30 –20 –10 0 –40 –35 –30 –25 –20 –15 –10 –5 0
SAMPLE RATE – MHz AIN – dB INPUT POWER LEVEL (f1 = f2) – dBFS

Figure 8. THD vs. Sample Rate Figure 9. Single Tone SFDR Figure 10. Dual Tone SFDR
(fIN = 5.0 MHz, AIN = –0.5 dBFS, (fIN = 5.0 MHz, VCM = 2.5 V) (f1 = 0.95 MHz, f2 = 1.04 MHz,
VCM = 2.5 V) VCM = 2.5 V)

–6– REV. B
 AD9240
(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, fSAMPLE = 10 MSPS, RBIAS = 2 k⍀,
Other Characterization Curves/Plots T = +25ⴗC, Single-Ended Input) A

3.0 1.0
2.5 13484335
0.8
2.0
0.6
1.5
0.4
1.0

DNL – LSB
0.2
INL – LSB

0.5

HITS
0.0 0.0
–0.5 –0.2
–1.0
–0.4
–1.5
–0.6 1414263 1482053
–2.0
–2.5 –0.8
–3.0 –1.0
0 16863 0 16383 N–1 N N+1
CODE CODE
CODE

Figure 11. Typical INL Figure 12. Typical DNL Figure 13. “Grounded-Input”
(Input Span = 5 V) (Input Span = 5 V) Histogram (Input Span = 5 V)

90 –40 0
85 –10
–50
80
–20
75 –0.5dBFS

AMPLITUDE – dB
–60
SINAD – dB

70 –30
THD – dB

–20.0dBFS
65 –70 –40
–6.0dBFS
60
–50
–80
55 –20.0dBFS –6.0dBFS
–60
50
–90
–0.5dBFS –70
45
40 –100 –80
0.1 1 10 20 0.1 1 10 20 1 10 100
INPUT FREQUENCY – MHz INPUT FREQUENCY – MHz FREQUENCY – MHz

Figure 14. SINAD vs. Input Frequency Figure 15. THD vs. Input Frequency Figure 16. CMR vs. Input Frequency
(Input Span = 2 V, VCM = 2.5 V) (Input Span = 2 V, VCM = 2.5 V) (Input Span = 2 V, VCM = 2.5 V)

90 –40 0.01

85 0.008
–50
0.006
80
–0.5dBFS 0.004
VREF ERROR – V

–60 –0.5dBFS
75
SINAD – dB

0.002
THD – dB

–20dBFS
70 –6.0dBFS –70 0

65 –0.002
–80
–20.0dBFS –0.004
60 –6.0dBFS
–0.006
–90
55
–0.008
50 –100 –0.01
0.1 1 10 20 0.1 1 10 20 –60 –40 –20 0 20 40 60 80 100 120 140
INPUT FREQUENCY – MHz INPUT FREQUENCY – MHz TEMPERATURE – 8C

Figure 17. SINAD vs. Input Frequency Figure 18. THD vs. Input Frequency Figure 19. Typical Voltage Reference
(Input Span = 5 V, VCM = 2.5 V) (Input Span = 5 V, VCM = 2.5 V) Error vs. Temperature

REV. B –7–
AD9240
INTRODUCTION 80
RBIAS =
The AD9240 uses a four-stage pipeline architecture with a 2kV
70
wideband input sample-and-hold amplifier (SHA) implemented RBIAS =
on a cost-effective CMOS process. Each stage of the pipeline, 60
4kV

excluding the last, consists of a low resolution flash A/D con-

nected to a switched capacitor DAC and interstage residue 50

SINAD – dB
amplifier (MDAC). The residue amplifier amplifies the differ- 40 RBIAS = 10kV
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used 30 RBIAS = 20kV
in each of the stages to facilitate digital correction of flash er-
20 RBIAS = 200kV
rors. The last stage simply consists of a flash A/D.
10
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the 0
1 10 20
converter is capable of capturing a new input sample every clock
CLOCK FREQUENCY – MHz
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a Figure 21. SINAD vs. Clock Frequency for Varying RBIAS
concern in most applications. The digital output, together with Values (VCM = 2.5 V, AIN = –0.5 dB, 5 V Span, fIN = fCLK/2)
the out-of-range indicator (OTR), is latched into an output
400
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
350
The AD9240 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing = 1.7kV
300 R BIAS
requirements). The A/D samples the analog input on the rising POWER – mW = 2kV
edge of the clock input. During the clock low time (between the R BIAS
250 = 2.5kV
falling edge and rising edge of the clock), the input SHA is in R BIAS
= 3.3kV
the sample mode; during the clock high time it is in the hold R BIAS
mode. System disturbances just prior to the rising edge of the 200 = 5kV
R BIAS
clock and/or excessive clock jitter may cause the input SHA to = 10kV
R BIAS
acquire the wrong value, and should be minimized. 150
= 100k
V
R BIAS
Speed/Power Programmability
100
The AD9240’s maximum conversion rate and associated power 2 4 6 8 10 12 14 16 18 20
dissipation can be set using the part’s BIAS pin. A simplified CLOCK FREQUENCY – MHz

diagram of the on-chip circuitry associated with the BIAS pin is Figure 22. Power Dissipation vs. Clock Frequency for
shown in Figure 20. Varying RBIAS Values

ADCBIAS
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 23, a simplified model of the AD9240, highlights the rela-
BIAS
tionship between the analog inputs, VINA, VINB, and the ref-
erence voltage, VREF. Like the voltage applied to the top of
I FIXED RBIAS the resistor ladder in a flash A/D converter, the value VREF defines
AD9240 the maximum input voltage to the A/D core. The minimum input
voltage to the A/D core is automatically defined to be –VREF.
Figure 20.
The value of RBIAS can be varied over a limited range to set the AD9240 +VREF
VINA
maximum sample rate and power dissipation of the AD9240. A
VCORE 14
typical plot of S/(N+D) @ fIN = Nyquist vs. fCLK at varying A/D
CORE
RBIAS is shown in Figure 21. A similar plot of power vs. fCLK
at varying RBIAS is shown in Figure 22. These plots indicate VINB –VREF
typical performance vs. RBIAS. Note that all other plots and
specifications in this data sheet reflect performance at a fixed Figure 23. Equivalent Functional Input Circuit
RBIAS = 2 kΩ.

–8– REV. B
 AD9240
The addition of a differential input structure gives the user an The input SHA of the AD9240 is optimized to meet the perfor-
additional level of flexibility that is not possible with traditional mance requirements for some of the most demanding commu-
flash converters. The input stage allows the user to easily con- nication, imaging, and data acquisition applications while
figure the inputs for either single-ended operation or differential maintaining low power dissipation. Figure 25 is a graph of the
operation. The A/D’s input structure allows the dc offset of the full-power bandwidth of the AD9240, typically 60 MHz. Note
input signal to be varied independently of the input span of the that the small signal bandwidth is the same as the full-power
converter. Specifically, the input to the A/D core is the differ- bandwidth. The settling time response to a full-scale stepped
ence of the voltages applied at the VINA and VINB input pins. input is shown in Figure 26 and is typically less than 40 ns to
0.0025%. The low input referred noise of 0.36 LSB’s rms is
Therefore, the equation, displayed via a grounded histogram and is shown in Figure 13.
VCORE = VINA – VINB (1)
1
defines the output of the differential input stage and provides 0
the input to the A/D core. –1
The voltage, VCORE , must satisfy the condition, –2

–VREF ≤ VCORE ≤ VREF

AMPLITUDE – dB
–3
(2) –4

where VREF is the voltage at the VREF pin. –5

While an infinite combination of VINA and VINB inputs exist –6

that satisfy Equation 2, there is an additional limitation placed –7

on the inputs by the power supply voltages of the AD9240. The –8

power supplies bound the valid operating range for VINA and –9
VINB. The condition, –10
1 10 100
AVSS – 0.3 V < VINA < AVDD + 0.3 V FREQUENCY – MHz
(3)
Figure 25. Full-Power Bandwidth
AVSS – 0.3 V < VINB < AVDD + 0.3 V
16000
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa-
tions 2 and 3. 12000

For additional information showing the relationship between

VINA, VINB, VREF and the digital output of the AD9240, see
CODE

8000
Table IV.
Refer to Table I and Table II for a summary of the various
analog input and reference configurations. 4000

ANALOG INPUT OPERATION

Figure 24 shows the equivalent analog input of the AD9240
which consists of a differential sample-and-hold amplifier (SHA). 0
0 10 20 30 40 50 60 70 80
The differential input structure of the SHA is highly flexible, SETTLING TIME – ns

allowing the devices to be easily configured for either a differen- Figure 26. Settling Time
tial or single-ended input. The dc offset, or common-mode
voltage, of the input(s) can be set to accommodate either single- The SHA’s optimum distortion performance for a differential or
supply or dual supply systems. Note also that the analog inputs, single-ended input is achieved under the following two condi-
VINA and VINB, are interchangeable with the exception that tions: (1) the common-mode voltage is centered around mid-
reversing the inputs to the VINA and VINB pins results in a supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input
polarity inversion. signal voltage span of the SHA is set at its lowest (i.e., 2 V input
span). This is due to the sampling switches, QS1, being CMOS
CH switches whose RON resistance is very low but has some signal
dependency which causes frequency dependent ac distortion
QS2
CPIN+
while the SHA is in the track mode. The RON resistance of a
QS1 CS CMOS switch is typically lowest at its midsupply but increases
CPAR
VINA
symmetrically as the input signal approaches either AVDD or
QH1 CS
QS1 AVSS. A lower input signal voltage span centered at midsupply
VINB
CPIN– reduces the degree of RON modulation.
QS2
CPAR
CH

Figure 24. Simplified Input Circuit

REV. B –9–
AD9240
VCC
Figure 27 compares the AD9240’s THD vs. frequency perfor- AD9240
RS*
mance for a 2 V input span with a common-mode voltage of VINA
1 V and 2.5 V. Note the difference in the amount of degrada- RS*
VINB
tion in THD performance as the input frequency increases. VEE
Similarly, note how the THD performance at lower frequencies VREF
becomes less sensitive to the common-mode voltage. As the 10mF 0.1mF
SENSE
input frequency approaches dc, the distortion will be domi-
nated by static nonlinearities such as INL and DNL. It is REFCOM

important to note that these dc static nonlinearities are inde-

pendent of any RON modulation. *OPTIONAL SERIES RESISTOR

Figure 28. Series Resistor Isolates Switched-Capacitor

–50 SHA Input from Op Amp. Matching Resistors Improve
SNR Performance
The optimum size of this resistor is dependent on several fac-
–60
tors, which include the AD9240 sampling rate, the selected op
amp and the particular application. In most applications, a
30 Ω to 50 Ω resistor is sufficient; however, some applications
THD – dB

–70 may require a larger resistor value to reduce the noise band-
width or possibly limit the fault current in an overvoltage
VCM = 1.0V condition. Other applications may require a larger resistor value
–80 as part of an antialiasing filter. In any case, since the THD
performance is dependent on the series resistance and the above
VCM = 2.5V mentioned factors, optimizing this resistor value for a given
–90 application is encouraged.
0.1 1 10 20
FREQUENCY – MHz A slight improvement in SNR performance and dc offset
Figure 27. THD vs. Frequency for VCM = 2.5 V and 1.0 V performance is achieved by matching the input resistance con-
(AIN = –0.5 dB, Input Span = 2.0 V p-p) nected to VINA and VINB. The degree of improvement is de-
Due to the high degree of symmetry within the SHA topology, a pendent on the resistor value and the sampling rate. For series
significant improvement in distortion performance for differen- resistor values greater than 100 Ω, the use of a matching resis-
tial input signals with frequencies up to and beyond Nyquist can tor is encouraged.
be realized. This inherent symmetry provides excellent cancella- The noise or small-signal bandwidth of the AD9240 is the same
tion of both common-mode distortion and noise. Also, the as its full-power bandwidth. For noise sensitive applications, the
required input signal voltage span is reduced a factor of two excessive bandwidth may be detrimental and the addition of a
which further reduces the degree of RON modulation and its series resistor and/or shunt capacitor can help limit the wide-
effects on distortion. band noise at the A/D’s input by forming a low-pass filter. Note,
The optimum noise and dc linearity performance for either however, that the combination of this series resistance with the
differential or single-ended inputs is achieved with the largest equivalent input capacitance of the AD9240 should be evalu-
input signal voltage span (i.e., 5 V input span) and matched ated for those time-domain applications that are sensitive to the
input impedance for VINA and VINB. Note that only a slight input signal’s absolute settling time. In applications where har-
degradation in dc linearity performance exists between the monic distortion is not a primary concern, the series resistance
2 V and 5 V input span as specified in the AD9240 DC may be selected in combination with the SHA’s nominal 16 pF
SPECIFICATIONS. of input capacitance to set the filter’s 3 dB cutoff frequency.
Referring to Figure 24, the differential SHA is implemented A better method of reducing the noise bandwidth, while possi-
using a switched-capacitor topology. Hence, its input imped- bly establishing a real pole for an antialiasing filter, is to add
ance and its subsequent effects on the input drive source should some additional shunt capacitance between the input (i.e.,
be understood to maximize the converter’s performance. The VINA and/or VINB) and analog ground. Since this additional
combination of the pin capacitance, CPIN, parasitic capacitance shunt capacitance combines with the equivalent input capaci-
CPAR, and the sampling capacitance, CS, is typically less than tance of the AD9240, a lower series resistance can be selected to
16 pF. When the SHA goes into track mode, the input source establish the filter’s cutoff frequency while not degrading the
must charge or discharge the voltage stored on CS to the new distortion performance of the device. The shunt capacitance
input voltage. This action of charging and discharging CS which also acts as a charge reservoir, sinking or sourcing the additional
is approximately 4 pF, averaged over a period of time and for a charge required by the hold capacitor, CH, further reducing
given sampling frequency, FS, makes the input impedance ap- current transients seen at the op amp’s output.
pear to have a benign resistive component (i.e., 83 kΩ at FS = The effect of this increased capacitive load on the op amp driv-
10 MSPS). However, if this action is analyzed within a sam- ing the AD9240 should be evaluated. To optimize performance
pling period (i.e., T = <1/FS), the input impedance is dynamic when noise is the primary consideration, increase the shunt
due to the instantaneous requirement of charging and discharg- capacitance as much as the transient response of the input signal
ing CS. A series resistor inserted between the input drive source will allow. Increasing the capacitance too much may adversely
and the SHA input as shown in Figure 28 provides effective affect the op amp’s settling time, frequency response and distor-
isolation. tion performance.

–10– REV. B
 AD9240
Table I. Analog Input Configuration Summary

Input Input Input Range (V) Figure

Connection Coupling Span (V) VINA1 VINB1 # Comments
Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum THD
and noise performance, requires ± 5 V op amp.
2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to
2 × VREF increase in dynamic range. Headroom/settling time requirements
of ± 5 V op amp should be evaluated.
5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance
to improves while THD performance degrades as VREF increases
2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode level
2 × VREF 0 to 2 × VREF not biased at optimum midsupply level (i.e., 2.5 V).
5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance.
2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with VREF = 1.
to Noise performance improves while THD performance degrades as
2.5 + VREF VREF increases to 2.5 V.
Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well beyond the
DC A/Ds Nyquist frequency.
2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale
to to THD and SFDR performance can be traded off for better noise
2.5 + VREF/2 2.5 – VREF/2 performance.
5 1.25 to 3.75 3.75 to 1.25 29–31 Widest dynamic range (i.e., ENOBs) due to optimum noise
performance.
1
VINA and VINB can be interchanged if signal inversion is required.

Table II. Reference Configuration Summary

Reference Input Span (VINA–VINB)

Operating Mode (V p-p) Required VREF (V) Connect To
INTERNAL 2 1 SENSE VREF
INTERNAL 5 2.5 SENSE REFCOM
INTERNAL 2 ≤ SPAN ≤ 5 AND 1 ≤ VREF ≤ 2.5 AND R1 VREF AND SENSE
SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM
EXTERNAL 2 ≤ SPAN ≤ 5 1 ≤ VREF ≤ 2.5 SENSE AVDD
(NONDYNAMIC) VREF EXT. REF.
EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD
(DYNAMIC) Externally Driven VREF REFCOM
EXT. REF. 1 CAPT
EXT. REF. 2 CAPB

REV. B –11–
AD9240
REFERENCE OPERATION The actual reference voltages used by the internal circuitry of
The AD9240 contains an onboard bandgap reference that pro- the AD9240 appear on the CAPT and CAPB pins. For proper
vides a pin-strappable option to generate either a 1 V or 2.5 V operation when using the internal or an external reference, it is
output. With the addition of two external resistors, the user can necessary to add a capacitor network to decouple these pins.
generate reference voltages other than 1 V and 2.5 V. Another Figure 30 shows the recommended decoupling network. This
alternative is to use an external reference for designs requiring capacitive network performs the following three functions: (1)
enhanced accuracy and/or drift performance. See Table II for a along with the reference amplifier, A2, it provides a low source
summary of the pin-strapping options for the AD9240 reference impedance over a large frequency range to drive the A/D inter-
configurations. nal circuitry, (2) it provides the necessary compensation for A2
Figure 29 shows a simplified model of the internal voltage and (3) it bandlimits the noise contribution from the reference.
reference of the AD9240. A pin-strappable reference ampli- The turn-on time of the reference voltage appearing between
fier buffers a 1 V fixed reference. The output from the refer- CAPT and CAPB is approximately 15 ms and should be evalu-
ence amplifier, A1, appears on the VREF pin. The voltage on ated in any power-down mode of operation.
the VREF pin determines the full-scale input span of the A/D. 0.1mF
This input span equals, CAPT
Full-Scale Input Span = 2 × VREF AD9240 0.1mF 10mF

The voltage appearing at the VREF pin as well as the state of CAPB
the internal reference amplifier, A1, are determined by the volt- 0.1mF

age appearing at the SENSE pin. The logic circuitry contains

Figure 30. Recommended CAPT/CAPB Decoupling Network
two comparators which monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V) The A/D’s input span may be varied dynamically by changing
controls the position of the switch within the feedback path of the differential reference voltage appearing across CAPT and
A1. If the SENSE pin is tied to REFCOM, the switch is con- CAPB symmetrically around 2.5 V (i.e., midsupply). To change
nected to the internal resistor network thus providing a VREF of the reference at speeds beyond the capabilities of A2, it will be
2.5 V. If the SENSE pin is tied to the VREF pin via a short or necessary to drive CAPT and CAPB with two high speed, low
resistor, the switch is connected to the SENSE pin. A short will noise amplifiers. In this case, both internal amplifiers (i.e., A1
provide a VREF of 1.0 V while an external resistor network will and A2) must be disabled by connecting SENSE to AVDD and
provide an alternative VREF between 1.0 V and 2.5 V. VREF to REFCOM and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
The second comparator controls internal circuitry that will
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec-
disable the reference amplifier if the SENSE pin is tied AVDD.
tively, where the input span can be varied between 2 V and 5 V.
Disabling the reference amplifier allows the VREF pin to be
Note that those samples within the pipeline A/D during any
driven by an external voltage reference.
reference transition will be corrupted and should be discarded.

AD9240
TO
A/D
5kV
5kV CAPT

A2

5kV
CAPB
5kV
DISABLE LOGIC
A2

VREF
A1
1V
7.5kV

SENSE
DISABLE 5kV
LOGIC
A1 REFCOM

Figure 29. Equivalent Reference Circuit

–12– REV. B
 AD9240
DRIVING THE ANALOG INPUTS VCC AVDD

INTRODUCTION RS1 D2 RS2

30V 1N4148 20V
The AD9240 has a highly flexible input structure allowing it to AD9240
D1
interface with single-ended or differential input interface cir- 1N4148
cuitry. The applications shown in sections Driving the Analog VEE
Inputs and Reference Configurations, along with the informa- Figure 31. Simple Clamping Circuit
tion presented in the Input and Reference Overview section of
this data sheet, give examples of both single-ended and differen- DIFFERENTIAL MODE OF OPERATION
tial operation. Refer to Tables I and II for a list of the different Since not all applications have a signal preconditioned for
possible input and reference configurations and their associated differential operation, there is often a need to perform a
figures in the data sheet. single-ended-to-differential conversion. A single-ended-to-
The optimum mode of operation, analog input range and asso- differential conversion can be realized with an RF transformer
ciated interface circuitry will be determined by the particular or a dual op amp differential driver. The optimum method
applications performance requirements as well as power supply depends on whether the application requires the input signal to
options. For example, a dc coupled single-ended input may be be ac or dc coupled to AD9240.
appropriate for many data acquisition and imaging applications. AC Coupling via an RF Transformer
Also, many communication applications which require a dc An RF transformer with a center tap can be used to generate
coupled input for proper demodulation can take advantage of differential inputs for the AD9240. It provides all of the benefits
the excellent single-ended distortion performance of the AD9240. of operating the ADC in the differential mode while contribut-
The input span should be configured such that the system’s ing no additional noise and minimal distortion. As a result, an
performance objectives and the headroom requirements of the RF transformer is recommended in high frequency applica-
driving op amp are simultaneously met. tions, especially undersampling, in which the performance of
Alternatively, the differential mode of operation provides the a dual op amp differential driver may not be adequate. An RF
best THD and SFDR performance over a wide frequency range. transformer has the added benefit of providing electrical isola-
A transformer coupled differential input should be considered tion between the signal source and the ADC. However, since the
for the most demanding spectral-based applications which allow lower cutoff frequency of most RF transformers is nominally a
ac coupling (e.g., Direct IF to Digital Conversion). The dc- few 100 kHz, a dual op amp differential driver may be more suit-
coupled differential mode of operation also provides an enhance- able in ac-coupling applications, where the spectral content of the
ment in distortion and noise performance at higher input spans. input signal falls below the cutoff frequency of a suitable RF
Furthermore, it allows the AD9240 to be configured for a 5 V transformer.
span using op amps specified for +5 V or ± 5 V operation. Figure 32 is a suggested transformer circuit using a Mini-
Single-ended operation requires that VINA be ac or dc coupled Circuits RF transformer, model #T4-6T, which has an imped-
to the input signal source while VINB of the AD9240 be biased ance ratio of four (turns ratio of 2). The 1:4 impedance ratio
to the appropriate voltage corresponding to a midscale code requires the 200 Ω secondary termination for optimum power
transition. Note that signal inversion may be easily accom- transfer and VSWR. The centertap of the transformer provides
plished by transposing VINA and VINB. a convenient means of level-shifting the input signal to a de-
sired common-mode voltage. Optimum performance can be
Differential operation requires that VINA and VINB be simulta-
realized when the centertap is tied to CML of the AD9240
neously driven with two equal signals that are in and out of
which is the common-mode bias level of the internal SHA.
phase versions of the input signal. Differential operation of the
AD9240 offers the following benefits: (1) Signal swings are
smaller and therefore linearity requirements placed on the input 50V
VINA

signal source may be easier to achieve, (2) Signal swings are CML
smaller and therefore may allow the use of op amps which 200V
0.1mF
AD9240
may otherwise have been constrained by headroom limitations,
VINB
(3) Differential operation minimizes even-order harmonic prod- MINI-CIRCUITS
ucts and (4) Differential operation offers noise immunity based T4-6T
on the device’s common-mode rejection as shown in Figure 16. Figure 32. Transformer Coupled Input
As is typical of most CMOS devices, exceeding the supply limits Transformers with other turns ratios may also be selected to
will turn on internal parasitic diodes resulting in transient cur- optimize the performance of a given application. For example, a
rents within the device. Figure 31 shows a simple means of given input signal source or amplifier may realize an improve-
clamping a dc coupled input with the addition of two series ment in distortion performance at reduced output power levels
resistors and two diodes. Note that a larger series resistor could and signal swings. Hence, selecting a transformer with a higher
be used to limit the fault current through D1 and D2 but should be impedance ratio (i.e., Mini-Circuits T16-6T with a 1:16 imped-
evaluated since it can cause a degradation in overall performance. ance ratio) effectively “steps up” the signal level, further reduc-
ing the driving requirements of the signal source.

REV. B –13–
AD9240
AC Coupling with Op Amps 390V
As previously stated, a dual op amp differential driver may be AVDD
more suitable in applications in which the spectral content of the 0.1mF
220V VCML–VIN
input signal falls below the cutoff frequency of a suitable RF 390V
AD9631
33V
transformer and/or the cost of an RF transformer and a low VINA
distortion driver for the transformer is prohibitive. 390V 390V
VIN AVDD
The ac-coupled differential driver shown in Figure 33 is best
suited for ± 5 V systems in which the input signal is ground 390V 390V
220V AD9240
referenced. In this case, VCM will be 0 V. This driver circuit can 0.1mF
VCML+VIN
AD9631
achieve performance similar to an RF transformer over the
33V
AD9240’s full Nyquist bandwidth of 5 MHz. However, unlike VINB
the RF transformer, the lower cutoff frequency can be arbitrarily 390V 390V 2.5kV

set low by adjusting the RC time constant formed by CC and 0.1mF

RB/2. CN, in combination with RS, can be used to limit the con-
tribution of op amp-generated noise at higher frequencies. Low 100V

cost, high performance dual op amps operating from ± 5 V such 0.1mF 1mF
CML
OP113
as the AD8056 and AD8058, are excellent choices for this appli-
cation and are capable of maintaining 78 dB SNR and 83 dB
THD at 1 MHz (5 V span). An optional resistor RO can be Figure 34. Differential Driver with Level-Shifting
added to U1B to achieve a similar group delay as U1A, potentially Single Supply DC-Coupled Driver
improving overall distortion performance. A resistor divider net- The circuit of Figure 33 can be easily modified for a single
work formed by RB centers the inputs of the AD9240 around supply, dc-coupled application. This is done by biasing VCM to
AVDD/2 to achieve its optimum distortion performance. AVDD/2, the normal common-mode level in a single supply
system. Since the outputs of the op amps are centered at
VCM VCC AVDD/2, the ac coupling network of CC and RB can be removed.
U1A
RB With this done, the differential driving pair can now be run from
RS 5kV a single supply.
CC RB
0.1mF 5kV SINGLE-ENDED MODE OF OPERATION
The AD9240 can be configured for single-ended operation
CN using dc or ac coupling. In either case, the input of the A/D
SOURCE VCC
must be driven from an operational amplifier that will not de-
RB
grade the A/D’s performance. Because the A/D operates from a
5kV
RO U1B single supply, it will be necessary to level-shift ground-based
RS RB
CC
5kV
bipolar signals to comply with its input requirements. Both dc
0.1mF
and ac coupling provide this necessary function, but each
method results in different interface issues which may influence
Figure 33. AC Coupling of Op Amps the system design and performance.
DC Coupling with Op Amps
The dc-coupled differential driver in Figure 34 is best suited for DC COUPLING AND INTERFACE ISSUES
± 5 V systems in which the input signal is ground referenced and Many applications require the analog input signal to be dc
optimum distortion performance is desired. This driver circuit coupled to the AD9240. An operational amplifier can be con-
provides the ability to level-shift the input signal to within the figured to rescale and level-shift the input signal so it is compat-
common-mode range of the AD9240. The two op amps are ible with the selected input range of the A/D. The input range
configured as matched differential amps with the input signal to the A/D should be selected on the basis of system perfor-
applied to opposing inputs to provide the differential output. mance objectives as well as the analog power supply availability
The common-mode offset voltage is applied to the noninverting since this will place certain constraints on the op amp selection.
resistor network, which provides the proper level shifting. The Many of the new high performance op amps are specified for
AD9631 is given as the amplifier of choice in this application only ± 5 V operation and have limited input/output swing capa-
due to its superior distortion performance for relatively large bilities. Hence, the selected input range of the AD9240 should
output swings and wide bandwidth. If cost or space are factors, be sensitive to the headroom requirements of the particular op
the AD8056 dual op amp will save on both, but at the cost of amp to prevent clipping of the signal. Also, since the output of a
slightly increased distortion with large signal levels. Figure 34 dual supply amplifier can swing below –0.3 V, clamping its
also illustrates the use of protection diodes, which are used to output should be considered in some applications.
protect the AD9240 from any fault condition in which the op
amps outputs inadvertently go above VDD or below GND. In some applications, it may be advantageous to use an op amp
specified for single supply +5 V operation since it will inherently
limit its output swing to within the power supply rails. Rail-to-
rail output amplifiers such as the AD8041 allow the AD9240 to
be configured with larger input spans which improves the noise
performance.

–14– REV. B
 AD9240
If the application requires the largest single-ended input range 500V*
(i.e., 0 V to 5 V) of the AD9240, the op amp will require larger +VCC
supplies to drive it. Various high speed amplifiers in the Op 0.1mF
Amp Selection Guide of this data sheet can be selected to
NC
accommodate a wide range of supply options. Once again, +VREF
500V*
0VDC
clamping the output of the amplifier should be considered for –VREF RS
these applications. Alternatively, a single-ended to differential RP** 500V*
A1 VINA

op amp driver circuit using the AD8042 could be used to AVDD

achieve the 5 V input span while operating from a single +5 V 0.1mF 500V* AD9240
NC
supply as discussed in the previous section.
RS
Two dc coupled op amp circuits using a noninverting and VREF VINB

inverting topology are discussed below. Although not shown, *OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D
**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE
the noninverting and inverting topologies can be easily config-
ured as part of an antialiasing filter by using a Sallen-Key or Figure 36. Single-Ended Input With DC-Coupled Level-Shift
Multiple-Feedback topology, respectively. An additional R-C
network can be inserted between the op amp’s output and the AC COUPLING AND INTERFACE ISSUES
AD9240 input to provide a real pole. For applications where ac coupling is appropriate, the op amp’s
output can be easily level-shifted to the common-mode voltage,
Simple Op Amp Buffer
VCM, of the AD9240 via a coupling capacitor. This has the
In the simplest case, the input signal to the AD9240 will already
advantage of allowing the op amps common-mode level to be
be biased at levels in accordance with the selected input range.
symmetrically biased to its midsupply level (i.e., (VCC + VEE)/
It is simply necessary to provide an adequately low source im-
2). Op amps that operate symmetrically with respect to their
pedance for the VINA and VINB analog input pins of the A/D.
power supplies typically provide the best ac performance as well
Figure 35 shows the recommended configuration for a single-
as greatest input/output span. Hence, various high speed/
ended drive using an op amp. In this case, the op amp is shown
performance amplifiers that are restricted to +5 V/–5 V op-
in a noninverting unity gain configuration driving the VINA pin.
eration and/or specified for +5 V single-supply operation can be
The internal reference drives the VINB pin. Note that the addi-
easily configured for the 5 V or 2 V input span of the AD9240,
tion of a small series resistor of 30 Ω to 50 Ω connected to VINA
respectively. The best ac distortion performance is achieved
and VINB will be beneficial in nearly all cases. Refer to the
when the A/D is configured for a 2 V input span and common-
Analog Input Operation section for a discussion on resistor
mode voltage of 2.5 V. Note that differential transformer
selection. Figure 35 shows the proper connection for a 0 V to
coupling, which is another form of ac coupling, should be
5 V input range. Alternative single ended input ranges of 0 V to
considered for optimum ac performance.
2 × VREF can also be realized with the proper configuration of
VREF (refer to the section, Using the Internal Reference). Simple AC Interface
Figure 37 shows a typical example of an ac-coupled, single-
+V ended configuration. The bias voltage shifts the bipolar,
5V AD9240 ground-referenced input signal to approximately VREF. The
RS
0V U1 VINA value for C1 and C2 will depend on the size of the resistor, R.
RS
VINB The capacitors, C1 and C2, are typically a 0.1 µF ceramic and
–V 2.5V
VREF 10 µF tantalum capacitor in parallel to achieve a low cutoff
10mF 0.1mF SENSE
frequency while maintaining a low impedance over a wide fre-
quency range. The combination of the capacitor and the resistor
form a high-pass filter with a high-pass –3 dB frequency deter-
Figure 35. Single-Ended AD9240 Op Amp Drive Circuit mined by the equation,
Op Amp with DC Level-Shifting f–3 dB = 1/(2 × π × R × (C1 + C2))
Figure 36 shows a dc-coupled level-shifting circuit employing an
op amp, A1, to sum the input signal with the desired dc offset. C1
+5V
Configuring the op amp in the inverting mode with the given +VREF AD9240
C2 RS
resistor values results in an ac signal gain of –1. If the signal 0V VIN
–VREF VINA
inversion is undesirable, interchange the VINA and VINB con- R
RS
nections to reestablish the original signal polarity. The dc volt- VINB
–5V
age at VREF sets the common-mode voltage of the AD9240. For VREF
example, when VREF = 2.5 V, the output level from the op amp C2 C1 SENSE
will also be centered around 2.5 V. The use of ratio matched,
thin-film resistor networks will minimize gain and offset errors.
Figure 37. AC-Coupled Input
An optional pull-up resistor, RP, may also be used to reduce the
output load on VREF to ±1 mA. The low impedance VREF voltage source biases both the VINB
input and provides the bias voltage for the VINA input. Figure
37 shows the VREF configured for 2.5 V. Thus the input range
of the A/D is 0 V to 5 V. Other input ranges could be selected
by changing VREF but the A/D’s distortion performance will

REV. B –15–
AD9240
degrade slightly as the input common-mode voltage deviates AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%,
from its optimum level of 2.5 V. ±5 V Supplies
Alternative AC Interface Best Applications: Best AC Specs, Low Noise,
Figure 38 shows a flexible ac-coupled circuit which can be con- AC-Coupled
figured for different input spans. Since the common-mode Limits: Usable Input/Output Range, Power
voltage of VINA and VINB are biased to midsupply indepen- Consumption
dent of VREF, VREF can be pin-strapped or reconfigured to AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%,
achieve input spans between 2 V and 5 V p-p. The AD9240’s ± 5 V Supplies
CMRR along with the symmetrical coupling R-C networks will Best Applications: Good AC Specs, Low Noise,
reject both power supply variations and noise. The resistors, R, AC-Coupled
establish the common-mode voltage. They may have a high value Limits: THD > 5 MHz, Usable Input Range
(e.g., 5 kΩ) to minimize power consumption and establish a low
AD8042: Dual AD8041
cutoff frequency. The capacitors, C1 and C2, are typically a
Best Applications: Differential and/or Low Imped-
0.1 µF ceramic and 10 µF tantalum capacitor in parallel to
ance Input Drivers
achieve a low cutoff frequency while maintaining a low imped-
Limits: Noise with 2 V Input Range
ance over a wide frequency range. RS isolates the buffer ampli-
fier from the A/D input. The optimum performance is achieved REFERENCE CONFIGURATIONS
when VINA and VINB are driven via symmetrical networks. For the purpose of simplicity, the figures associated with this
The high pass f –3 dB point can be approximated by the equation, section on internal and external reference operation do not
f–3 dB = 1/(2 × π × R/2 × (C1 + C2)) show recommended matching series resistors for VINA and
VINB. Please refer to section Driving the Analog Inputs, Intro-
+5V duction, for a discussion of this topic. The figures do not show
+5V
AD9240 the decoupling network associated with the CAPT and CAPB
C1 R
VIN RS pins. Please refer to the Reference Operation section for a discus-
VINA
sion of the internal reference circuitry and the recommended
C2 R
decoupling network shown in Figure 30.
–5V
R RS
+5V VINB
USING THE INTERNAL REFERENCE
R C2 C1 Single-Ended Input with 0 to 2 ⴛ VREF Range
Figure 39 shows how to connect the AD9240 for a 0 V to 2 V or
0 V to 5 V input range via pin strapping the SENSE pin. An
intermediate input range of 0 to 2 × VREF can be established
Figure 38. AC-Coupled Input-Flexible Input Span, using the resistor programmable configuration in Figure 41 and
VCM = 2.5 V connecting VREF to VINB.
OP AMP SELECTION GUIDE
Op amp selection for the AD9240 is highly dependent on a 2xVREF
VINA
particular application. In general, the performance requirements 0V
VINB
of any given application can be characterized by either time 10mF 0.1mF
domain or frequency domain parameters. In either case, one VREF
should carefully select an op amp that preserves the perfor- SHORT FOR 0 TO 2V AD9240
INPUT SPAN
mance of the A/D. This task becomes challenging when one SENSE
considers the AD9240’s high performance capabilities coupled SHORT FOR 0 TO 5V
with other external system level requirements such as power INPUT SPAN
REFCOM
consumption and cost.
The ability to select the optimal op amp may be further compli-
Figure 39. Internal Reference (2 V p-p Input Span,
cated by limited power supply availability and/or limited accept-
VCM = 1 V, or 5 V p-p Input Span, VCM = 2.5 V)
able supplies for a desired op amp. Newer, high performance op
amps typically have input and output range limitations in accor- In either case, both the common-mode voltage and input span
dance with their lower supply voltages. As a result, some op are directly dependent on the value of VREF. More specifically,
amps will be more appropriate in systems where ac-coupling is the common-mode voltage is equal to VREF while the input
allowable. When dc-coupling is required, op amps without span is equal to 2 × VREF. Thus, the valid input range extends
headroom constraints such as rail-to-rail op amps or ones where from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output
larger supplies can be used should be considered. The following will be 0000 Hex; when VINA is ≥ 2 × VREF, the digital output
section describes some op amps currently available from Analog will be 3FFF Hex.
Devices. The system designer is always encouraged to contact Shorting the VREF pin directly to the SENSE pin places the
the factory or local sales office to be updated on Analog De- internal reference amplifier in unity-gain mode and the result-
vices’ latest amplifier product offerings. Highlights of the areas ant VREF output is 1 V. The valid input range is, therefore, 0 V
where the op amps excel and where they may limit the perfor- to 2 V. Shorting the SENSE pin directly to the REFCOM pin
mance of the AD9240 are also included. configures the internal reference amplifier for a gain of 2.5 and

–16– REV. B
 AD9240
the resultant VREF output is 2.5 V. The valid input range thus the example shown, the valid input signal range for VINA is 1 V
becomes 0 V to 5 V. The VREF pin should be bypassed to the to 4 V since VINB is set to an external, low impedance 2.5 V
REFCOM pin with a 10 µF tantalum capacitor in parallel with a source. The VREF pin should be bypassed to the REFCOM pin
low-inductance 0.1 µF ceramic capacitor. with a 10 µF tantalum capacitor in parallel with a low induc-
Single-Ended or Differential Input, V CM = 2.5 V tance 0.1 µF ceramic capacitor.
Figure 37 shows the single-ended configuration that gives the
4V
best SINAD performance. To optimize dynamic specifications, VINA
1V
center the common-mode voltage of the analog input at
2.5V VINB
approximately by 2.5 V by connecting VINB to VREF, a low- 1.5V
impedance 2.5 V source. As described above, shorting the R1 C1
VREF
10mF 0.1mF AD9240
SENSE pin directly to the REFCOM pin results in a 2.5 V 2.5kV 0.1mF
SENSE
reference voltage and a 5 V p-p input span. The valid range R2
5kV
for input signals is 0 V to 5 V. The VREF pin should be by-
passed to the REFCOM pin with a 10 µF tantalum capacitor in REFCOM

parallel with a low inductance 0.1 µF ceramic capacitor.

This reference configuration could also be used for a differential Figure 41. Resistor Programmable Reference (3 V p-p
input in which VINA and VINB are driven via a transformer as Input Span, VCM = 2.5 V)
shown in Figure 32. In this case, the common-mode voltage,
VCM, is set at midsupply by connecting the transformer’s center USING AN EXTERNAL REFERENCE
tap to CML of the AD9240. VREF can be configured for 1 V Using an external reference may enhance the dc performance of
or 2.5 V by connecting SENSE to either VREF or REFCOM the AD9240 by improving drift and accuracy. Figures 42
respectively. Note that the valid input range for each of the through 44 show examples of how to use an external reference
differential inputs is one half of the single-ended input and thus with the A/D. Table III is a list of suitable voltage references
becomes VCM – VREF/2 to VCM + VREF/2. from Analog Devices. To use an external reference, the user
must disable the internal reference amplifier and drive the
5V VREF pin. Connecting the SENSE pin to AVDD disables the
VINA
0V internal reference amplifier.
VINB
2.5V AD9240
VREF Table III. Suitable Voltage References
10mF 0.1mF SENSE
Initial Operating
REFCOM
Output Drift Accuracy Current
Voltage (ppm/ⴗC) % (max) (␮A)
Figure 40. Internal Reference—5 V p-p Input Span, Internal 1.00 26 1.4 N/A
VCM = 2.5 V REF191 2.048 5–25 0.1–0.5 45
Resistor Programmable Reference Internal 2.50 26 1.4 N/A
Figure 41 shows an example of how to generate a reference REF192 2.50 5–25 0.08–0.4 45
voltage other than 1 V or 2.5 V with the addition of two external AD780 2.50 3–7 0.04–0.2 1000
resistors and a bypass capacitor. Use the equation,
The AD9240 contains an internal reference buffer, A2 (see
VREF = 1 V × (1 + R1/R2), Figure 29), that simplifies the drive requirements of an external
to determine appropriate values for R1 and R2. These resistors reference. The external reference must be able to drive a ≈5 kΩ
should be in the 2 kΩ to 100 kΩ range. For the example (± 20%) load. Note that the bandwidth of the reference buffer is
shown, R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equa- deliberately left small to minimize the reference noise contribu-
tion above, the resultant reference voltage on the VREF pin is tion. As a result, it is not possible to change the reference volt-
1.5 V. This sets the input span to be 3 V p-p. To assure stabil- age rapidly in this mode without the removal of the CAPT/
ity, place a 0.1 µF ceramic capacitor in parallel with R1. CAPB Decoupling Network, and driving these pins directly.
The common-mode voltage can be set to VREF by connecting
VINB to VREF to provide an input span of 0 to 2 × VREF.
Alternatively, the common-mode voltage can be set to 2.5 V
by connecting VINB to a low impedance 2.5 V source. For

REV. B –17–
AD9240
Variable Input Span with V CM = 2.5 V 3.75V
VINA
Figure 42 shows an example of the AD9240 configured for an 1.25V
input span of 2 × VREF centered at 2.5 V. An external 2.5 V
820V
1kV +5V
reference drives the VINB pin thus setting the common-mode
0.1mF VINB
voltage at 2.5 V. The input span can be independently set by a 1kV 10mF 0.1mF
voltage divider consisting of R1 and R2, which generates the 2N2222
1kV AD9240
VREF signal. A1 buffers this resistor network and drives VREF. 1/2 316V
Choose this op amp based on accuracy requirements. It is OP282
7.5kV
essential that a minimum of a 10 µF capacitor in parallel with a +5V
1.225V
VREF
0.1 µF low inductance ceramic capacitor decouple the reference AD1580 10mF 0.1mF
+5V SENSE
output to ground.

2.5V+VREF Figure 44. External Reference Using the AD1580 and Low
2.5V VINA
2.5V–VREF Impedance Buffer

2.5V DIGITAL INPUTS AND OUTPUTS

+5V VINB
REF Digital Outputs
0.1mF 22mF R1 0.1mF
AD9240
The AD9240 output data is presented in positive true straight
A1 VREF binary for all input ranges. Table IV indicates the output data
0.1mF R2 formats for various input ranges regardless of the selected input
+5V SENSE range. A twos complement output data format can be created by
inverting the MSB.
Figure 42. External Reference, VCM = 2.5 V (2.5 V on VINB, Table IV. Output Data Format
Resistor Divider to Make VREF)
Single-Ended Input with 0 to 2 ⴛ VREF Range Input (V) Condition (V) Digital Output OTR
Figure 43 shows an example of an external reference driving VINA – VINB < –VREF 00 0000 0000 0000 1
both VINB and VREF. In this case, both the common mode VINA – VINB = –VREF 00 0000 0000 0000 0
voltage and input span are directly dependent on the value of VINA – VINB =0 10 0000 0000 0000 0
VREF. More specifically, the common-mode voltage is equal to VINA – VINB = +VREF – 1 LSB 11 1111 1111 1111 0
VREF while the input span is equal to 2 × VREF. Thus, the VINA – VINB ≥ +VREF 11 1111 1111 1111 1
valid input range extends from 0 to 2 × VREF. If, for example,
the REF191, a 2.048 external reference, were selected, the valid Out Of Range (OTR)
input range extends from 0 V to 4.096 V. In this case, 1 LSB of An out-of-range condition exists when the analog input voltage
the AD9240 corresponds to 0.250 mV. It is essential that a is beyond the input range of the converter. OTR is a digital
minimum of a 10 µF capacitor in parallel with a 0.1 µF low induc- output that is updated along with the data output corresponding
tance ceramic capacitor decouple the reference output to ground. to the particular sampled analog input voltage. Hence, OTR
has the same pipeline delay (latency) as the digital data. It is
2xREF LOW when the analog input voltage is within the analog input
VINA
0V range. It is HIGH when the analog input voltage exceeds the
input range as shown in Figure 45. OTR will remain HIGH
+5V VINB
VREF until the analog input returns within the input range and an-
0.1mF 10mF 0.1mF
AD9240 other conversion is completed. By logical ANDing OTR with
the MSB and its complement, overrange high or underrange low
VREF
0.1mF conditions can be detected. Table V is a truth table for the over/
underrange circuit in Figure 46 which uses NAND gates. Sys-
+5V SENSE tems requiring programmable gain conditioning of the AD9240
input signal can immediately detect an out-of-range condition,
Figure 43. Input Range = 0 V to 2 × VREF thus eliminating gain selection iterations. Also, OTR can be
used for digital offset and gain calibration.
Low Cost/Power Reference
The external reference circuit shown in Figure 44 uses a low cost +FS –1 1/2 LSB
OTR DATA OUTPUTS
1.225 V external reference (e.g., AD580 or AD1580) along with an
1 111111 1111 1111 OTR
op amp and transistor. The 2N2222 transistor acts in conjunction 0 111111 1111 1111
with 1/2 of an OP282 to provide a very low impedance drive for 0 111111 1111 1110
VINB. The selected op amp need not be a high speed op amp and –FS+1/2 LSB

may be selected based on cost, power and accuracy. 0 000000 0000 0001
0 000000 0000 0000
1 000000 0000 0000
–FS +FS
–FS –1/2 LSB +FS –1/2 LSB

Figure 45. Output Data Format

–18– REV. B
 AD9240
Table V. Out-of-Range Truth Table Most of the power dissipated by the AD9240 is from the analog
power supply; however, lower clock speeds will reduce digital
OTR MSB Analog Input Is current slightly. Figure 47 shows the relationship between power
0 0 In Range and clock rate.
0 1 In Range
400
1 0 Underrange
1 1 Overrange 380

360

MSB 340
OVER = “1”

POWER – mW
320
OTR
UNDER = “1” 300
MSB
280

Figure 46. Overrange or Underrange Logic 260

Digital Output Driver Considerations (DRVDD) 240

The AD9240 output drivers can be configured to interface with 220

+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V 200
2 4 6 8 10 12 14 16 18 20
respectively. The AD9240 output drivers are sized to provide
CLOCK FREQUENCY – MHz
sufficient output current to drive a wide variety of logic families;
large drive currents tend to cause glitches on the supplies and may Figure 47. Power Consumption vs. Clock Frequency
affect SINAD performance. Applications requiring the AD9240 to (RBIAS = 2 kΩ)
drive large capacitive loads or large fanout may require additional
decoupling capacitors on DRVDD. In extreme cases, external GROUNDING AND DECOUPLING
buffers or latches may be required. Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
Clock Input and Considerations
system. Multilayer printed circuit boards (PCBs) are recom-
The AD9240 internal timing uses the two edges of the clock
mended to provide optimal grounding and power schemes. The
input to generate a variety of internal timing signals. The clock
use of ground and power planes offers distinct advantages:
input must meet or exceed the minimum specified pulsewidth
high and low (tCH and tCL) specifications for the given A/D, as 1. The minimization of the loop area encompassed by a signal
defined in the Switching Specifications at the beginning of the and its return path.
data sheet, to meet the rated performance specifications. For 2. The minimization of the impedance associated with ground
example, the clock input to the AD9240 operating at 10 MSPS and power paths.
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified tCH and tCL is 45 ns. 3. The inherent distributed capacitor formed by the power
For clock rates below 10 MSPS, the duty cycle may deviate plane, PCB insulation and ground plane.
from this range to the extent that both tCH and tCL are satisfied. These characteristics result in both a reduction of electro-
All high speed high resolution A/Ds are sensitive to the quality magnetic interference (EMI) and an overall improvement in
of the clock input. The degradation in SNR at a given full-scale performance.
input frequency (fIN), due only to aperture jitter (tA), can be It is important to design a layout that prevents noise from coupling
calculated with the following equation: onto the input signal. Digital signals should not be run in paral-
SNR = 20 log10 [1/(2 π fIN tA)] lel with input signal traces and should be routed away from the
input circuitry. While the AD9240 features separate analog and
In the equation, the rms aperture jitter, tA, represents the root- digital ground pins, it should be treated as an analog component.
sum square of all the jitter sources, which include the clock The AVSS, DVSS and DRVSS pins must be joined together
input, analog input signal and A/D aperture jitter specification. directly under the AD9240. A solid ground plane under the A/D
For example, if a 5.0 MHz full-scale sine wave is sampled by an is acceptable if the power and ground return currents are care-
A/D with a total rms jitter of 15 ps, the SNR performance of the fully managed. Alternatively, the ground plane under the A/D
A/D will be limited to 66.5 dB. Undersampling applications are may contain serrations to steer currents in predictable directions
particularly sensitive to jitter. where cross-coupling between analog and digital would other-
The clock input should be treated as an analog signal in cases wise be unavoidable. The AD9240/EB ground layout, shown in
where aperture jitter may affect the dynamic range of the Figure 57, depicts the serrated type of arrangement. The analog
AD9240. As such, supplies for clock drivers should be separated and digital grounds are connected by a jumper below the A/D.
from the A/D output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal controlled oscil-
lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing or other method), it
should be retimed by the original clock at the last step.

REV. B –19–
AD9240
Analog and Digital Supply Decoupling output bits: large capacitive loads are to be avoided. Note that the
The AD9240 features separate analog and digital supply and internal correction logic of the AD9240 is referenced DVDD
ground pins, helping to minimize digital corruption of sensitive while the output drivers are referenced to DRVDD.
analog signals. The decoupling shown in Figure 51, a 0.1 µF ceramic chip
120
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
DVDD involving greater digital loads should consider increasing the
100
digital decoupling proportionally and/or using external buffers/
latches.
PSRR – dBFS

AVDD

80 DVDD DRVDD
0.1mF AD9240 0.1mF
DVSS DRVSS

60

Figure 51. Digital Supply Decoupling

40 A complete decoupling scheme will also include large tantalum
1 10 100
FREQUENCY – kHz
1000 or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. For more information regarding the
Figure 48. PSRR vs. Frequency placement of decoupling capacitors, refer to the AD9240/EB
Figure 48 shows the power supply rejection ratio vs. frequency schematic and layouts in Figures 54–58.
for a 200 mV p-p ripple applied to both AVDD and DVDD.
APPLICATIONS
In general, AVDD, the analog supply, should be decoupled to
Direct IF Down Conversion Using the AD9240
AVSS, the analog common, as close to the chip as physically
Sampling IF signals above an ADC’s baseband region (i.e., dc
possible. Figure 49 shows the recommended decoupling for the
to FS/2) is becoming increasingly popular in communication
analog supplies; 0.1 µF ceramic chip capacitors should provide
applications. This process is often referred to as Direct IF Down
adequately low impedance over a wide frequency range. Note
Conversion or Undersampling. There are several potential benefits
that the AVDD and AVSS pins are co-located on the AD9240
in using the ADC to alias (or mix) down a narrowband or wide-
to simplify the layout of the decoupling capacitors and provide
band IF signal. First and foremost is the elimination of a
the shortest possible PCB trace lengths. The AD9240/EB power
complete mixer stage with its associated amplifiers and filters
plane layout, shown in Figure 58, depicts a typical arrangement
reducing cost and power dissipation. Second is the ability to
using a multilayer PCB.
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
AVDD reduction, detection, etc. A detailed discussion on using this
0.1mF technique in digital receivers can be found in Analog Devices
AVSS
Application Notes AN-301 and AN-302.
AD9240
In Direct IF Down Conversion applications, one exploits the
AVDD
0.1mF inherent sampling process of an ADC in which an IF signal
AVSS lying outside the baseband region can be aliased back into the
baseband region in a similar manner that a mixer will downconvert
an IF signal. Similar to the mixer topology, an image rejection
Figure 49. Analog Supply Decoupling filter is required to limit other potential interfering signals from
The CML is an internal analog bias point used internally by the also aliasing back into the ADC’s baseband region. A tradeoff
AD9240. This pin must be decoupled with at least a 0.1 µF exists between the complexity of this image rejection filter and
capacitor as shown in Figure 50. The dc level of CML is ap- the sample rate as well as dynamic range of the ADC.
proximately AVDD/2. This voltage should be buffered if it is to Until recently, the actual implementation of Direct IF Down
be used for any external biasing. Conversion has been limited by the lack of cost-effective ADCs
with sufficiently wide dynamic range and high sample rates for
CML
IFs beyond 10.7 MHz. Since the performance of the AD9240
0.1mF AD9240 in the differential mode of operation extends well beyond its
baseband region, it may be well suited as a mix-down converter
in narrowband as well as some wideband applications. Also,
Figure 50. CML Decoupling with the full-power bandwidth of the AD9240 extending beyond
The digital activity on the AD9240 chip falls into two general 60 MHz, various IF frequencies exist over this frequency range
categories: correction logic and output drivers. The internal in which the AD9240 maintains excellent dynamic performance.
correction logic draws relatively small surges of current, mainly Figure 52 shows the AD9240 configured in an IF sampling
during the clock transitions. The output drivers draw large application at 37.5 MHz. To reduce the complexity of the
current impulses while the output bits are changing. The size digital demodulator in many quadrature demodulation applica-
and duration of these currents are a function of the load on the tions, the IF frequency and/or sample rate are selected such that

–20– REV. B
 AD9240
the bandlimited IF signal aliases back into the center of the ADC’s 80

baseband region (i.e. FS/4). At a sample rate of 10 MSPS, an

WORST CASE SPURIOUS AND SNR – dBc

70
image of the IF signal centered at 37.5 MHz will be aliased back
to 2.5 MHz which corresponds to one quarter of the sample rate 60
(i.e. FS/4). Note, the IF signal in this case will have undergone a SFDR w/5V SPAN
50
frequency inversion that may easily be corrected for in the digital SFDR w/2V SPAN SNR w/5V SPAN
domain. 40

SAW FILTER 30
OUTPUT G1 = 20dB SNR w/2V SPAN
G2 = 12dB
50V AD9240 20
50V AD8009 50V VINA
AD8009 10
200V CML
0.1mF
280V 0
200V
22.1V –80 –70 –60 –50 –40 –30 –20 –10 0
VINB
93.1V INPUT POWER LEVEL – dBFS
MINI-CIRCUITS
T4-6T Figure 53. Single-Tone SNR/SFDR vs. Input Amplitude
@ 37.45 MHz
Figure 52. Simplified AD9240 IF Sampling Circuit
Figure 54 compares the two tone SFDR performance of the
To maximize its distortion performance, the AD9240 is config-
AD9240 in the 2 V span with and without the use of the AD8009
ured in the differential mode using a transformer. Preceding the
gain stage. No degradation in distortion performance was noted
AD9240 is a bandpass filter and a 32 dB gain stage. A large
with the inclusion of the AD8009 gain stage provided that the
gain stage may be required to compensate for the high insertion
AD8009 2nd order distortion products are sufficiently attenu-
losses of a SAW filter used for image rejection. The gain stage
ated by the bandpass filter.
will also provide adequate isolation for the SAW filter from the
transient currents associated with AD9240’s input stage. 100
The gain stage can be realized using one or two cascaded AD8009 WORST CASE SPURIOUS – dBc AND dBFS
90
op amps. The AD8009 is a low cost current-feedback op amp
80 w/AD8009 – dBFS w/o AD8009 – dBFS
having a third order intercept of 33 dB for a gain of +10 MHz
at 37.5 MHz. A passive bandpass filter is required after the 70 w/AD8009 – dBc
AD8009 to reduce the resulting second order distortion prod- 60
ucts and limit its out-of-band noise. The specifications of this 50 w/o AD8009 – dBc
filter are application dependent and will affect both the total
40 85 dB REFERENCE LINE
distortion and noise performance of this circuit.
30
Figure 53 shows the single-tone SNR and SFDR performance of
20
the AD9240 configured in the 2 V and 5 V span without using
the AD8009 gain stage. Only a slight degradation in SNR perfor- 10

mance (i.e., 1 dB) was noted with the inclusion of the AD8009 0
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
gain stage and a bandpass filter. Note, the tradeoff in SNR and
INPUT POWER LEVEL (f1 = f2) – dBFS
SFDR (dBFS) performance between the 5 V and 2 V spans at
different signal levels. Figure 54. Two Tone SFDR vs. Input Amplitude
@ f1 = 36.40 MHz and f2 = 38.60 MHz

REV. B –21–
 JP7
+5VA R20 TP10
TP1 A C9 22.1V
0.1mF D13 13 J8
C8 A U5
TPC 0.1mF 13 12 R21 TP11
JP2 + C1 C2 22.1V
+5VA 10mF U6
TPD JP6 0.1mF 28 4 2 29 1
11 J8
16V A
AD9240
C41 JP3 U5 U5 G1 11 R22 TP12
R1 11 10 19
0.1mF TP24 9 8 JP15 G2 Y7 22.1V
10kV D7 9 12 9 J8
JP4 A A7 Y6

AVSS2
AVSS1

AVDD2
AVDD1
CLKB D8 8 13
32 25 A6 Y5 R23 TP13
R2 JP5 VREF OTR D9 7 14 22.1V
U1 JP16 A5 Y4
10kV 24 D13 ADC_CLK U8 D10 6 15 7 J8
6 5 A4 Y3
A AD9240MQFP BIT1 23 D12 CLK D11 5 16 R24 TP14
A BIT2 A3 Y2
31 22 D11 D12 4 17 22.1V
SENSE BIT3 C23 A2 Y1 5 J8
33 21 D10 J9 TP2 D13 3 Y0 18
REFCOM BIT4 0.1mF A1 R25 TP15
C3 + C5 20 D9 2
0.1mF C6 BIT5 CLKIN A0 20 +DRVDD 22.1V
10mF A 19 D8 10
0.1mF BIT6 GND +5VD 3 J8
16V 18 D7 R19 JP17
37 BIT7 50V C24 R26 TP16
CAPT 17 D6 A +5VA 74HC541N
BIT8 0.1mF JP18 22.1V
BIT9 16 D5 A 1 J8
A C4 36 U7
0.1mF CAPB BIT10 15 D4 R16 1 R27 TP3
39 G1 22.1V
CML CML BIT11 14 D3 5kV R40 19 11
41 13 D2 G2 Y7 33 J8
VINA BIT12 R17 CLK 9 12
42 12 D1 A7 Y6 R28 TP4
A C7 VINB BIT13 1kV CW D0 8 13
11 D0 A6 Y5 22.1V
0.1mF 35 BIAS BIT14 R41 D1 7 14 27 J8
A5 Y4
VINA2 D2 6 15 R29 TP5
7 R18 A4 Y3
A JP11 B RBIAS CLK D3 5 16 22.1V
VINA1 5kV A3 Y2
D4 4 17 25 J8
3 2 1 A2 Y1

DRVSS
18 R30 TP17

DVSS
DVDD

DRVDD
ADC_CLK A D5 3 A1 Y0
VINB2 22.1V
5 1 6 3 D6 2 A0 23 J8
A JP12 B 10 20 +DRVDD
VINB1 GND +5VD R31 TP6
3 2 1 JP8
+5VD +5VA C25 22.1V
+DRVDD 74HC541N 21 J8
C10 0.1mF
C43 C11
0.1mF 0.1mF R32 TP7
0.1mF R6 TP25
820V 22.1V
19 J8
TPD R33 TP8
VCC C17 22.1V
U2 C16 10mF C18 17 J8
TP18 C14 0.1mF 16V 0.1mF
L1 REF43 EXTERNAL REFERENCE DRIVE 0.1mF R34 TP9
U3
+5A J2 +5VA VIN VOUT 22.1V
+ C28 VCC A 15 J8
C32 R7 Q1
22mF C12 3 7 A

–22–
0.1mF 0.1mF GND R3 1kV 2N2222
25V JP10 15kV R4
A AD817 6
50V
TP19 A A A
L2 2 4
A C13 C15 R8
+5D J3 +5VD R5 0.1mF
10kV 10mF 316V
+ C29
C33 16V
22mF A
0.1mF A A A
25V VEE
TP20 A A
L3
+VCC J4 VCC J1
T1 C38
+ C30 J10 R37
22mF C34 VIN
0.1mF 1 6 33V VCC
25V AIN VINA1 AC COUPLE OPTION

Figure 55. Evaluation Board Schematic

A R11
TP21 A A C36 JP24 500V C19
L4 PRI SEC 15pF 0.1mF +5VA
A R9 U4
–VEE J5 VEE 2 5 A 50V DIRECT COUPLE OPTION
+ C31 D1
C35 7 A R12 1N5711
22mF R35 R36 A 3 2
0.1mF 33V
25V 50V 200V R38 A R10 BUFFER AD845 6 VINA2
3 4 33V 2 500V
TP27 A A VINB1 JP23 3 D2
L5 4 C21
C37 B 0.1mF 1N5711
J11 +DRVDD 1 C20 R14 R39
A 15pF A
+5_OR _+3 + C39 0.1mF 10kV
C40 CW
22mF 0.1mF A AC COUPLE OPTION
JP21 R13 A
25V TPC 10kV A A VEE
JP14 +5VA
2 J8 26 J8 JP22 TPD
4 J8 NC 39 J8 TPD R15 D3
JP1 JP13 33V 1N5711
6 J8 28 J8 CML TPC VINB2
TP22
8 J8 29 J8 C42 U8 D4
DGND J6 0.1mF 11 10 1N5711
10 J8 30 J8
5 SETS OF A U5
12 J8 31 J8 U8 5 A
PADS TO U8 6 U5
TP26

SJ1
SJ3
SJ5

SJ2

JG1
SJ4
TP23 CONNECT 14 J8 32 J8 9 8 DECOUPLING DECOUPLING
GROUNDS U5
AGND J7 16 J8 34 J8 U8 +5VA +5VD 40 J8
1 2
JG1-WIRE A 18 J8 3 4
NC 35 J8
ETCH C26 C22 SJ6
20 J8 36 J8 U8 U5 0.1mF
CKT SIDE 2 0.1mF 3
1 4
22 J8 NC 37 J8
A
24 J8 38 J8 U8 74HC04
13 12
SPARE GATES
74HC14

REV. B
A
 AD9240

Figure 56. Evaluation Board Component Side Layout Figure 58. Evaluation Board Ground Plane Layout
(Not to Scale) (Not to Scale)

Figure 57. Evaluation Board Solder Side Layout Figure 59. Evaluation Board Power Plane Layout
(Not to Scale) (Not to Scale)

REV. B –23–
AD9240

OUTLINE DIMENSIONS
13.45
1.03 2.45 13.20 SQ
0.88 MAX 12.95
0.73
44 34

1.60 REF 1 33

PIN 1
SEATING
PLANE
TOP VIEW 10.20
(PINS DOWN) 10.00 SQ
9.80
2.20
2.00 0.23
1.80 0.11
11 23
0.25 7° 12 22
0.10 0°
0.10
COPLANARITY 0.45
VIEW A 0.29
0.80 BSC LEAD WIDTH
VIEW A LEAD PITCH
ROTATED 90° CCW

041807-A
COMPLIANT TO JEDEC STANDARDS MS-022-AB-1

Figure 1. 44-Lead Metric Quad Flat Package [MQFP]

(S-44-1)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9240AS −55°C to +85°C 44-Lead MQFP S-44-1
AD9240ASRL −55°C to +85°C 44-Lead MQFP S-44-1
AD9240ASZ −55°C to +85°C 44-Lead MQFP S-44-1
AD9240ASZRL −55°C to +85°C 44-Lead MQFP S-44-1
1
Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
D08985-0-3/10(B)

Rev. B | Page 24 of 24