a 8-Bit, 40/80/100 MSPS

Dual A/D Converter

AD9288
FEATURES FUNCTIONAL BLOCK DIAGRAM
Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS per Channel
VDD
On-Chip Reference and Track/Holds
475 MHz Analog Bandwidth Each Channel
AD9288

OUTPUT REGISTER
ENCA TIMING
SNR = 47 dB @ 41 MHz
1 V p-p Analog Input Range Each Channel AINA 8 8
Single 3.0 V Supply Operation (2.7 V to 3.6 V) T/H ADC D7A–D0A
AINA
Standby Mode for Single Channel Operation
SELECT #1
Two’s Complement or Offset Binary Output Mode REFINA
Output Data Alignment Mode REFOUT REF SELECT #2
Pin-Compatible 10-Bit Upgrade Available

OUTPUT REGISTER
REFINB DATA FORMAT
SELECT
APPLICATIONS AINB 8 8
T/H ADC D7B–D0B
Battery-Powered Instruments AINB
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes ENCB TIMING

I and Q Communications
VD GND VDD

GENERAL DESCRIPTION The encode input is TTL/CMOS-compatible and the 8-bit

The AD9288 is a dual 8-bit monolithic sampling analog-to- digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
digital converter with on-chip track-and-hold circuits and is supplies. User-selectable options are available to offer a combi-
optimized for low cost, low power, small size, and ease of use. nation of standby modes, digital data formats and digital data
The product operates at a 100 MSPS conversion rate with out- timing schemes. In standby mode, the digital outputs are driven
standing dynamic performance over its full operating range. to a high impedance state.
Each channel can be operated independently. Fabricated on an advanced CMOS process, the AD9288 is avail-
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power able in a 48-lead surface mount plastic package (7 × 7 mm,
supply and an encode clock for full-performance operation. No 1.4 mm LQFP) specified over the industrial temperature range
external reference or driver components are required for many (–40°C to +85°C). The AD9288 is pin-compatible with the
applications. The digital outputs are TTL/CMOS-compatible 10-bit AD9218, facilitating future system migrations.
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD9288–SPECIFICATIONS (V DD = 3.0 V; VD = 3.0 V, Differential Input; External reference unless otherwise noted.)
Test AD9288BST-100 AD9288BST-80 AD9288BST-40
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 8 Bits

DC ACCURACY
Differential Nonlinearity 25°C I ± 0.5 +1.25 ±0.5 +1.25 ±0.5 +1.25 LSB
Full VI 1.50 1.50 1.50 LSB
Integral Nonlinearity 25°C I ± 0.50 +1.25 ±0.50 +1.25 ±0.50 +1.25 LSB
Full VI 1.50 1.50 1.50 LSB
No Missing Codes Full VI Guaranteed Guaranteed Guaranteed
Gain Error1 25°C I –6 ± 2.5 +6 –6 ±2.5 +6 –6 ±2.5 +6 % FS
Full VI –8 +8 –8 +8 –8 +8 % FS
Gain Tempco1 Full VI 80 80 80 ppm/°C
Gain Matching 25°C V ± 1.5 ±1.5 ±1.5 % FS
Voltage Matching 25°C V ± 15 ±15 ±15 mV

ANALOG INPUT
Input Voltage Range
(With Respect to AIN) Full V ± 512 ±512 ±512 mV p-p
Common-Mode Voltage Full V 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD V
–0.2 +0.2 –0.2 +0.2 –0.2 +0.2
Input Offset Voltage 25°C I –35 ± 10 +35 –35 ±10 +35 –35 ±10 +35 mV
Full VI –40 +40 –40 +40 –40 +40 mV
Reference Voltage Full VI 1.2 1.25 1.3 1.2 1.25 1.3 1.2 1.25 1.3 V
Reference Tempco Full VI ± 130 ±130 ±130 ppm/°C
Input Resistance 25°C I 7 10 13 7 10 13 7 10 13 kΩ
Full VI 5 16 5 16 5 16 kΩ
Input Capacitance 25°C V 2 2 2 pF
Analog Bandwidth, Full Power 25°C V 475 475 475 MHz

SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 100 80 40 MSPS
Minimum Conversion Rate 25°C IV 1 1 1 MSPS
Encode Pulsewidth High (tEH) 25°C IV 4.3 1000 5.0 1000 8.0 1000 ns
Encode Pulsewidth Low (tEL) 25°C IV 4.3 1000 5.0 1000 8.0 1000 ns
Aperture Delay (tA) 25°C V 300 300 300 ps
Aperture Uncertainty (Jitter) 25°C V 5 5 5 ps rms
Output Valid Time (tV)2 Full VI 2 3.0 2 3.0 2 3.0 ns
Output Propagation Delay (tPD)2 Full VI 4.5 6.0 4.5 6.0 4.5 6.0 ns

DIGITAL INPUTS
Logic “1” Voltage Full VI 2.0 2.0 2.0 V
Logic “0” Voltage Full VI 0.8 0.8 0.8 V
Logic “1” Current Full VI ±1 ±1 ±1 µA
Logic “0” Current Full VI ±1 ±1 ±1 µA
Input Capacitance 25°C V 2.0 2.0 2.0 pF
3
DIGITAL OUTPUTS
Logic “1” Voltage Full VI 2.45 2.45 2.45 V
Logic “0” Voltage Full VI 0.05 0.05 0.05 V

POWER SUPPLY
Power Dissipation4 Full VI 180 218 171 207 156 189 mW
Standby Dissipation4, 5 Full VI 6 11 6 11 6 11 mW
Power Supply Rejection Ratio
(PSRR) 25°C I 8 20 8 20 8 20 mV/V
6
DYNAMIC PERFORMANCE
Transient Response 25°C V 2 2 2 ns
Overvoltage Recovery Time 25°C V 2 2 2 ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10.3 MHz 25°C I 47.5 47.5 44 47.5 dB
fIN = 26 MHz 25°C I 47.5 44 47 dB
fIN = 41 MHz 25°C I 44 47.0 dB

–2– REV. B
 AD9288
Test AD9288BST-100 AD9288BST-80 AD9288BST-40
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
6
DYNAMIC PERFORMANCE (Continued)
Signal-to-Noise Ratio (SINAD) (With Harmonics)
fIN = 10.3 MHz 25°C I 47 47 44 47 dB
fIN = 26 MHz 25°C I 47 44 47 dB
fIN = 41 MHz 25°C I 44 47 47 dB
Effective Number of Bits
fIN = 10.3 MHz 25°C I 7.5 7.5 7.0 7.5 Bits
fIN = 26 MHz 25°C I 7.5 7.0 7.5 Bits
fIN = 41 MHz 25°C I 7.0 7.5 7.5 Bits
2nd Harmonic Distortion
fIN = 10.3 MHz 25°C I 70 70 55 70 dBc
fIN = 26 MHz 25°C I 70 55 70 dBc
fIN = 41 MHz 25°C I 55 70 70 dBc
3rd Harmonic Distortion
fIN = 10.3 MHz 25°C I 60 60 55 60 dBc
fIN = 26 MHz 25°C I 60 55 60 dBc
fIN = 41 MHz 25°C I 52 60 60 dBc
Two-Tone Intermod Distortion (IMD)
fIN = 10.3 MHz 25°C V 60 60 60 dBc
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2
tV and tPD are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 10 pF or a dc current of ± 40 µA.
3
Digital supply current based on V DD = 3.0 V output drive with <10 pF loading under dynamic test conditions.
4
Power dissipation measured under the following conditions: f S = 100 MSPS, analog input is –0.7 dBFS, both channels in operation.
5
Standby dissipation calculated with encode clock in operation.
6
SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS

VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Test Level
Analog Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V I 100% production tested.
Digital Inputs . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V II 100% production tested at 25°C and sample tested at
VREF IN . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V specified temperatures.
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA III Sample tested only.
Operating Temperature . . . . . . . . . . . . . . . –55°C to +125°C
IV Parameter is guaranteed by design and characterization
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
testing.
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C V Parameter is a typical value only.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
VI 100% production tested at 25°C; guaranteed by design and
nent damage to the device. This is a stress rating only; functional operation of the characterization testing for industrial temperature range;
device at these or any other conditions outside of those indicated in the operation 100% production tested at temperature extremes for mili-
sections of this specification is not implied. Exposure to absolute maximum tary devices.
ratings for extended periods may affect device reliability.
Table I. User Select Options
ORDERING GUIDE
S1 S2 User Select Options
Temperature Package
0 0 Standby Both Channels A and B.
Model Ranges Options
0 1 Standby Channel B Only.
AD9288BST 1 0 Normal Operation (Data Align Disabled).
-40, -80, -100 –40°C to +85°C ST-48* 1 1 Data align enabled (data from both channels avail-
AD9288/PCB 25°C Evaluation Board able on rising edge of Clock A. Channel B data is
*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7 × 7 mm: LQFP).
delayed a 1/2 clock cycle).

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD9288 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B –3–
AD9288
PIN CONFIGURATION Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.

D7A (MSB)
ENCA
Aperture Uncertainty (Jitter)

GND

D2A
D4A
D6A

D1A
D3A

D0A
VDD

D5A
VD

48 47 46 45 44 43 42 41 40 39 38 37
The sample-to-sample variation in aperture delay.
GND 1 36
Differential Nonlinearity
NC
PIN 1
AINA 2 IDENTIFIER 35 NC The deviation of any code from an ideal 1 LSB step.
AINA 3 34 GND
DFS 4
Encode Pulsewidth/Duty Cycle
33 VDD
REFINA 5 32 GND
Pulsewidth high is the minimum amount of time that the
REFOUT 6 AD9288 31 VD ENCODE pulse should be left in Logic “1” state to achieve
TOP VIEW
REFINB 7
(Not to Scale)
30 VD rated performance; pulsewidth low is the minimum time
S1 8 29 GND
ENCODE pulse should be left in low state. At a given clock
S2 9 28 VDD
AINB 10
rate, these specs define an acceptable Encode duty cycle.
27 GND
AINB 11 26 NC Integral Nonlinearity
GND 12 25 NC The deviation of the transfer function from a reference line
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24 measured in fractions of 1 LSB using a “best straight line”
GND
VD
ENCB

D1B
D2B

D0B
D3B
D4B
D5B
D6B
(MSB) D7B
VDD

determined by a least square curve fit.

Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
PIN FUNCTION DESCRIPTIONS
Maximum Conversion Rate
Pin No. Name Description The encode rate at which parametric testing is performed.
1, 12, 16, 27, 29, Output Propagation Delay
32, 34, 45 GND Ground The delay between a differential crossing of ENCODE and
2 AINA Analog Input for Channel A ENCODE and the time when all output data bits are within
valid logic levels.
3 AINA Analog Input for Channel A
(Complementary) Power Supply Rejection Ratio
4 DFS Data Format Select: (Offset The ratio of a change in input offset voltage to a change in
binary output available if set power supply voltage.
low. Twos complement output Signal-to-Noise-and-Distortion (SINAD)
available if set high). The ratio of the rms signal amplitude (set at 1 dB below full
5 REFINA Reference Voltage Input for scale) to the rms value of the sum of all other spectral compo-
Channel A. nents, including harmonics but excluding dc.
6 REFOUT Internal Reference Voltage Signal-to-Noise Ratio (SNR)
7 REFINB Reference Voltage Input for The ratio of the rms signal amplitude (set at 1 dB below full
Channel B scale) to the rms value of the sum of all other spectral compo-
8 S1 User Select #1 (Refer to Table nents, excluding the first five harmonics and dc.
I), Tied with Respect to VD Spurious-Free Dynamic Range (SFDR)
9 S2 User Select #2 (Refer to Table The ratio of the rms signal amplitude to the rms value of the
I), Tied with Respect to VD peak spurious spectral component. The peak spurious compo-
10 AINB Analog Input for Channel B nent may or may not be a harmonic. May be reported in dBc
(Complementary) (i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
11 AINB Analog Input for Channel B
Two-Tone Intermodulation Distortion Rejection
13, 30, 31, 48 VD Analog Supply (3 V)
The ratio of the rms value of either input tone to the rms value of
14 ENCB Clock Input for Channel B the worst third order intermodulation product; reported in dBc.
15, 28, 33, 46 VDD Digital Supply (3 V)
Two-Tone SFDR
17–24 D7B–D0B Digital Output for Channel B The ratio of the rms value of either input tone to the rms value
25, 26, 35, 36 NC Do Not Connect of the peak spurious component. The peak spurious component
37–44 D0A–D7A Digital Output for Channel A may or may not be an IMD product. May be reported in dBc
47 ENCA Clock Input for Channel A (i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
DEFINITION OF SPECIFICATIONS Worst Harmonic
Analog Bandwidth (Small Signal) The ratio of the rms signal amplitude to the rms value of the
The analog input frequency at which the spectral power of the worst harmonic component, reported in dBc.
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
–4– REV. B
 AD9288

SAMPLE N SAMPLE N+1 SAMPLE N+5

A IN A, A IN B

tA SAMPLE N+2 SAMPLE N+3 SAMPLE N+4

tEH tEL
1/ f
S

ENCODE A, B
tPD tV

D7A–D0A DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1

D7B–D0B DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N DATA N+1

Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing

SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE

N N+1 N+2 N+3 N+4

AINA, AINB

tA
tEH tEL
1/ f
S

ENCODE A
tPD
tV
ENCODE B

D7A–D0A DATA N–8 DATA N–6 DATA N–4 DATA N–2 DATA N DATA N+2

D7B–D0B DATA N–7 DATA N–5 DATA N–3 DATA N–1 DATA N+1 DATA N+3

Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing

REV. B –5–
AD9288
SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
N N+1 N+2 N+3 N+4

AINA, AINB

tA
tEH tEL
1/ fS

ENCODE A
tPD
tV
ENCODE B

D7A–D0A DATA N–8 DATA N–6 DATA N–4 DATA N–2 DATA N DATA N+2

D7B–D0B DATA N-9 DATA N–7 DATA N–5 DATA N–3 DATA N–1 DATA N+1

Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

–6– REV. B
 Typical Performance Characteristics–AD9288
0 72.00
ENCODE = 100MSPS
ENCODE RATE = 100MSPS
–10 AIN = 10.3MHz
SNR = 48.52dB 68.00
SINAD = 48.08dB
–20 2ND HARMONIC = –62.54dBc 64.00
3RD HARMONIC = –63.56dBc
2ND
–30
60.00
–40
dB

dB
56.00
–50
3RD
52.00
–60

–70 48.00

–80 44.00

–90 40.00
SAMPLE 0 10 20 30 40 50 60 70 80 90
MHz

TPC 1. Spectrum: fS = 100 MSPS, fIN = 10 MHz, TPC 4. Harmonic Distortion vs. AIN Frequency
Single-Ended Input

0 0
ENCODE = 100MSPS ENCODE = 100MSPS
–10 AIN = 41MHz –10 AIN1 = 9.3MHz
SNR = 47.87dB AIN2 = 10.3MHz
SINAD = 46.27dB
–20 2ND HARMONIC = –54.10dBc –20 IMD = –60.0dBc
3RD HARMONIC = –55.46dBc
–30 –30

–40 –40
dB
dB

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90
SAMPLE SAMPLE

TPC 2. Spectrum: fS = 100 MSPS, fIN = 41 MHz, TPC 5. Two-Tone Intermodulation Distortion
Single-Ended Input

0 50.00
ENCODE = 100MSPS ENCODE RATE = 100MSPS
–10 AIN = 76MHz
SNR = 47.1dB 48.00
SINAD = 43.2dB SNR
–20 2ND HARMONIC = –52.2dBc
3RD HARMONIC = –51.5dBc 46.00
–30 SINAD

–40 44.00
dB
dB

–50 42.00

–60
40.00
–70
38.00
–80

–90 36.00
SAMPLE 0 10 20 30 40 50 60 70 80 90
MHz

TPC 3. Spectrum: fS = 100 MSPS, fIN = 76 MHz, TPC 6. SINAD/SNR vs. AIN Frequency
Single-Ended Input

REV. B –7–
AD9288
49.00 190
AIN = 10.3MHz SNR AIN = 10.3MHz
185

SINAD 180
48.00
175

POWER – mW
170
dB

47.00 165

160

155
46.00
150

145

45.00 140
30 40 50 60 70 80 90 100 110 0 10 20 30 40 50 60 70 80 90 100
MSPS MSPS

TPC 7. SINAD/SNR vs. Encode Rate TPC 10. Analog Power Dissipation vs. Encode Rate

50.00 48.0
SNR AIN = 10.3MHz ENCODE RATE = 100MSPS
47.5 AIN = 10.3MHz

46.00 SINAD
47.0
SNR
46.5
42.00 SINAD
46.0
dB

dB

45.5
38.00
45.0

44.5
34.00

44.0

30.00 43.5
7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 –40 25 85
ENCODE HIGH PULSEWIDTH – ns TEMPERATURE – ⴗC

TPC 8. SINAD/SNR vs. Encode Pulsewidth High TPC 11. SINAD/SNR vs. Temperature

0.5 0.6
ENCODE RATE = 100MSPS ENCODE RATE = 100MSPS
0.0 AIN = 10.3MHz
0.4
–0.5

–1.0 0.2

–1.5
0
–2.0 –3dB
% GAIN
dB

–2.5 –0.2
–3.0
–0.4
–3.5
–4.0 –0.6
–4.5
–0.8
–5.0

–5.5 –1.0
0 100 200 300 400 500 600 –40 25 85
BANDWIDTH – MHz TEMPERATURE – ⴗC

TPC 9. ADC Frequency Response: fS = 100 MSPS TPC 12. ADC Gain vs. Temperature (with External
1.25 V Reference)

–8– REV. B
 AD9288
2.0 VD

28k⍀ 28k⍀
1.5

AIN AIN
1.0
12k⍀ 12k⍀

0.5
LSB

0.0 TPC 16. Equivalent Analog Input Circuit

–0.5

–1.0 VD

–1.5
VBIAS

–2.0
CODE REFIN

TPC 13. Integral Nonlinearity

TPC 17. Equivalent Reference Input Circuit

1.00

0.75 VD

0.50
ENCODE

0.25
LSB

0.00
TPC 18. Equivalent Encode Input Circuit
–0.25

–0.50
VDD
–0.75

OUT
–1.00
CODE

TPC 14. Differential Nonlinearity

TPC 19. Equivalent Digital Output Circuit

1.3
ENCODE = 100MSPS
VD = 3.0V
VD
1.2 TA = +25ⴗC

1.1
VREFOUT – V

OUT
1.0

0.9

0.8 TPC 20. Equivalent Reference Output Circuit

0.7
0 0.25 0.5 0.75 1 1.25 1.5 1.75
LOAD – mA

TPC 15. Voltage Reference Out vs. Current Load

REV. B –9–
AD9288
APPLICATION NOTES Timing
THEORY OF OPERATION The AD9288 provides latched data outputs, with four pipeline
The AD9288 ADC architecture is a bit-per-stage pipeline-type delays. Data outputs are available one propagation delay (tPD)
converter utilizing switch capacitor techniques. These stages after the rising edge of the encode command (see Figures 1, 2
determine the 5 MSBs and drive a 3-bit flash. Each stage pro- and 3). The length of the output data lines and loads placed on
vides sufficient overlap and error correction allowing optimiza- them should be minimized to reduce transients within the
tion of comparator accuracy. The input buffers are differential AD9288. These transients can detract from the converter’s
and both sets of inputs are internally biased. This allows the dynamic performance.
most flexible use of ac or dc and differential or single-ended The minimum guaranteed conversion rate of the AD9288 is
input modes. The output staging block aligns the data, carries 1 MSPS. At clock rates below 1 MSPS, dynamic performance
out the error correction and feeds the data to output buffers. will degrade. Typical power-up recovery time after standby
The set of output buffers are powered from a separate supply, mode is 15 clock cycles.
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels. User Select Options
Two pins are available for a combination of operational modes.
USING THE AD9288 These options allow the user to place both channels in standby,
Good high speed design practices must be followed when using excluding the reference, or just the B channel. Both modes place
the AD9288. To obtain maximum benefit, decoupling capacitors the output buffers and clock inputs in high impedance states.
should be physically as close to the chip as possible, minimizing The other option allows the user to skew the B channel output
trace and via inductance between chip pins and capacitor (0603 data by 1/2 a clock cycle. In other words, if two clocks are fed to
surface mount caps are used on the AD9288/PCB evaluation the AD9288 and are 180° out of phase, enabling the data align
board). It is recommended to place a 0.1 µF capacitor at each will allow Channel B output data to be available at the rising
power-ground pin pair for high frequency decoupling, and edge of Clock A. If the same encode clock is provided to both
include one 10 µF capacitor for local low frequency decoupling. channels and the data align pin is enabled, then output data
The VREF IN pin should also be decoupled by a 0.1 µF capaci- from Channel B will be 180° out of phase with respect to Chan-
tor. It is also recommended to use a split power plane and nel A. If the same encode clock is provided to both channels
contiguous ground plane (see evaluation board section). Data and the data align pin is disabled, then both outputs are deliv-
output traces should be short (<1 inch), minimizing on-chip ered on the same rising edge of the clock.
noise at switching.
ENCODE Input EVALUATION BOARD
Any high speed A/D converter is extremely sensitive to the qual- The AD9288 evaluation board offers an easy way to test the
ity of the sampling clock provided by the user. A track/hold AD9288. It provides a means to drive the analog inputs single-
circuit is essentially a mixer. Any noise, distortion or timing endedly or differentially. The two encode clocks are easily
jitter on the clock will be combined with the desired signal at accessible at on-board SMB connectors J2, J7. These clocks are
the A/D output. For that reason, considerable care has been buffered on the board to provide the clocks for an on-board
taken in the design of the ENCODE input of the AD9288, and DAC and latches. The digital outputs and output clocks are
the user is advised to give commensurate thought to the clock available at a standard 37-pin connector, P2. The board has
source. The ENCODE input is fully TTL/CMOS compatible. several different modes of operation, and is shipped in the fol-
lowing configuration:
Digital Outputs
The digital outputs are TTL/CMOS compatible for lower • Single-Ended Analog Input
power consumption. During standby, the output buffers transi- • Normal Operation Timing Mode
tion to a high impedance state. A data format selection option • Internal Voltage Reference
supports either twos complement (set high) or offset binary Power Connector
output (set low) formats. Power is supplied to the board via a detachable 6-pin power
Analog Input strip, P1.
The analog input to the AD9288 is a differential buffer. For VREFA – Optional External Reference Input (1.25 V/1 µA)
best dynamic performance, impedance at AIN and AIN should VREFB – Optional External Reference Input (1.25 V/1 µA)
match. Special care was taken in the design of the analog input VDL – Supply for Support Logic and DAC (3 V/215 mA)
stage of the AD9288 to prevent damage and corruption of VDD – Supply for ADC Outputs (3 V/15 mA)
data when the input is overdriven. The nominal input range is VD – Supply for ADC Analog (3 V/30 mA)
1.024 V p-p centered at VD × 0.3. Analog Inputs
Voltage Reference The evaluation board accepts a 1 V analog input signal centered
A stable and accurate 1.25 V voltage reference is built into the at ground at each analog input. These can be single-ended sig-
AD9288 (REFOUT). In normal operation, the internal reference nals using SMB connectors J5 (channel A) and J1 (Channel B).
is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6 In this mode use jumpers E4–E5 and E6–E7. (E1–E2 and E9–
(REFOUT). The input range can be adjusted by varying the E10 jumpers should be lifted.)
reference voltage applied to the AD9288. No appreciable degra- Differential analog inputs use SMB connectors J4 and J6. Input
dation in performance occurs when the reference is adjusted is 1 V centered at ground. The single-ended input is converted
± 5%. The full-scale range of the ADC tracks reference voltage,
which changes linearly.

–10– REV. B
 AD9288
to differential by transformers T1, T2—allowing the ADC perfor-
mance for differential inputs to be measured using a single-ended
source. In this mode use jumpers E1–E2, E3–E4, E7–E8 and PIN 22 (DATA)
E9–E10. (E4–E5 and E6–E7 jumpers should be lifted.)
Each analog input is terminated on the board with 50 Ω to
ground. Each input is ac-coupled on the board through a 0.1 µF 1
capacitor to an on-chip resistor divider that provides dc bias.
Note that the inverting analog inputs are terminated on the PIN 2 (CLOCK)

board with 25 Ω (optimized for single-ended operation). When

driving the board differentially these resistors can be changed to Ch1 2.00V CH2 2.00V M 10.0ns CH4 40mV
50 Ω to provide balanced inputs.
Figure 4. Data Output and Clock at 37-Pin Connector
Encode
The encode clock for channel A uses SMB connector J7. Channel DAC Outputs
B encode is at SMB connector J2. Each clock input is termi- Each channel is reconstructed by an on-board dual channel
nated on the board with 50 Ω to ground. The input clocks are DAC, an AD9763. This DAC is intended to assist in debug—it
fed directly to the ADC and to buffers U5, U6 which drive the should not be used to measure the performance of the ADC.
DAC and latches. The clock inputs are TTL compatible, but It is a current output DAC with on-board 50 Ω termination
should be limited to a maximum of VD. resistors. Figure 5 is representative of the DAC output with a
full-scale analog input. The scope setting was low bandwidth,
Voltage Reference 50 Ω termination. Note that both Encode A and Encode B need
The AD9288 has an internal 1.25 V voltage reference. An to be running to use the DAC.
external reference for each channel may be employed instead.
The evaluation board is configured for the internal reference
(use jumpers E18–E41 and E17–E19. To use external references,
connect to VREFA and VREFB pins on the power connector
P1 and use jumpers E20–E18 and E21–E19.
Normal Operation Mode 1
In this mode both converters are clocked by the same encode
clock; latency is four clock cycles (see timing diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set at jumpers E22–E29 and E26–E23.
Data Align Mode Ch1 500mV⍀BW M 50.0ns CH1 380mV
In this mode channel B output is delayed an additional 1/2 cycle.
Signal S1 (Pin 8) and signal S2 (Pin 9) are both held high. This Figure 5. AD9763 Reconstruction DAC Output
is set at jumpers E22–E29 and E26–E28. Troubleshooting
Data Format Select If the board does not seem to be working correctly, try the
Data Format Select sets the output data format that the ADC following:
outputs. Setting DFS (Pin 4) low at E30–E27 sets the output • Verify power at IC pins.
format to be offset binary; setting DFS high at E30–E25 sets • Check that all jumpers are in the correct position for the
the output to be twos complement. desired mode of operation.
• Verify VREF is at 1.25 V
Data Outputs • Try running encode clock and analog inputs at low speeds
The ADC digital outputs are latched on the board by two 574s, (10 MSPS/1 MHz) and monitor 574 outputs, DAC outputs,
the latch outputs are available at the 37-pin connector at Pins and ADC outputs for toggling.
22–29 (Channel A) and Pins 30–37 (Channel B). A latch out-
put clock (data ready) is available at Pin 2 or 21 on the output The AD9288 Evaluation Board is provided as a design example
connector. The data ready signal can be aligned with clock A for customers of Analog Devices, Inc. ADI makes no warranties,
input by connecting E31–E32 or aligned with clock B input by express, statutory, or implied, regarding merchantability or
connecting E31–E33. fitness for a particular purpose.

REV. B –11–
AD9288
BILL OF MATERIALS

# Qty REFDES Device Package Value

1 22 C1–C15, C20–C25, C27 Ceramic Cap 0603 0.1 µF
2 5 C16–C19, C26 Tantalum Cap TAJD 10 µF
3 43 E1–E43 W-HOLE W-HOLE
4 8 J1–J8 SMBPN SMBP
5 1 P1 TB6 TB6
6 1 P2 37DRFP C37DRFP
7 10 R1, R3, R5–R7, R10–R14 Resistor R1206 50 Ω
8 2 R2, R4 Resistor R1206 25 Ω
9 2 R8, R9 Resistor R1206 2 kΩ
10 2 R15, R16 Resistor R1206 0Ω
11 2 T1, T2 Transformer T1–1T
12 1 U1 AD9288BST-100 LQFP48
13 1 U2 AD9763 LQFP48
14 2 U3, U4 74ACQ574 DIP20\SOL
15 2 U5, U6 SN74LCX86 SO14

–12– REV. B
 DAC OUTPUT B DAC OUTPUT A
J8 J3

GND
GND GND

REV. B
R14

GND
GND

GND
GND
50⍀ R12
GND 50⍀

0.1␮F
C20 VDL GND

2k⍀
2k⍀
50⍀

50⍀
0.1␮F

C21
GND
GND
GND

R9
R8
R10

R13
VDL
48 47 46 45 44 43 42 41 40 39 38 37

A1
B1
B2
A2
D7B 1 DB9–P1 NC7 36 P1

AVDD
D6B 2 NC6 35

MODE
DB8–P1

REFIO
REFIO
ACOM
SLEEP

FSADJ1
FSADJ0
34
1 2 3 4 5 6
D5B 3 DB7–P1 NC5
D4B 4 DB6–P1 NC4 33
D3B 5 DB5–P1 DB0–P2 32 GND GND VD VDD VDL VREFA VREFB
AD9763 31
D2B 6 DB4–P1 DB1–P2 GND
U2
D1B 7 DB3–P1 DB2–P2 30 D0A
D0B 8 DB2–P1 DB3–P2 29 D1A VD VDD VDL VREFA VREFB
GND 9 DB1–P1 DB4–P2 28 D2A
ENCA 10 27
GND GND DB0–P1 DB5–P2 D3A C16 C17 C18 C19 C26
R16 11 NC DB6–P2 26 D4A 10␮F 10␮F 10␮F 10␮F 10␮F
00 74LCX86 C25 12 25
ENCODE A 0.1␮F NC1 DB7–P2 D5A GND

NC2
NC3
DCOM1
DVDD1
WRT1/IQWRT
CLK1/1QCLK
CLK2/IQRESET
WRT2/IQSEL
DCOM2
DVDD2
DB9–P2
DB8–P2
1 14
J7 1A VCC VDL 13 14 15 16 17 18 19 20 21 22 23 24
R11 2 13
GND 1B 4B GND GND
50⍀ 3 12 D6A
1Y 4A
4 11 D7A C14
GND GND

GND
GND
GND
GND
2A
U6 4Y CLKLATA 74ACQ574 0.1␮F
E35 E36 5 10 E39 E38
VDL 2B 3B VDL GND GND 1 20
6 9 GND OUT_EN VCC VDL

CLKDACA
CLKDACA
CLKDACB
CLKDACB
E34 CLKCONA 2Y 3A C23 C22 2 19 D7A 1
7 8 E37 0.1␮F VDL VDL 0.1␮F D7 D0 Q0 GND
GND GND 3Y CLKDACA 3 18 D6A 2
D6 D1 Q1
GND GND 4 17 D5A 3
VD VDD D5 D2 Q2
5 16 D4A 4
D4 D3 U3 Q3
C7 C8 6 15 D3A
0.1␮F 0.1␮F D3 D4 Q4 5
GND 7 14 D2A 6
GND GND D2 D5 Q5
8 13 D1A
GND D1 D6 Q6 7
R1 C10 D0A LSB
50⍀ 0.1␮F 9 12 8
D0 D7 Q7

GND
D7
D6
D5
D4
D3
D2
D1
D0

ENCA
E5 E4 10 11
J5 GND GND GND GND CLOCK CLKLATA CLKCONA 9

–13–
AINA E3 48 47 46 45 44 43 42 41 40 39 38 37 10
SINGLE-ENDED C27 C24 E32 11
GND

VD
0.1␮F 0.1␮F

VDD
D6A
D5A
D4A
D3A
D2A
D1A
D0A

GND E31 12

GND
GND

ENCA
T1–1T
GND 1 GND NC 36 GND E33 13
GND 6 1 R2
R5 C9

(MSB) D7A
50⍀ 2 25⍀ 0.1␮F 2 AINA NC 35 14
4 3 CLKCONB 15
J4 3 AINA GND 34 GND
E1 E2 T2 E25 E30 16
AINA VD 4 DFS VDD 33 VDD
DIFFERENTIAL E41 C4 GND 17
E27 E20 E18 5 REFINA GND 32 GND 0.1␮F C3
VREFA GND 0.1␮F 18
GND 6 AD9288 31 VD
GND E17
REFOUT VD 19
U1
GND E24 VREFB 7 REFINB VD 30 VD 20
GND E21 E19 C2 GND GND

Figure 6. Dual Evaluation Board Schematic

E23 VD 8 S1 GND 29 GND 0.1␮F C1 21
GND R6 E29 E22 GND 0.1␮F
9 S2 28 22
50⍀ T1 VD
E28 E26
VDD VDD
4 3 23
J6 10 AINB GND 27 GND
E9 2 24
E10 R4 C12
AINB 6 1 11 AINB NC 26
25⍀ 0.1␮F 25
DIFFERENTIAL
T1–1T GND 12 GND NC 25 GND
GND 26
GND GND GND
27
VD
ENCB
VDD
GND
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B

C15
E8 13 14 15 16 17 18 19 20 21 22 23 24 74ACQ574 0.1␮F 28
J1 1 20 29
E6 E7 C5 GND OUT EN
AINB R3 C11 0.1␮F
VCC VDL
0.1␮F ENCB GND 2 19 D0B 30
SINGLE-ENDED 50⍀ D0 Q0
GND 3 18 D1B 31
ENCB D1 Q1
GND GND VD 4 17 D2B 32
D2 Q2
R15 5 16 D3B 33
00 74LCX86 C13 D3 U4 Q3
ENCODE B 0.1␮F C6 6 15 D4B 34
1 14 0.1␮F D4 Q4
J2 1A VCC VDL 7 14 D5B 35
2 13 GND D5 Q5
R7 GND 8 13 D6B 36
50⍀ GND 1B 4B D6 Q6
3 12 VDD 9 12 D7B MSB 37
1Y 4A D7 Q7
GND GND 4 U5 11 10 11 E43
2A 4Y CLKLATB E42
E13 E16 5 10 E15 E11 GND GND CLOCK CLKLATB
VDL 2B 3B VDL
NC = NO CONNECT E40 C37DRPF
6 9 P2
E14 CLKCONB 2Y 3A E12
7 8
AD9288

GND GND 3Y CLKDACB CLKLATA

GND GND
AD9288

Figure 7. Printed Circuit Board Top Side Copper Figure 9. Printed Circuit Board Ground Layer

Figure 8. Printed Circuit Board Bottom Side Silkscreen Figure 10. Printed Circuit Board “Split” Power Layer

–14– REV. B
 AD9288

Figure 11. Printed Circuit Board Bottom Side Copper Figure 12. Printed Circuit Board Top Side Silkscreen

REV. B –15–
AD9288
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

48-Lead LQFP
(ST-48)

C00585–0–2/02(B)
0.063 (1.60) MAX 0.354 (9.00) BSC
0.030 (1.45)
0.057 (0.75) 0.276 (7.0) BSC
0.030 (0.75) 0.018 (1.35)
0.053 (0.45)
0.018 (0.45) 48 37
1 36

0.354 (9.00) BSC

0.276 (7.0) BSC
SEATING
PLANE
TOP VIEW
(PINS DOWN)

0.006 (0.15) 12 25
13 24
0.002 (0.05) 0 MIN
0 –7 0.007 (0.18) 0.019 (0.5) 0.011 (0.27)
0.004 (0.09) BSC 0.006 (0.17)

Revision History
Location Page
Data Sheet changed from REV. A to REV. B.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

PRINTED IN U.S.A.

–16– REV. B