Dual 12-/14-/16-Bit,

LVDS Interface, 500 MSPS DACs

Data Sheet AD9780/AD9781/AD9783
FEATURES GENERAL DESCRIPTION
High dynamic range, dual DAC parts The AD9780/AD9781/AD9783 include pin-compatible, high
Low noise and intermodulation distortion dynamic range, dual digital-to-analog converters (DACs) with
Single carrier W-CDMA ACLR = 80 dBc at 61.44 MHz IF 12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.
Innovative switching output stage permits usable outputs The devices include specific features for direct conversion transmit
beyond Nyquist frequency applications, including gain and offset compensation, and they
LVDS inputs with dual-port or optional interleaved single- interface seamlessly with analog quadrature modulators such as
port operation the ADL5370.
Differential analog current outputs are programmable from
A proprietary, dynamic output architecture permits synthesis
8.6 mA to 31.7 mA full scale
of analog outputs even above Nyquist by shifting energy away
Auxiliary 10-bit current DACs with source/sink capability for
from the fundamental and into the image frequency.
external offset nulling
Internal 1.2 V precision reference voltage source Full programmability is provided through a serial peripheral
Operates from 1.8 V and 3.3 V supplies interface (SPI) port. Some pin-programmable features are also
315 mW power dissipation offered for those applications without a controller.
Small footprint, RoHS compliant, 72-lead LFCSP PRODUCT HIGHLIGHTS
APPLICATIONS 1. Low noise and intermodulation distortion (IMD) enable
Wireless infrastructure high quality synthesis of wideband signals.
W-CDMA, CDMA2000, TD-SCDMA, WiMAX 2. Proprietary switching output for enhanced dynamic
Wideband communications performance.
LMDS/MMDS, point-to-point 3. Programmable current outputs and dual auxiliary DACs
RF signal generators, arbitrary waveform generators provide flexibility and system enhancements.

FUNCTIONAL BLOCK DIAGRAM

CLKP AD9783 DUAL LVDS DAC

CLKN
16-BIT IOUT1P
I DAC IOUT1N
DEINTERLEAVING

INTERFACE LOGIC
16-BIT IOUT2P
LOGIC

LVDS Q DAC
INTERFACE IOUT2N
GAIN
D[15:0]
DAC
VIA, VIB
GAIN
DAC

OFFSET AUX1P
INTERNAL DAC AUX1N
SERIAL REFERENCE
PERIPHERAL AND AUX2P
OFFSET
INTERFACE BIAS
DAC AUX2N
06936-001
REFIO
SDIO
SCLK
SDO

CSB

RESET

Figure 1.

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD9780/AD9781/AD9783 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 General Operation of the Serial Interface ............................... 19
Applications ....................................................................................... 1 Instruction Byte .......................................................................... 19
General Description ......................................................................... 1 MSB/LSB Transfers .................................................................... 20
Product Highlights ........................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 20
Functional Block Diagram .............................................................. 1 SPI Register Map ............................................................................ 21
Table of Contents .............................................................................. 2 SPI Register Descriptions .............................................................. 22
Revision History ............................................................................... 2 SPI Port, RESET, and Pin Mode ............................................... 24
Specifications..................................................................................... 3 Parallel Data Port Interface ........................................................... 25
DC Specifications ......................................................................... 3 Optimizing the Parallel Port Timing ....................................... 25
Digital Specifications ................................................................... 4 BIST Operation........................................................................... 27
AC Specifications.......................................................................... 5 Driving the CLK Input .............................................................. 27
Absolute Maximum Ratings............................................................ 6 Full-Scale Current Generation ................................................. 28
Thermal Resistance ...................................................................... 6 DAC Transfer Function ............................................................. 28
ESD Caution .................................................................................. 6 Analog Modes of Operation ..................................................... 28
Pin Configurations and Function Descriptions ........................... 7 Power Dissipation....................................................................... 30
Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 31
Terminology .................................................................................... 18 Ordering Guide .......................................................................... 31
Theory of Operation ...................................................................... 19
Serial Peripheral Interface ......................................................... 19

REVISION HISTORY
8/2017—Rev. B to Rev. C 6/2008—Rev. 0 to Rev. A
Changes to Table 12 ........................................................................ 22 Changed Maximum Sample Rate to 500 MHz Throughout .......1
Changes to Table 3.............................................................................4
6/2012—Rev. A to Rev. B Changes to Building the Array Section ....................................... 25
Changes to Table 2 ............................................................................ 4 Changes to Determining the SMP Value Section ...................... 25
Changes to Pins 25, 26, 29, and 30 Description, Table 6 ............. 7 Added Evaluation Board Schematics Section ............................. 30
Changes to Pins 9 to 24, 31 to 42, 25, 26, 29, and 30 Description, Updated Outline Dimensions ....................................................... 35
Table 7 ................................................................................................ 8
Changes to Pins 25, 26, 29, and 30 Description, Table 7 ............. 9 11/2007—Revision 0: Initial Version
Changes to SEEK Bit Function Description, Table 12 ............... 22
Changes to Parallel Data Port Interface Section......................... 25
Changed fDACCLK from 600 MHz to 500 MHz .............................. 26
Added BIST Operation Section .................................................... 27
Changes to Driving the CLK Input Section and Figure 59 ....... 27
Removed Evaluation Board Schematics Section ........................ 31
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31

Rev. C | Page 2 of 32
AD9780/AD9781/AD9783 Data Sheet

SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.

Table 1.
AD9780 AD9781 AD9783
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 14 16 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.13 ±0.5 ±2 LSB
Integral Nonlinearity (INL) ±0.25 ±1 ±4 LSB
MAIN DAC OUTPUTS
Offset Error –0.001 0 +0.001 –0.001 0 +0.001 –0.001 0 +0.001 % FSR
Gain Error (with Internal Reference) ±2 ±2 ±2 % FSR
Full-Scale Output Current 1 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA
Output Compliance Range –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 V
Output Resistance 10 10 10 MΩ
Main DAC Monotonicity Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset 0.04 0.04 0.04 ppm/°C
Gain 100 100 100 ppm/°C
Reference Voltage 30 30 30 ppm/°C
AUX DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current –2 +2 –2 +2 –2 +2 mA
Output Compliance Range (Source) 0 1.6 0 1.6 0 1.6 V
Output Compliance Range (Sink) 0.8 1.6 0.8 1.6 0.8 1.6 V
Output Resistance 1 1 1 MΩ
AUX DAC Monotonicity Guaranteed
REFERENCE
Internal Reference Voltage 1.2 1.2 1.2 V
Output Resistance 5 5 5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
POWER CONSUMPTION
fDAC = 500 MSPS, IF = 20 MHz V×I V×I V×I V×I V×I V×I mW
fDAC = 500 MSPS, IF = 10 MHz 440 440 440 mW
Power-Down Mode 3 5 3 5 3 35 mW
SUPPLY CURRENTS 2
AVDD33 55 58 55 58 55 58 mA
CVDD18 34 38 34 38 34 38 mA
DVDD33 13 15 13 15 13 15 mA
DVDD18 68 85 68 85 68 85 mA
1
Based on a 10 kΩ external resistor.
2
fDAC = 500 MSPS, fOUT = 20 MHz.

Rev. C | Page 3 of 32
AD9780/AD9781/AD9783 Data Sheet
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.

Table 2.
Parameter Min Typ Max Unit
DAC CLOCK INPUT (CLKP, CLKN)
Differential Peak-to-Peak Voltage (CLKP − CLKN) 400 800 1600 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate 500 MSPS
DAC CLOCK TO ANALOG OUTPUT DATA LATENCY 7 Cycles
SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
Setup Time, SDI to SCLK (tDS) 2.0 ns
Hold Time , SDI to to SCLK (tDH) 0.2 ns
Data Valid ,SDO to SCLK, (tDV) 2.3 ns
Setup time, CSB to SCLK (tDCSB) 1.4 ns
SERIAL PERIPHERAL INTERFACE LOGIC LEVELS
Input Logic High 2.0 V
Input Logic Low 0.8 V
DIGITAL INPUT DATA (LVDS INTERFACE)
Input Voltage Range, VIA or VIB 800 1600 mV
Input Differential Threshold, VIDTH −100 +100 mV
Input Differential Hysteresis, VIDTHH to VIDTHL 20 mV
Input Differential Input Impedance, RIN 80 120 Ω
Maximum LVDS Input Rate (per DAC) 500 MSPS

Rev. C | Page 4 of 32
Data Sheet AD9780/AD9781/AD9783
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.

Table 3.
AD9780 AD9781 AD9783
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 500 MSPS, fOUT = 20 MHz 79 78 80 dBc
fDAC = 500 MSPS, fOUT = 120 MHz 67 66 68 dBc
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode) 55 58 62 dBc
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode) 58 62 59 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 500 MSPS, fOUT = 20 MHz 91 93 86 dBc
fDAC = 500 MSPS, fOUT = 120 MHz 80 75 79 dBc
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode) 69 70 64 dBc
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode) 60.5 61.5 66 dBc
ONE-TONE NOISE SPECTRAL DENSITY (NSD)
fDAC = 500 MSPS, fOUT = 40 MHz −157 −162 −165 dBc
fDAC = 500 MSPS, fOUT = 120 MHz −154.5 −156.5 −157 dBc
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode) −153 −153 −154 dBc
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode) −152 −152 −153 dBc
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 20 MHz −81 −82.5 −82 dBc
fDAC = 491.52 MSPS, fOUT = 80 MHz −80 −82.5 −81 dBc
fDAC = 491.52 MSPS, fOUT = 411.52 MHz −71 −68 −69 dBc
fDAC = 491.52 MSPS, fOUT = 471.52 MHz −69 −69 −70 dBc

Rev. C | Page 5 of 32
AD9780/AD9781/AD9783 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4. THERMAL RESISTANCE
With Thermal resistance is tested using a JEDEC standard 4-layer
Parameter Respect to Rating thermal test board with no airflow.
AVDD33, DVDD33 AGND, DGND, CGND −0.3 V to +3.6 V
DVDD18, CVDD18 AGND, DGND, CGND −0.3 V to +1.98 V Table 5.
AGND DGND, CGND −0.3 V to +0.3 V Package Type θJA Unit
DGND AGND, CGND −0.3 V to +0.3 V CP-72-1 (Exposed Pad Soldered to PCB) 25 °C/W
CGND AGND, DGND −0.3 V to +0.3 V
Stresses at or above those listed under Absolute Maximum
REFIO AGND −0.3 V to
Ratings may cause permanent damage to the product. This is a
AVDD33 + 0.3 V
stress rating only; functional operation of the product at these
IOUT1P, IOUT1N, AGND −1.0 V to
IOUT2P, IOUT2N, AVDD33 + 0.3 V or any other conditions above those indicated in the operational
AUX1P, AUX1N, section of this specification is not implied. Operation beyond
AUX2P, AUX2N the maximum operating conditions for extended periods may
D15 to D0 DGND −0.3 V to affect product reliability.
DVDD33 + 0.3 V
CLKP, CLKN CGND −0.3 V to ESD CAUTION
CVDD18 + 0.3 V
CSB, SCLK, SDIO, SDO DGND –0.3 V to
DVDD33 + 0.3 V
Junction Temperature +125°C
Storage Temperature −65°C to +150°C

Rev. C | Page 6 of 32
Data Sheet AD9780/AD9781/AD9783

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AVDD33
AVDD33

AVDD33
AVDD33
IOUT1N

IOUT2N
IOUT1P

IOUT2P
AUX1N

AUX2N
AUX1P

AUX2P

REFIO
AVSS

AVSS

AVSS

AVSS

AVSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CVDD18 1 PIN 1 54 FS ADJ
CVSS 2 INDICATOR 53 RESET
CLKP 3 52 CSB
CLKN 4 51 SCLK
CVSS 5 50 SDIO
CVDD18 6 49 SDO
DVSS 7 48 DVSS
DVDD18 8 AD9780 47 DVDD18
D11P 9 (TOP VIEW) 46 NC
D11N 10 45 NC
D10P 11 44 NC
D10N 12 43 NC
D9P 13 42 NC
D9N 14 41 NC
D8P 15 40 NC
D8N 16 39 NC
D7P 17 38 D0N
D7N 18 37 D0P
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D6P

D5P

D4P

DCOP

DCIP

D3P

D2P

D1P
DCON

DVSS

DCIN
D6N

D5N

D4N

D3N

D2N

D1N
DVDD33
NOTES
1. NC = NO CONNECT

06936-002
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.

Figure 2. AD9780 Pin Configuration

Table 6. AD9780 Pin Function Descriptions

Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Return.
3, 4 CLKP, CLKN Differential DAC Sampling Clock Input.
7, 28, 48 DVSS Digital Common.
8, 47 DVDD18 Digital Supply Voltage (1.8 V).
9 to 24, 31 to 38 D11P, D11N to D0P, D0N LVDS Data Inputs. D11 is the MSB, D0 is the LSB.
25, 26 DCOP, DCON Differential Data Clock Output. Clock at the DAC sample rate.
27 DVDD33 Digital Input and Output Pad Ring Supply Voltage (3.3 V).
29, 30 DCIP, DCIN Differential Data Clock Input. Clock aligned with input data.
39 to 46 NC No Connection. Leave these pins floating.
49 SDO Serial Port Data Output.
50 SDIO Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
51 SCLK Serial Port Clock Input.
52 CSB Serial Port Chip Select (Active Low).
53 RESET Chip Reset (Active High).
54 FS ADJ Full-Scale Current Output Adjust.
55 REFIO Analog Reference Input/Output (1.2 V Nominal).
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Common.
59 IOUT2P DAC Current Output. Full-scale current is sourced when all data bits are 1s.
60 IOUT2N Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
62, 63 AUX2P, AUX2N Differential Auxiliary DAC Current Output (Channel 2).
65, 66 AUX1N, AUX1P Differential Auxiliary DAC Current Output (Channel 1).
68 IOUT1N Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
69 IOUT1P DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Heat Sink Pad N/A The heat sink pad on the bottom of the package must be soldered to the PCB plane that
carries AVSS.

Rev. C | Page 7 of 32
AD9780/AD9781/AD9783 Data Sheet

AVDD33
AVDD33

AVDD33
AVDD33
IOUT1N

IOUT2N
IOUT1P

IOUT2P
AUX1N

AUX2N
AUX1P

AUX2P

REFIO
AVSS

AVSS

AVSS

AVSS

AVSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CVDD18 1 PIN 1 54 FS ADJ
CVSS 2 INDICATOR 53 RESET
CLKP 3 52 CSB
CLKN 4 51 SCLK
CVSS 5 50 SDIO
CVDD18 6 49 SDO
DVSS 7 48 DVSS
DVDD18 8 AD9781 47 DVDD18
D13P 9 (TOP VIEW) 46 NC
D13N 10 45 NC
D12P 11 44 NC
D12N 12 43 NC
D11P 13 42 D0N
D11N 14 41 D0P
D10P 15 40 D1N
D10N 16 39 D1P
D9P 17 38 D2N
D9N 18 37 D2P
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D8P

D7P

D6P

DCOP

DCIP

D5P

D4P

D3P
DCON

DVSS

DCIN
D8N

D7N

D6N

D5N

D4N

D3N
DVDD33
NOTES
1. NC = NO CONNECT

06936-003
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.

Figure 3. AD9781 Pin Configuration

Table 7. AD9781 Pin Function Descriptions

Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Return.
3, 4 CLKP, CLKN Differential DAC Sampling Clock Input.
7, 28, 48 DVSS Digital Common.
8, 47 DVDD18 Digital Supply Voltage (1.8 V).
9 to 24, 31 to 42 D13P, D13N to D0P, D0N Data Inputs. D13 is the MSB, D0 is the LSB.
25, 26 DCOP, DCON Differential Data Clock Output. Clock at the DAC sample rate.
27 DVDD33 Digital Input and Output Pad Ring Supply Voltage (3.3 V).
29, 30 DCIP, DCIN Differential Data Clock Input. Clock aligned with input data.
43 to 46 NC No Connection. Leave these pins floating.
49 SDO Serial Port Data Output.
50 SDIO Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
51 SCLK Serial Port Clock Input.
52 CSB Serial Port Chip Select (Active Low).
53 RESET Chip Reset (Active High).
54 FS ADJ Full-Scale Current Output Adjust.
55 REFIO Analog Reference Input/Output (1.2 V Nominal).
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Common.
59 IOUT2P DAC Current Output. Full-scale current is sourced when all data bits are 1s.
60 IOUT2N Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
62, 63 AUX2P, AUX2N Differential Auxiliary DAC Current Output (Channel 2).
65, 66 AUX1N, AUX1P Differential Auxiliary DAC Current Output (Channel 1).
68 IOUT1N Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
69 IOUT1P DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Heat Sink Pad N/A The heat sink pad on the bottom of the package must be soldered to the PCB plane that
carries AVSS.

Rev. C | Page 8 of 32
Data Sheet AD9780/AD9781/AD9783

AVDD33
AVDD33

AVDD33
AVDD33
IOUT1N

IOUT2N
IOUT1P

IOUT2P
AUX1N

AUX2N
AUX1P

AUX2P

REFIO
AVSS

AVSS

AVSS

AVSS

AVSS
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CVDD18 1 PIN 1 54 FS ADJ
CVSS 2 INDICATOR 53 RESET
CLKP 3 52 CSB
CLKN 4 51 SCLK
CVSS 5 50 SDIO
CVDD18 6 49 SDO
DVSS 7 48 DVSS
DVDD18 8 AD9783 47 DVDD18
D15P 9 (TOP VIEW) 46 D0N
D15N 10 45 D0P
D14P 11 44 D1N
D14N 12 43 D1P
D13P 13 42 D2N
D13N 14 41 D2P
D12P 15 40 D3N
D12N 16 39 D3P
D11P 17 38 D4N
D11N 18 19 37 D4P
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D10P

D9P

D8P

DCOP

DCIP

D7P

D6P

D5P
DCON

DVSS

DCIN
D9N

D8N

D7N

D6N

D5N
D10N

DVDD33
NOTES

06936-004
1. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.

Figure 4. AD9783 Pin Configuration

Table 8. AD9783 Pin Function Descriptions

Pin No. Mnemonic Description
1, 6 CVDD18 Clock Supply Voltage (1.8 V).
2, 5 CVSS Clock Supply Return.
3, 4 CLKP, CLKN Differential DAC Sampling Clock Input.
7, 28, 48 DVSS Digital Common.
8, 47 DVDD18 Digital Supply Voltage (1.8 V).
9 to 24, 31 to 46 D15P, D15N to D0P, D0N LVDS Data Inputs. D15 is the MSB, D0 is the LSB.
25, 26 DCOP, DCON Differential Data Clock Output. Clock at the DAC sample rate.
27 DVDD33 Digital Input and Output Pad Ring Supply Voltage (3.3 V).
29, 30 DCIP, DCIN Differential Data Clock Input Clock aligned with input data.
49 SDO Serial Port Data Output.
50 SDIO Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
51 SCLK Serial Port Clock Input.
52 CSB Serial Port Chip Select (Active Low).
53 RESET Chip Reset (Active High).
54 FS ADJ Full-Scale Current Output Adjust.
55 REFIO Analog Reference Input/Output (1.2 V Nominal).
56, 57, 71, 72 AVDD33 Analog Supply Voltage (3.3 V).
58, 61, 64, 67, 70 AVSS Analog Common.
59 IOUT2P DAC Current Output. Full-scale current is sourced when all data bits are 1s.
60 IOUT2N Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
62, 63 AUX2P, AUX2N Differential Auxiliary DAC Current Output (Channel 2).
65, 66 AUX1N, AUX1P Differential Auxiliary DAC Current Output (Channel 1).
68 IOUT1N Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
69 IOUT1P DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Heat Sink Pad N/A The heat sink pad on the bottom of the package must be soldered to the PCB plane that
carries AVSS.

Rev. C | Page 9 of 32
AD9780/AD9781/AD9783 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.5 0.4

0.2
1.0
0
0.5
–0.2
0
–0.4

LSB
LSB

–0.5 –0.6

–0.8
–1.0
–1.0
–1.5
–1.2
–2.0 –1.4

–2.5 –1.6

06936-005

06936-008
0 16,384 32,768 49,152 65,535 0 16,384 32,768 49,152 65,535
CODE CODE

Figure 5. AD9783 INL, TA = 85°C, FS = 20 mA Figure 8. AD9783 DNL, TA = 85°C, FS = 20 mA

5 0.4

4 0.2

0
3
–0.2
2
–0.4
LSB

LSB

1 –0.6

0 –0.8

–1.0
–1
–1.2
–2
–1.4

–3
06936-006

–1.6

06936-009
0 16,384 32,768 49,152 65,535 0 16,384 32,768 49,152 65,535
CODE CODE

Figure 6. AD9783 INL, TA = 25°C, FS = 20 mA Figure 9. AD9783 DNL, TA = 25°C, FS = 20 mA

5 1.0

4 0.8

0.6
3
0.4
2
0.2
LSB

LSB

1 0

0 –0.2

–0.4
–1
–0.6
–2
–0.8

–3 –1.0
06936-007

06936-010

0 16,384 32,768 49,152 65,535 0 16,384 32,768 49,152 65,535

CODE CODE

Figure 7. AD9783 INL, TA = −40°C, FS = 20 mA Figure 10. AD9783 DNL, TA = −40°C, FS = 20 mA

Rev. C | Page 10 of 32
Data Sheet AD9780/AD9781/AD9783
0.4 0.059
0.3

0.2
–0.060
0.1

0
LSB

–0.1

LSB
–0.179

–0.2

–0.3
–0.297
–0.4

–0.5

–0.6

06936-011
–0.416

06936-014
0 4096 8192 12,288 16,383
0 4096 8192 12,288 16,383
CODE
CODE

Figure 11. AD9781 INL, TA = 85°C, FS = 20 mA Figure 14. AD9781 DNL, TA = 85°C, FS = 20 mA

0.6 0.1

0.4
0
0.2
–0.1
0
LSB

LSB

–0.2 –0.2

–0.4
–0.3
–0.6

–0.4
–0.8

–1.0 –0.5
06936-012

06936-015
0 4096 8192 12288 16,383 0 4096 8192 12,288 16,383
CODE CODE

Figure 12. AD9781 INL, TA = −40°C, FS = 20 mA Figure 15. AD9781 DNL, TA = −40°C, FS = 20 mA

0.2 0.2

0.1 0.1

0 0

–0.1 –0.1
LSB

LSB

–0.2 –0.2

–0.3 –0.3

–0.4 –0.4

–0.5 –0.5

–0.6 –0.6
06936-013

06936-016

0 1024 2048 3072 4096 0 1024 2048 3072 4096

CODE CODE

Figure 13. AD9780 INL, TA = −40°C, FS = 20 mA Figure 16. AD9780 INL, TA = 85°C, FS = 20 mA

Rev. C | Page 11 of 32
AD9780/AD9781/AD9783 Data Sheet
90
100
85 95

80 250MSPS 90

400MSPS 85 +25°C
75
80 –40°C
SFDR (dBc)

70

SFDR (dBc)
75
65
70
60 65
+85°C
55 60
500MSPS
55
50
50
45
45
40

06936-017
0 50 100 150 200 250 300 350 400 450 500 40

06936-020
0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz)
fOUT (MHz)
Figure 17. AD9783 SFDR vs. fOUT Over fDAC in Baseband and Mix Modes, Figure 20. AD9783 SFDR vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA
FS = 20 mA

100 100
95 95
90 90
250MSPS
85 20mA 85
80 30mA 80
SFDR (dBc)

IMD (dBc)

75 75
70 70
65 65 400MSPS

60 60
55 10mA 55
500MSPS
50 50
45 45
40 40

06936-021
06936-018

0 25 50 75 100 125 150 175 200 225 250 0 50 100 150 200 250 300 350 400 450 500
fOUT (MHz) fOUT (MHz)

Figure 18. AD9783 SFDR vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS Figure 21. AD9783 IMD vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA

100 100
95 95
90 90
85 85 10mA

80 –3dBFS 80 20mA
SFDR (dBc)

75 75
IMD (dBc)

70 70 30mA
65 –6dBFS 65
60 0dBFS 60
55 55
50 50
45 45
40 40
06936-019

06936-022

0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz) fOUT (MHz)

Figure 19. AD9783 SFDR vs. fOUT Over Digital Input Level, Figure 22. AD9783 IMD vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
TA = 25°C, at 500 MSPS, FS = 20 mA

Rev. C | Page 12 of 32
Data Sheet AD9780/AD9781/AD9783
100 –140

95 –143
–6dBFS
90
–146
85 –3dBFS
–149
80

NSD (dBm/Hz)
–152
75
IMD (dBc)

70 –155
250MSPS
65 0dBFS –158
60
–161
55
–164 500MSPS
50 400MSPS
–167
45
40 –170

06936-026
06936-023
0 30 60 90 120 150 180 210 240 0 50 100 150 200 250 300 350 400 450 500
fOUT (MHz) fOUT (MHz)

Figure 23. AD9783 IMD vs. fOUT Over Digital Input Level, TA = 25°C, at Figure 26. AD9783 Eight-Tone NSD vs. fOUT Over fDAC Baseband and
500 MSPS, FS = 20 mA Mix Modes, FS = 20 mA

100 –140

95 –143
90
–146
85
+85°C
–149
80
NSD (dBm/Hz)
+85°C
–152
IMD (dBc)

75 +25°C
70 –155 +25°C
–40°C
65 –158
60 –40°C
–161
55
–164
50

45 –167

40 –170
06936-024

06936-027
0 30 60 90 120 150 180 210 240 0 25 50 75 100 125 150 175 200 225 250
fOUT (MHz) fOUT (MHz)

Figure 24. AD9783 IMD vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA Figure 27. AD9783 One-Tone NSD vs. fOUT Over Temperature, at 500 MSPS,
FS = 20 mA

–140 –140

–143 –143

–146 –146

–149 –149
250MSPS
NSD (dBm/Hz)
NSD (dBm/Hz)

–152 –152

–155 500MSPS –155

–158 –158
+85°C

–161 –161
400MSPS
–164 –164
+25°C

–167 –167 –40°C

–170
06936-028

–170
06936-025

0 50 100 150 200 250 300 350 400 450 500 0 25 50 75 100 125 150 175 200 225 250

fOUT (MHz) fOUT (MHz)

Figure 25. AD9783 One-Tone NSD vs. fOUT Over fDAC Baseband and Mix Modes, Figure 28. AD9783 Eight-Tone NSD vs. fOUT Over Temperature, at 500 MSPS,
FS = 20 mA FS = 20 mA

Rev. C | Page 13 of 32
AD9780/AD9781/AD9783 Data Sheet
–50 –50

–55 –55

–60 –60

–65 491.52MSPS –65 0dB

ACLR (dBc)
ACLR (dBc)

245.76MSPS
–70 –70
–3dB
–75 –75

–80 –80

–85 –85

–90 –90

06936-032
0 100 200 300 400 500

06936-029
0 100 200 300 400 500
fOUT (MHz) fOUT (MHz)

Figure 29. AD9783 ACLR for First Adjacent Band One-Carrier W-CDMA Figure 32. AD9783 ACLR for First Adjacent Channel Two-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA

–50 –50

–55 –55

–60 –60

–65 –65
ACLR (dBc)
ACLR (dBc)

–70 –70 –3dB

245.76MSPS 491.52MSPS
–75 –75

–80 –80
0dB

–85 –85

–90 –90

06936-033
0 100 200 300 400 500
06936-030

0 100 200 300 400 500

fOUT (MHz) fOUT (MHz)

Figure 30. AD9783 ACLR for Second Adjacent Band One-Carrier W-CDMA Figure 33. AD9783 ACLR for Second Adjacent Channel Two-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA

–50 –50

–55 –55

–60 –60

–65 –65
ACLR (dBc)
ACLR (dBc)

–70 245.76MSPS –70 –3dB

491.52MSPS
–75 –75

–80 –80
0dB
–85
06936-034

–85

–90 –90
0 100 200 300 400 500
06936-031

0 100 200 300 400 500

fOUT (MHz) fOUT (MHz)

Figure 31. AD9783 ACLR for Third Adjacent Band One-Carrier W-CDMA Figure 34. AD9783 ACLR for Third Adjacent Channel Two-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA

Rev. C | Page 14 of 32
Data Sheet AD9780/AD9781/AD9783
–50 1.0

0.5
–55
0
–60 0dB –0.5

AMPLITUDE (dBm)
–1.0 NORMAL MODE
–65
ACLR (dBc)

–1.5
–70 –2.0
–3dB
–2.5
–75
–3.0
–80 –3.5 MIX MODE

–4.0
–85
–4.5

–90 –5.0

06936-038
06936-035
0 100 200 300 400 500 0 60 120 180 240 300 360 420 480 540 600
fOUT (MHz) fOUT (MHz)

Figure 35. AD9783 ACLR for First Adjacent Channel Four-Carrier W-CDMA Figure 38. Nominal Power in the Fundamental, FS = 20 mA, at 500 MSPS,
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA
FS = 20 mA
–50 0.8

–55 0.6

–60 0.4

–65 –3dB 0.2

ACLR (dBc)

LSB

–70 0

–75 0dB –0.2

–80 –0.4

–85 –0.6

–90 –0.8

06936-039
06936-036

0 100 200 300 400 500 0 4096 8192 12,288 16,383

fOUT (MHz) CODE

Figure 36. AD9783 ACLR for Second Adjacent Channel Four-Carrier W-CDMA Figure 39. AD9781 INL, FS = 20 mA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
–50 0.1

–55
0

–60
–0.1
–65 –3dB
ACLR (dBc)

LSB

–70 –0.2

–75 0dB –0.3

–80
–0.4
–85

–0.5
06936-040

–90
06936-037

0 100 200 300 400 500 0 4096 8192 12,288 16,383

fOUT (MHz) CODE

Figure 37. AD9783 ACLR for Third Adjacent Channel Four-Carrier W-CDMA Figure 40. AD9781 DNL, FS = 20 mA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA

Rev. C | Page 15 of 32
AD9780/AD9781/AD9783 Data Sheet
100 –50
95
–55
90
85 –60
FIRST
80 ADJACENT
–65 CHANNEL
SFDR (dBc)

ACLR (dBc)
75
70 –70
65
–75
60
55 –80 THIRD
SECOND ADJACENT
50 ADJACENT CHANNEL
–85 CHANNEL
45
40 –90

06936-041

06936-044
0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 500
fOUT (MHz) fOUT (MHz)

Figure 41. AD9781 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS, Figure 44. AD9781 ACLR for One-Carrier W-CDMA Baseband and Mix Modes,
FS = 20 mA at 491.52 MSPS, FS = 20 mA

100
0.2
IMD @ 500MSPS
95
90 0.1

85
0
80
–0.1
IMD (dBc)

75
LSB

70 –0.2
65
60 –0.3

55 –0.4
50
–0.5
45
40
06936-042

0 60 120 180 240 300 360 420 480 540 600 –0.6

06936-045
0 1024 2048 3072 4096
fOUT (MHz)
CODE

Figure 42. AD9781 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS, Figure 45. AD9780 INL, FS = 20 mA
FS = 20 mA

–140 0.04
–142
–144 0.02
–146
–148 0

–150 1-TONE
–0.02
NSD (dBm/Hz)

–152
–154
LSB

–0.04
–156
8-TONE
–158 –0.06
–160
–162 –0.08
–164
–166 –0.10
–168
–170 –0.12
06936-046
06936-043

0 50 100 150 200 250 300 350 400 450 500 0 1024 2048 3072 4096
fOUT (MHz) CODE

Figure 43. AD9781 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix Figure 46. AD9780 DNL, FS = 20 mA
Modes, at 500 MSPS, FS = 20 mA

Rev. C | Page 16 of 32
Data Sheet AD9780/AD9781/AD9783
–140
100
–142
95
–144
90 –146
85 –148
–150
80

NSD (dBm/Hz)
–152 1-TONE
SFDR (dBc)

75
–154
70 –156
65 –158
–160 8-TONE
60
–162
55
–164
50 –166
45 –168
–170

06936-049
40

06936-047
0 50 100 150 200 250 300 350 400 450 500
0 50 100 150 200 250 300 350 400 450 500
fOUT (MHz) fOUT (MHz)

Figure 47. AD9780 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS, Figure 49. AD9780 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix
FS = 20 mA Modes, at 500 MSPS, FS = 20 mA

100 –50
95
90 –55

85
–60
80
FIRST
75 ACLR (dBc)
–65 ADJACENT
IMD (dBc)

70 CHANNEL
65 –70
60
55 –75

50
–80 SECOND
45 ADJACENT THIRD
CHANNEL ADJACENT
40 CHANNEL
–85
35
30 –90
06936-048

06936-050
0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 500
fOUT (MHz) fOUT (MHz)

Figure 48. AD9780 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS, Figure 50. AD9780 ACLR for One-Carrier W-CDMA Baseband and Mix Modes,
FS = 20 mA at 491.52 MSPS, FS = 20 mA

Rev. C | Page 17 of 32
AD9780/AD9781/AD9783 Data Sheet

TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL) Power Supply Rejection
Linearity error is defined as the maximum deviation of the Power supply rejection is the maximum change in the full-scale
actual analog output from the ideal output, determined by a output as the supplies are varied from minimum to maximum
straight line drawn from zero scale to full scale. specified voltages.
Differential Nonlinearity (DNL) Settling Time
DNL is the measure of the variation in analog value, normalized Settling time is the time required for the output to reach and
to full scale, associated with a 1 LSB change in digital input code. remain within a specified error band around its final value,
Monotonicity measured from the start of the output transition.
A DAC is monotonic if the output either increases or remains Spurious-Free Dynamic Range (SFDR)
constant as the digital input increases. SFDR is the difference, in decibels, between the peak amplitude
Offset Error of the output signal and the peak spurious signal between dc
Offset error is the deviation of the output current from the ideal and the frequency equal to half the input data rate.
of zero. For IOUTA, 0 mA output is expected when the inputs are Total Harmonic Distortion (THD)
all 0s. For IOUTB, 0 mA output is expected when all inputs are THD is the ratio of the rms sum of the first six harmonic com-
set to 1s. ponents to the rms value of the measured fundamental. It is
Gain Error expressed as a percentage or in decibels.
Gain error is the difference between the actual and ideal output Signal-to-Noise Ratio (SNR)
span. The actual span is determined by the difference between SNR is the ratio of the rms value of the measured output signal
the output when all inputs are set to 1s and the output when all to the rms sum of all other spectral components below the Nyquist
inputs are set to 0s. frequency, excluding the first six harmonics and dc. The value
Output Compliance Range for SNR is expressed in decibels.
Output compliance range is the range of allowable voltage at Adjacent Channel Leakage Ratio (ACLR)
the output of a current-output DAC. Operation beyond the ACLR is the ratio in dBc between the measured power within a
maximum compliance limits can cause either output stage channel relative to its adjacent channel.
saturation or breakdown, resulting in nonlinear performance. Complex Image Rejection
Temperature Drift In a traditional two-part upconversion, two images are created
Temperature drift is specified as the maximum change from around the second IF frequency. These images usually waste
the ambient (25°C) value to the value at either TMIN or TMAX. transmitter power and system bandwidth. By placing the real
For offset and gain drift, the drift is reported in ppm of full- part of a second complex modulator in series with the first
scale range (FSR) per degree Celsius. For reference drift, the complex modulator, either the upper or lower frequency image
drift is reported in ppm per degree Celsius. near the second IF can be rejected.

Rev. C | Page 18 of 32
Data Sheet AD9780/AD9781/AD9783

THEORY OF OPERATION
The AD9780/AD9781/AD9783 have a combination of features The Phase 1 instruction byte defines whether the upcoming
that make them very attractive for wired and wireless commu- data transfer is a read or write, the number of bytes in the data
nications systems. The dual DAC architecture facilitates easy transfer, and a reference register address for the first byte of the
interface to common quadrature modulators when designing data transfer. A logic high on the CSB pin followed by a logic
single sideband transmitters. In addition, the speed and low resets the SPI port to its initial state and defines the start of
performance of the devices allow wider bandwidths and more the instruction cycle. From this point, the next eight rising
carriers to be synthesized than in previously available products. SCLK edges define the eight bits of the instruction byte for the
All features and options are software programmable through current communication cycle.
the SPI port. The remaining SCLK edges are for Phase 2 of the communication
cycle, which is the data transfer between the serial port controller
SERIAL PERIPHERAL INTERFACE
and the system controller. Phase 2 can be a transfer of one, two,
SDO three, or four data bytes as determined by the instruction byte.
SDIO AD9783 Using multibyte transfers is usually preferred, although single-
SCLK
SPI
PORT
byte data transfers are useful to reduce CPU overhead or when
only a single register access is required.
06936-051

CSB
All serial port data is transferred to and from the device in
Figure 51. SPI Port synchronization with the SCLK pin. Input data is always latched
The serial peripheral interface (SPI) port is a flexible, synchron- on the rising edge of SCLK, whereas output data is always valid
ous serial communications port allowing easy interface to many after the falling edge of SCLK. Register contents change imme-
industry-standard microcontrollers and microprocessors. The diately upon writing to the last bit of each transfer byte.
port is compatible with most synchronous transfer formats, Anytime synchronization is lost, the device has the ability to
including both the Motorola SPI and Intel® SSR protocols. asynchronously terminate an I/O operation whenever the CSB pin
The interface allows read and write access to all registers that is taken to logic high. Any unwritten register content data is lost
configure the AD9780/AD9781/AD9783. Single or multiple if the I/O operation is aborted. Taking CSB low then resets the
byte transfers are supported as well as MSB-first or LSB-first serial port controller and restarts the communication cycle.
transfer formats. Serial data input/output can be accomplished INSTRUCTION BYTE
through a single bidirectional pin (SDIO) or through two The instruction byte contains the information shown in Table 9.
unidirectional pins (SDIO/SDO).
The serial port configuration is controlled by Register 0x00, Table 9.
Bits[7:6]. It is important to note that any change made to the MSB LSB
serial port configuration occurs immediately upon writing to B7 B6 B5 B4 B3 B2 B1 B0
the last bit of this byte. Therefore, it is possible with a multibyte R/W N1 N0 A4 A3 A2 A1 A0
transfer to write to this register and change the configuration in
the middle of a communication cycle. Care must be taken to Bit 7, R/W, determines whether a read or a write data transfer
compensate for the new configuration within the remaining occurs after the instruction byte write. Logic 1 indicates a read
bytes of the current communication cycle. operation. Logic 0 indicates a write operation.

Use of a single-byte transfer when changing the serial port Bits[6:5], N1 and N0, determine the number of bytes to be
configuration is recommended to prevent unexpected device transferred during the data transfer cycle. The bits decode as
behavior. shown in Table 10.

GENERAL OPERATION OF THE SERIAL INTERFACE Table 10. Byte Transfer Count
There are two phases to any communication cycle with the N1 N0 Description
AD9780/AD9781/AD9783: Phase 1 and Phase 2. Phase 1 is the 0 0 Transfer one byte
instruction cycle, which writes an instruction byte into the device. 0 1 Transfer two bytes
This byte provides the serial port controller with information 1 0 Transfer three bytes
regarding Phase 2 of the communication cycle: the data transfer 1 1 Transfer four bytes
cycle.

Rev. C | Page 19 of 32
AD9780/AD9781/AD9783 Data Sheet
Bits[4:0], A4, A3, A2, A1, and A0, determine which register is Serial Port Data I/O (SDIO)
accessed during the data transfer of the communication cycle. Data is always written into the device on this pin. However,
For multibyte transfers, this address is a starting or ending SDIO can also function as a bidirectional data output line. The
address depending on the current data transfer mode. For configuration of this pin is controlled by Register 0x00, Bit 7.
MSB-first format, the specified address is an ending address The default is Logic 0, which configures the SDIO pin as
or the most significant address in the current cycle. Remaining unidirectional.
register addresses for multiple byte data transfers are generated Serial Port Data Output (SDO)
internally by the serial port controller by decrementing from
Data is read from this pin for protocols that use separate lines
the specified address. For LSB-first format, the specified address
for transmitting and receiving data. The configuration of this
is a beginning address or the least significant address in the
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
current cycle. Remaining register addresses for multiple byte
Logic 1, the SDO pin does not output data and is set to a high
data transfers are generated internally by the serial port
impedance state.
controller by incrementing from the specified address.
MSB/LSB TRANSFERS
INSTRUCTION CYCLE DATA TRANSFER CYCLE
The serial port can support both MSB-first and LSB-first data
CSB
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format. SCLK

When using MSB-first format (LSBFIRST = 0), the instruction

and data bit must be written from MSB to LSB. Multibyte data SDIO R/W N1 N0 A4 A3 A2 A1 A0 D7 D6N D5N D30 D20 D10 D00

transfers in MSB-first format start with an instruction byte that

06936-052
D7 D6N D5N D30 D20 D10 D00
includes the register address of the most significant data byte. SDO

Subsequent data bytes are loaded into sequentially lower address Figure 52. Serial Register Interface Timing Diagram, MSB First
locations. In MSB-first mode, the serial port internal address
generator decrements for each byte of the multibyte data INSTRUCTION CYCLE DATA TRANSFER CYCLE
transfer.
CSB
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data SCLK
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte. SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N

Subsequent data bytes are loaded into sequentially higher

06936-053
D00 D10 D20 D4N D5N D6N D7N
address locations. In LSB-first mode, the serial port internal SDO

address generator increments for each byte of the multibyte Figure 53. Serial Register Interface Timing Diagram, LSB First
data transfer.
Use of a single-byte transfer when changing the serial port data tS fSCLK –1
format is recommended to prevent unexpected device behavior.
CSB
SERIAL INTERFACE PORT PIN DESCRIPTIONS tPWH tPWL
Chip Select Bar (CSB)
SCLK
Active low input starts and gates a communication cycle. It tDS
tDH
allows more than one device to be used on the same serial
06936-054

INSTRUCTION BIT 7 INSTRUCTION BIT 6

communication lines. CSB must stay low during the entire SDIO

communication cycle. Incomplete data transfers are aborted Figure 54. Timing Diagram for SPI Write Register
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high. CSB

Serial Clock (SCLK)

The serial clock pin is used to synchronize data to and from the SCLK
device and to run the internal state machines. The maximum tDV
06936-055

frequency of SCLK is 40 MHz. All data input is registered on SDIO

DATA BIT N DATA BIT N – 1
the rising edge of SCLK. All data is driven out on the falling SDO

edge of SCLK. Figure 55. Timing Diagram for SPI Read Register

Rev. C | Page 20 of 32
Data Sheet AD9780/AD9781/AD9783

SPI REGISTER MAP

Table 11.
Register Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPI Control 0x00 0x00 SDIO_DIR LSBFIRST RESET
Data Control 0x02 0x00 DATA INVDCO
Power-Down 0x03 0x00 PD_DCO PD_INPT PD_AUX2 PD_AUX1 PD_BIAS PD_CLK PD_DAC2 PD_DAC1
Setup and Hold 0x04 0x00 SET[3:0] HLD[3:0]
Timing Adjust 0x05 0x00 SAMP_DLY[4:0]
Seek 0x06 0x00 LVDS low LVDS high SEEK
Mix Mode 0x0A 0x00 DAC1MIX[1:0] DAC2MIX[1:0]
DAC1 FSC 0x0B 0xF9 DAC1FSC[7:0]
DAC1 FSC MSBs 0x0C 0x01 DAC1FSC[9:8]
AUXDAC1 0x0D 0x00 AUXDAC1[7:0]
AUXDAC1 MSB 0x0E 0x00 AUX1SGN AUX1DIR AUXDAC1[9:8]
DAC2 FSC 0x0F 0xF9 DAC2FSC[7:0]
DAC2 FSC MSBs 0x10 0x01 DAC2FSC[9:8]
AUXDAC2 0x11 0x00 AUXDAC2[7:0]
AUXDAC2 MSB 0x12 0x00 AUX2SGN AUX2DIR AUXDAC2[9:8]
BIST Control 0x1A 0x00 BISTEN BISTRD BISTCLR
BIST Result 1 Low 0x1B 0x00 BISTRES1[7:0]
BIST Result 1 High 0x1C 0x00 BISTRES1[15:8]
BIST Result 2 Low 0x1D 0x00 BISTRES2[7:0]
BIST Result 2 High 0x1E 0x00 BISTRES2[15:8]
Hardware Version 0x1F N/A VERSION[3:0] DEVICE[3:0]

Rev. C | Page 21 of 32
AD9780/AD9781/AD9783 Data Sheet

SPI REGISTER DESCRIPTIONS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted.

Table 12.
Register Address Bit Name Function
SPI Control 0x00 7 SDIO_DIR 0, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin.
1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line.
6 LSBFIRST 0, MSB first per SPI standard.
1, LSB first per SPI standard.
Only change LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
5 RESET 0, execute software reset of SPI and controllers, reload default register values
except Register 0x00.
1, set software reset, write 0 on the next (or any following) cycle to release the reset.
Data Control 0x02 7 DATA 0, DAC input data is twos complement binary format.
1, DAC input data is unsigned binary format.
4 INVDCO 1, inverts the data clock output. Used for adjusting timing of input data.
Power-Down 0x03 7 PD_DCO 1, power down data clock output driver circuit.
6 PD_INPT 1, power down input.
5 PD_AUX2 1, power down AUX2 DAC
4 PD_AUX1 1, power down AUX1 DAC.
3 PD_BIAS 1, power down voltage reference bias circuit.
2 PD_CLK 1, power down DAC clock input circuit.
1 PD_DAC2 1, power down DAC2.
0 PD_DAC1 1, power down DAC1.
Setup and Hold 0x04 7:4 SET[3:0] 4-bit value used to determine input data setup timing.
3:0 HLD[3:0] 4-bit value used to determine input data hold timing.
Timing Adjust 0x05 4:0 SAMP_DLY[4:0] 5-bit value used to optimally position input data relative to internal sampling clock.
Seek 0x06 2 LVDS low One of the LVDS inputs is above the input voltage limits of the IEEE reduced link
specification.
1 LVDS high One of the LVDS inputs is below the input voltage limits of the IEEE reduced link
specification.
0 SEEK Indicator bit used with LVDS_SET and LVDS HLD to determine input data timing
margin.
Mix Mode 0x0A 3:2 DAC1MIX[1:0] 00, selects Normal Mode.
01, selects Mix Mode.
10, selects RZ Mode.
11, selects RZ Mode.
1:0 DAC2MIX[1:0] 00, selects Normal Mode.
01, selects Mix Mode.
10, selects RZ Mode.
11, selects RZ Mode.
DAC1 FSC 0x0B 7:0 DAC1FSC[9:0] DAC1 full-scale 10-bit adjustment word.
0x0C 1:0 0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.
0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.

Rev. C | Page 22 of 32
Data Sheet AD9780/AD9781/AD9783
Register Address Bit Name Function
AUXDAC1 0x0D 7:0 AUXDAC1[9:0] AUXDAC1 output current adjustment word.
0x0E 1:0 0x3FF, sets AUXDAC1 output current to 2.0 mA.
0x200, sets AUXDAC1 output current to 1.0 mA.
0x000, sets AUXDAC1 output current to 0.0 mA.
0x0E 7 AUX1SGN 0, AUX1P output pin is active.
1, AUX1N output pin is active.
6 AUX1DIR 0, configures AUXDAC1 output to source current.
1, configures AUXDAC1 output to sink current.
DAC2 FSC 0x0F 7:0 DAC2FSC[9:0] DAC2 full-scale 10-bit adjustment word.
0x10 1:0 0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.
0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.
AUXDAC2 0x11 7:0 AUXDAC2[9:0] AUXDAC2 output current adjustment word.
0x12 1:0 0x3FF, sets AUXDAC2 output current to 2.0 mA.
0x200, sets AUXDAC2 output current to 1.0 mA.
0x000, sets AUXDAC2 output current to 0.0 mA.
0x12 7 AUX2SGN 0, AUX2P output pin is active.
1, AUX2N output pin is active.
6 AUX2DIR 0, configures AUXDAC2 output to source current.
1, configures AUXDAC2 output to sink current.
BIST Control 0x1A 7 BISTEN 1, enables and starts built-in self-test.
6 BISTRD 1, transfers BIST result registers to SPI for readback.
5 BISTCLR 1, reset BIST logic and clear BIST result registers.
BIST Result 1 0x1B 7:0 BISTRES1[15:0] 16-bit result generated by BIST 1.
0x1C 7:0
BIST Result 2 0x1D 7:0 BISTRES2[15:0] 16-bit result generated by BIST 2.
0x1E 7:0
Hardware Version 0x1F 7:4 VERSION[3:0] Read only register; indicates the version of the chip.
3:0 DEVICE[3:0] Read only register; indicates the device type.

Rev. C | Page 23 of 32
AD9780/AD9781/AD9783 Data Sheet
SPI PORT, RESET, AND PIN MODE Table 13. SPI Pin Functions (Pin Mode)
In general, when the AD9780/AD9781/AD9783 are powered Pin
Name Pin Mode Function
up, an active high pulse applied to the RESET pin follows. This
SDIO DATA (Register 0x02, Bit 7), bit value (1/0) equals pin
ensures the default state of all control register bits. In addition,
state (high/low).
once the RESET pin goes low, the SPI port can be activated;
CSB Enable mix mode. If CSB is high, Register 0x0A is set
thus, CSB must be held high. to 0x05, putting both DAC1 and DAC2 into mix mode.
For applications without a controller, the AD9780/AD9781/ SDO Enable full power-down. If SDO is high, Register 0x03
AD9783 also supports pin mode operation, which allows some is set to 0xFF.
functional options to be pin selected without the use of the SPI
port. Pin mode is enabled anytime the RESET pin is held high.
In pin mode, the four SPI port pins take on secondary
functions, as shown in Table 13.

Rev. C | Page 24 of 32
Data Sheet AD9780/AD9781/AD9783

PARALLEL DATA PORT INTERFACE

The parallel port data interface consists of up to 18 differential OPTIMIZING THE PARALLEL PORT TIMING
signals, DCO, DCI, and up to 16 data lines (D[15:0]), as shown Before outlining the procedure for determining the delay for
in Figure 56. DCO is the output clock generated by the AD9780/ SMP (that is, the positioning of DSS with respect to the data
AD9781/AD9783 that is used to clock out the data from the signals), it is worthwhile to describe the simplified block
digital data engine. The data lines transmit the multiplexed diagram of the digital data port. As can be seen in Figure 57, the
I and Q data words for the I and Q DACs, respectively. DCI data signals are sampled on the rising and falling edges of DSS.
provides timing information about the parallel data and signals From there, the data is demultiplexed and retimed before being
the I/Q status of the data. sent to the DACs.
As diagrammed in Figure 56, the incoming LVDS data is The clock input signal provides timing information about the
latched by an internally generated clock referred to as the data parallel data, as well as indicating the destination (that is, I DAC
sampling signal (DSS). DSS is a delayed version of the main or Q DAC) of the data. A delayed version of DCI is generated
DAC clock signal, CLKP/CLKN. Optimal positioning of the by a delay element, SET, and is referred to as DDCI. DDCI is
rising and falling edges of DSS with respect to the incoming sampled by a delayed version of the DSS signal, labeled as DDSS
data signals results in the most robust transmission of the DAC in Figure 56. DDSS is simply DSS delayed by a period of time,
data. Positioning the edges of DSS with respect to the data HLD. The pair of delays, SET and HLD, allows accurate timing
signals is achieved by selecting the value of a programmable information to be extracted from the clock input. Increasing the
delay element, SMP. A procedure for determining the optimal delay of the HLD block results in the clock input being sampled
value of SMP is given in the Optimizing the Parallel Port later in its cycle. Increasing the delay of the SET block results in
Timing section. the clock input being sampled earlier in its cycle. The result of
In addition to properly positioning the DSS edges, maximizing this sampling is stored and can be queried by reading the SEEK
the opening of the eye in the clock input (DCIP/DCIN) and bit. Because DSS and the clock input signal are the same
data signals improves the reliability of the data port interface. frequency, the SEEK bit must be a constant value. By varying
The two sources of degradation that reduce the eye in the clock the SET and HLD delay blocks and seeing the effect on the
input and data signals are the jitter on these signals and the SEEK bit, the setup-and-hold timing of DSS with respect to
skew between them. Therefore, it is recommended that the clock clock input (and, hence, data) can be measured.
input signals be generated in the same manner as the data
DATA I0 Q0 I1 Q1 I2 Q2
signals with the same output driver and data line routing. In
other words, it must be implemented as a 17th data line with an DCIP/DCIN
alternating (010101 …) bit sequence. tHLD0
tHLD0
D15:D0
I DAC
FF DSS

06936-072
RETIMING
AND
FF DEMUX SAMPLE 1 SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5 SAMPLE 6
Q DAC
Figure 57. Timing Diagram of Parallel Interface

DCIP/DCIN DDCI The incremental units of SET, HLD, and SMP are in units of
SET_DLY
FF SEEK
real time, not fractions of a clock cycle. The nominal step size
HLD_DLY
DDSS for SET and HLD is 80 ps. The nominal step size for SMP is
160 ps. Note that the value of SMP refers to Register 0x05,
DSS CLOCK CLK
SMP_DLY
DISTRIBUTION Bits[4:0], SET refers to Register 0x04, Bits[7:4], and HLD refers
06936-071

DCOP/DCON to Register 0x04, Bits[3:0].

Figure 56. Digital Data Port Block Diagram A procedure for configuring the device to ensure valid sampling
of the data signals follows. Generally speaking, the procedure
begins by building an array of setup-and-hold values as the sample
delay is swept through a range of values. Based on this infor-
mation, a value of SMP is programmed to establish an optimal
sampling point. This new sampling point is then double-checked
to verify that it is optimally set.

Rev. C | Page 25 of 32
AD9780/AD9781/AD9783 Data Sheet
Building the Array Table 14 shows example arrays taken at DAC sample rates of
The following procedure is used to build the array: 200 MHz, 400 MHz, and 500 MHz. It must be noted that the
delay from the DCO input to the DCI output of the data source
1. Set the values of SMP, SET, and HLD to 0. Read and record
has a profound effect on when the SEEK bit toggles over the
the value of the SEEK bit.
range of SMP values. Therefore, the tables generated in any
2. With SMP and SET set to 0, increment the HLD value until
particular system do not necessarily match the example timing
the SEEK bit toggles, and then record the HLD value. This
data arrays in Table 14.
measures the hold time as shown in Figure 57.
3. With SMP and HLD set to 0, increment the SET value until As may be seen in Table 14, at 500 MHz the device has only two
the SEEK bit toggles, and then record the SET value. This working SMP settings. There is no way to monitor timing
measures the setup time as shown in Figure 57. margin in real time, so the output must be interrupted to check
4. Set the value of SET and HLD to 0. Increment the value of or correct timing errors. The device must not be clocked above
SMP and record the value of the SEEK bit. 500 MHz in applications where 100% up time is a requirement.
5. Increment HLD until the SEEK bit toggles, and then record Determining the SMP Value
the HLD value. Set HLD to 0 and increment SET until the Once the timing data array has been built, the value of SMP can
SEEK bit toggles, and then record the SET value. be determined using the following procedure:
6. Repeat Step 4 and Step 5 until the procedure has been
completed for SMP values from 0 to 31. 1. Look for the SMP value that corresponds to the 0-to-1
transition of the SEEK bit in the table. In the 500 MHz case
Note that while building the table, a value for either SET or from Table 14, this occurs for an SMP value of 6.
HLD may not be found to make the SEEK bit toggle. In this 2. Look for the SMP value that corresponds to the 1-to-0
case, assume a value of 15. transition of the SEEK bit in the table. In the 500 MHz case
from Table 14, this occurs for an SMP value of 11.
Table 14. Timing Data Arrays
3. The same two values found in Step 1 and Step 2 indicate
fDACCLK = 200 MHz fDACCLK = 400 MHz fDACCLK = 500 MHz
the valid sampling window. In the 500 MHz case, this
SMP SEEK SET HLD SEEK SET HLD SEEK SET HLD
0 0 6 15 0 2 13 0 0 11
occurs for an SMP value of 11.
1 0 8 15 0 4 11 0 2 9 4. The optimal SMP value in the valid sampling window is
2 0 10 15 0 6 9 0 3 7 where the following two conditions are true: SET < HLD
3 0 12 15 0 8 7 0 5 5 and |HLD − SET| is the smallest value.
4 0 15 15 0 10 4 0 8 2
In the 500 MHz case, the optimal SMP value is 7.
5 0 15 13 0 12 2 0 10 1
6 0 15 11 0 14 1 1 1 9 After programming the calculated value of SMP (referred to as
7 0 15 9 1 1 13 1 2 7 SMPOPTIMAL), the configuration must be tested to verify that
8 0 15 7 1 3 11 1 4 4 there is sufficient timing margin. This can be accomplished by
9 0 15 5 1 4 9 1 7 2 ensuring that the SEEK bit reads back as a 1 for SMP values
10 0 15 3 1 6 7 1 9 1
equal to SMPOPTIMAL + 1 and SMPOPTIMAL − 1. Also, it can be
11 0 15 1 1 8 5 0 1 10
noted that the sum of SET and HLD must be a minimum of 8. If
12 0 15 0 1 10 3 0 2 8
13 1 1 15 1 12 1 0 4 7
the sum is lower than this, you must check for excessive jitter on
14 1 4 15 0 0 15 0 6 4 the clock input line and check that the frequency of the clock
15 1 6 15 0 2 13 0 9 2 input does not exceed the data sheet maximum of 500 MHz (or
16 1 8 15 0 4 11 0 11 0 1000 Mbps).
17 1 10 15 0 6 9 1 1 8 As mentioned previously, low jitter and skew between the input
18 1 12 15 0 7 7 1 3 7
data bits and DCI are critical for reliable operation at the maxi-
19 1 13 15 0 9 5 1 5 5
mum input data rates. Figure 58 shows the eye diagram for the
20 1 15 13 0 11 3 1 7 2
21 1 15 11 0 13 1 1 9 1
input data signals that were used to collect the data in Table 14.
22 1 15 9 0 15 0 0 1 10
23 1 15 7 1 2 11 0 2 8
24 1 15 5 1 4 9 0 4 6
25 1 15 3 1 6 7 0 7 4
26 1 15 1 1 8 5 0 9 2
27 1 15 0 1 9 3 0 10 0
28 0 1 15 1 11 2 1 1 8
29 0 1 15 1 11 2 1 1 8
30 0 1 15 1 11 2 1 1 8
31 0 1 15 1 11 2 1 1 8

Rev. C | Page 26 of 32
Data Sheet AD9780/AD9781/AD9783
DRIVING THE CLK INPUT
The CLK input requires a low jitter differential drive signal. It is
a PMOS input differential pair powered from the 1.8 V supply;
therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
V1: 296mV from 200 mV p-p to 1 V p-p about the 400 mV common-mode
V2: –228mV
1 ΔV: –524mV voltage. CLK can be driven by an offset ac-coupled signal, as
shown in Figure 59.
0.1µF
P_IN CLKP
50Ω

06936-076
VCM = 400mV
50Ω
CH1 100mV 125ps/DIV 2.12ns A CH1 58mV

06936-056
20GSPS IT 2.5ps/PT N_IN CLKN
Figure 58. Eye Diagram of Data Source Used in Building the 500 MHz Timing 0.1µF
Data Array of Table 14 Figure 59. DAC CLK Drive Circuit
Over temperature, the valid sampling window shifts. Therefore, If a clean sine clock is available, it can be transformer-coupled
when attempting operation of the device over 500 MHz, the to CLKP and CLKN as shown in Figure 60. Use of a CMOS or
timing must be optimized again whenever the device undergoes TTL clock is also acceptable for lower sample rates. It can then
a temperature change of more than 20oC. Another consideration be ac-coupled, as described in this section. Alternatively, it can
in the timing of the digital data port is the propagation delay be transformer-coupled and clamped, as shown in Figure 60.
variation from the clock output (DCOP/DCON) to the clock 0.1µF 50Ω
TTL OR CMOS
input. If this varies significantly over time (more than 25% of CLK INPUT CLKP

SET or HLD) due to temperature changes or other effects,

repeat this timing calibration procedure.
CLKN
50Ω BAV99ZXCT
At sample rates of ≤400 MSPS, the interface timing margin is HIGH SPEED
sufficient to allow for a simplified procedure. In this case, the

06936-057
DUAL DIODE

SEEK bit can be recorded as SMP is swept through the range VCM = 400mV

from 0 to 31. The center of the first valid sampling window can Figure 60. TTL or CMOS DAC CLK Drive Circuit
then be chosen as the optimal value of SMP. Using the 400 MHz A simple bias network for generating the 400 mV common-
case from Table 14 as an example, the first valid sampling mode voltage is shown in Figure 61. It is important to use
window occurs for SMP values of 7 to 13. The center of this CVDD18 and CGND for the clock bias circuit. Any noise or
window is 10, so 10 can be used as the optimal SMP value. other signal coupled onto the clock is multiplied by the DAC
BIST OPERATION digital input signal and can degrade the DAC’s performance.
The BIST feature in the AD9780/AD9781/AD9783 is a simple VCM = 400mV

type adder and is a user synchronizable BIST feature. In CVDD18

Register 0x1A, write 0x20 then 0x00 to clear the BIST registers 1kΩ

while writing zeros to the data bits for at least eight clock cycles 1nF
06936-058

287Ω 0.1µF 1nF

to propagate to the BIST signature module. Then enable BIST CGND

by writing 0x80 to Register 0x1A. Next, begin writing a known Figure 61. DAC CLK VCM Generator Circuit
set of vectors to the data inputs. Proceed by writing zeros into
the bits after the vectors while the BIST read is being performed.
Perform a BIST read by writing 0xC0 to Register 0x1A to
receive the unique sum of rising edge data in Register 0x1B
and Register 0x1C and a unique sum of falling edge data in
Register 0x1D and Register 0x1E. These register contents must
always give the same values for the same vectors
each time they are sent.

Rev. C | Page 27 of 32
AD9780/AD9781/AD9783 Data Sheet
FULL-SCALE CURRENT GENERATION The current output appearing at IOUTP and IOUTN is a function of
Internal Reference both the input code, and IFS and can be expressed as
Full-scale current on the I DAC and Q DAC can be set from IOUTP = (DAC DATA/2N) × IFS (1)
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is IOUTN = ((2N − 1) − DAC DATA)/2N × IFS (2)
used to set up a current in an external resistor connected to
where DAC DATA = 0 to 2 − 1 (decimal representation).
N
FS ADJ (Pin 54). A simplified block diagram of the reference
circuitry is shown in Figure 62. The recommended value for The two current outputs typically drive a resistive load directly
the external resistor is 10 kΩ, which sets up an IREFERENCE in the or via a transformer. If dc coupling is required, IOUTP and IOUTN
resistor of 120 μA, which in turn provides a DAC output full- must be connected to matching resistive loads (RLOAD) that are tied
scale current of 20 mA. Because the gain error is a linear function to analog common (AVSS). The single-ended voltage output
of this resistor, a high precision resistor improves gain matching appearing at the IOUTP and IOUTN pins is
to the internal matching specification of the devices. Internal VOUTP = IOUTP × RLOAD (3)
current mirrors provide a current-gain scaling, where I DAC or
VOUTN = IOUTN × RLOAD (4)
Q DAC gain is a 10-bit word in the SPI port register. The default
value for the DAC gain registers gives a full-scale current output Note that to achieve the maximum output compliance of 1 V at
(IFS) of approximately 20 mA, where IFS is equal to the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN must not
IFS = (86.6 + (0.220 × DAC gain)) × 1000/R
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
There are two distinct advantages to operating the AD9780/
AD9783
AD9781/AD9783 differentially. First, differential operation
I DAC GAIN
1.2V BAND GAP I DAC helps cancel common-mode error sources associated with IOUTP
REFIO
CURRENT DAC FULL-SCALE
and IOUTN, such as noise, distortion, and dc offsets. Second, the
0.1µF FS ADJ SCALING REFERENCE CURRENT differential code-dependent current and subsequent output
10kΩ Q DAC
voltage (VDIFF) is twice the value of the single-ended voltage
06936-059

Q DAC GAIN
output (VOUTP or VOUTN), providing 2× signal power to the load.
Figure 62. Reference Circuitry VDIFF = (IOUTP – IOUTN) × RLOAD (5)
35
ANALOG MODES OF OPERATION
30
The AD9780/AD9781/AD9783 use a proprietary quad-switch
architecture that lowers the distortion of the DAC by eliminating a
25
code-dependent glitch that occurs with conventional dual-switch
architectures. This architecture eliminates the code-dependent
IFS (mA)

20
glitches, but creates a constant glitch at a rate of 2 × fDAC. For
communications systems and other applications requiring good
15 frequency domain performance from the DAC, this is seldom
problematic.
10 The quad-switch architecture also supports two additional
modes of operation: mix mode and return-to-zero mode. The
waveforms of these two modes are shown in Figure 64. In mix
06936-060

5
0 256 512 768 1024
DAC GAIN CODE mode, the output is inverted every other half clock cycle. This
Figure 63. IFS vs. DAC Gain Code effectively chops the DAC output at the sample rate. This chop-
ping has the effect of frequency shifting the sinc roll-off from dc
DAC TRANSFER FUNCTION to fDAC. Additionally, there is a second subtle effect on the output
Each DAC output of the AD9780/AD9781/AD9783 drives two spectrum. The shifted spectrum is also shaped by a second sinc
complementary current outputs, IOUTP and IOUTN. IOUTP provides function with a first null at 2 × fDAC. The reason for this shaping
a near IFS when all bits are high. For example, is that the data is not continuously varying at twice the clock
DAC CODE = 2N − 1 rate, but is simply repeated.
where N = 12/14/16 bits for AD9780/AD9781/AD9783
(respectively), while IOUTN provides no current.

Rev. C | Page 28 of 32
Data Sheet AD9780/AD9781/AD9783
In return-to-zero mode, the output is set to midscale every Auxiliary DACs
other half clock cycle. The output is similar to the DAC output Two auxiliary DACs are provided on the AD9780/AD9781/
in normal mode except that the output pulses are half the width AD9783. A functional diagram is shown in Figure 66. The
and half the area. Because the output pulses have half the width, auxiliary DACs are current output devices with two output
the sinc function is scaled in frequency by two and has a first pins, AUXP and AUXN. The active pin can be programmed to
null at 2 × fDAC. Because the area of the pulses is half that of the either source or sink current. When either sinking or sourcing,
pulses in normal mode, the output power is half the normal the full-scale current magnitude is 2 mA. The available compliance
mode output power. range at the auxiliary DAC outputs depends on whether the output
INPUT DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 is configured to sink or source current. When sourcing current,
the compliance voltage is 0 V to 1.6 V, but when sinking current,
DAC CLK
the output compliance voltage is reduced to 0.8 V to 1.6 V. Either
output can be used, but only one output of the AUX DAC (P or
N) is active at any time. The inactive pin is always in a high
QUAD-SWITCH t
DAC OUTPUT impedance state (>100 kΩ).
(fS MIX MODE)
0mA
TO
2mA
AUXP
VBIAS

QUAD-SWITCH
DAC OUTPUT t AUXN
(RETURN-TO- 0mA

06936-063
TO SINK POSITIVE
ZERO MODE)
06936-061

2mA OR OR
SOURCE NEGATIVE

Figure 66. Auxiliary DAC Functional Diagram

Figure 64. Mix Mode and Return-to-Zero Mode DAC Waveforms

The functions that shape the output spectrums for the three In a single sideband transmitter application, the combination of
modes of operation, normal mode, mix mode, and return-to- the input referred dc offset voltage of the quadrature modulator
zero mode, are shown in Figure 65. Switching between the and the DAC output offset voltage can result in local oscillator
analog modes reshapes the sinc roll-off inherent at the DAC (LO) feedthrough at the modulator output, which degrades system
output. This ability to change modes in the AD9780/AD9781/ performance. The auxiliary DACs can be used to remove the dc
AD9783 makes the parts suitable for direct IF applications. The offset and the resulting LO feedthrough. The circuit configura-
user can place a carrier anywhere in the first three Nyquist tion for using the auxiliary DACs for performing dc offset
zones depending on the operating mode selected. The perfor- correction depends on the details of the DAC and modulator
mance and maximum amplitude in all three Nyquist zones is interface. An example of a dc-coupled configuration with low-
impacted by this sinc roll-off depending on where the carrier is pass filtering is shown in Figure 67.
QUADRATURE
placed, as shown in Figure 65. MODULATOR V+
0
MIX
RETURN-TO-ZERO
AD9783
AUX QUAD MOD
DAC1 OR I OR Q INPUTS
–10
DAC2

NORMAL
T(f) (dB)

–20

AD9783 OPTIONAL
DAC1 OR PASSIVE
FILTERING
DAC2
–30
06936-064

25Ω TO 50Ω 25Ω TO 50Ω

Figure 67. DAC DC-Coupled to Quadrature Modulator with a Passive DC Shift

–40
06936-062

0 0.5 1.0 1.5 2.0

(fS)

Figure 65. Transfer Function for Each Analog Operating Mode

Rev. C | Page 29 of 32
AD9780/AD9781/AD9783 Data Sheet
POWER DISSIPATION
Figure 68 through Figure 73 show the power dissipation of the part in single DAC and dual DAC modes.
0.50 0.50

0.45 0.45

0.40 0.40

0.35 0.35
POWER (W)

0.30

POWER (W)
0.30

0.25 0.25

0.20 0.20

0.15 0.15

0.10 0.10

0.05 0.05

0 0

06936-068
06936-065
0 100 200 300 400 500 0 100 200 300 400 500
CLOCK SPEED (MSPS) CLOCK SPEED (MSPS)

Figure 68. Power Dissipation, I Data Only, Single DAC Mode Figure 71. Power Dissipation, I and Q Data, Dual DAC Mode
0.200 0.200

0.175 0.175

0.150 0.150

0.125 0.125
POWER (W)
POWER (W)

0.100 0.100
DVDD18
0.075 0.075
DVDD18
0.050 0.050 CVDD

CVDD
0.025 0.025

0 0

06936-069
06936-066

0 100 200 300 400 500 0 100 200 300 400 500
CLOCK SPEED (MSPS) CLOCK SPEED (MSPS)

Figure 69. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply, Figure 72. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply,
I Data Only I and Q Data, Dual DAC Mode
0.200 0.200

0.175 0.175 AVDD33

0.150 0.150

0.125 0.125
POWER (W)

POWER (W)

AVDD33
0.100 0.100

0.075 0.075

0.050 DVDD33 0.050

DVDD33
0.025 0.025

0 0
06936-067

06936-070

0 100 200 300 400 500 0 100 200 300 400 500
CLOCK SPEED (MSPS) CLOCK SPEED (MSPS)

Figure 70. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply, Figure 73. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply,
I Data Only I and Q Data, Dual DAC Mode

Rev. C | Page 30 of 32
Data Sheet AD9780/AD9781/AD9783

OUTLINE DIMENSIONS
10.10 0.60
10.00 SQ 0.60 0.42
9.90 0.42 0.24
0.24
55 72 1 PIN 1
54 INDICATOR
PIN 1
INDICATOR
9.85 0.50
9.75 SQ BSC
TOP VIEW 9.65 EXPOSED 4.70
PAD BSC SQ

(BOTTOM VIEW)

0.50
0.40 37 18
36 19
0.30

12° MAX 0.80 MAX 8.50 REF

1.00
0.65 TYP
0.85
0.05 MAX FOR PROPER CONNECTION OF
0.80
0.02 NOM THE EXPOSED PAD, REFER TO
COPLANARITY THE PIN CONFIGURATION AND
SEATING 0.30 FUNCTION DESCRIPTIONS
0.20 REF 0.08
PLANE 0.23 SECTION OF THIS DATA SHEET.

06-07-2012-A
0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4

Figure 74. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm, Very Thin Quad
(CP-72-1)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD9780BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9780BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9781BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9781BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9783BCPZ −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9783BCPZRL −40°C to +85°C 72-Lead LFCSP_VQ CP-72-1
AD9783-DPG2-EBZ Evaluation Board
1
Z = RoHS Compliant Part.

Rev. C | Page 31 of 32
AD9780/AD9781/AD9783 Data Sheet

NOTES

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registered trademarks are the property of their respective owners.
D06936-0-8/17(C)

Rev. C | Page 32 of 32