® ADS

128
6
ADS1286
ADS
128
6

12-Bit Micro Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES DESCRIPTION
● SERIAL INTERFACE The ADS1286 is a 12-bit, 20kHz analog-to-digital
● GUARANTEED NO MISSING CODES converter with a differential input and sample and hold
amplifier and consumes only 250µA of supply cur-
● 20kHz SAMPLING RATE
rent. The ADS1286 offers an SPI and SSI compatible
● LOW SUPPLY CURRENT: 250µA serial interface for communications over a two or three
wire interface. The combination of a serial two wire
APPLICATIONS interface and micropower consumption makes the
ADS1286 ideal for remote applications and for those
● REMOTE DATA ACQUISITION requiring isolation.
● ISOLATED DATA ACQUISITION The ADS1286 is available in a 8-pin plastic mini DIP
● TRANSDUCER INTERFACE and a 8-lead SOIC.
● BATTERY OPERATED SYSTEMS

SAR Control

VREF

DOUT
+In
CDAC Serial
–In Interface DCLOCK
CS/SHDN
S/H Amp Comparator

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©
1996 Burr-Brown Corporation PDS-1335B Printed in U.S.A. October, 1998

SBAS053
SPECIFICATIONS
At TA = TMIN to TMAX, +VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, , fCLK = 16 • fSAMPLE, unless otherwise specified.

ADS1286, ADS1286A ADS1286K, ADS1286B ADS1286C, ADS1286L

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

ANALOG INPUT
Full-Scale Input Range +In – (–In) 0 VREF ✻ ✻ ✻ ✻ V
Absolute Input Voltage +In –0.2 VCC +0.2 ✻ ✻ ✻ ✻ V
–In –0.2 +0.2 ✻ ✻ ✻ ✻ V
Capacitance 25 ✻ ✻ pF
Leakage Current ±1 ✻ ✻ µA
SYSTEM PERFORMANCE
Resolution 12 ✻ ✻ Bits
No Missing Codes 12 ✻ ✻ Bits
Integral Linearity ±1 ±2 ✻ ✻ ±0.5 ±1 LSB
Differential Linearity ±0.5 ±1.0 ✻ ±0.75 ±0.25 ±0.75 LSB
Offset Error 0.75 ±3 ✻ ✻ ✻ ✻ LSB
Gain Error ±2 ±8 ✻ ✻ ✻ ✻ LSB
Noise 50 ✻ ✻ µVrms
Power Supply Rejection 82 ✻ ✻ dB
SAMPLING DYNAMICS
Conversion Time 12 ✻ ✻ Clk Cycles
Acquisition Time 1.5 ✻ ✻ Clk Cycles
Small Signal Bandwidth 500 ✻ ✻ kHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion VIN = 5.0Vp-p at 1kHz –85 ✻ ✻ dB
VIN = 5.0Vp-p at 5kHz –83 ✻ ✻ dB
SINAD VIN = 5.0Vp-p at 1kHz 72 ✻ ✻ dB
Spurious Free Dynamic Range VIN = 5.0Vp-p at 1kHz 90 ✻ ✻ dB
REFERENCE INPUT
REF Input Range 1.25 2.5 VCC+0.05V ✻ ✻ ✻ ✻ ✻ ✻ V
Input Resistance CS = VCC 5000 ✻ ✻ MΩ
CS = GND, fCLK = 0Hz 5000 ✻ ✻ MΩ
Current Drain CS = VCC 0.01 2.5 ✻ ✻ ✻ ✻ µA
tCYC ≥ 640µs, fCLK ≤ 25kHz 2.4 20 ✻ ✻ ✻ ✻ µA
tCYC = 80µs, fCLK = 200kHz 2.4 20 ✻ ✻ ✻ ✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻ ✻
Logic Levels:
VIH IIH = +5µA 3 +VCC ✻ ✻ ✻ ✻ V
VIL IIL = +5µA 0.0 0.8 ✻ ✻ ✻ ✻ V
VOH IOH = 250µA 3 +VCC ✻ ✻ ✻ ✻ V
VOL IOL = 250µA 0.0 0.4 ✻ ✻ ✻ ✻ V
Data Format Straight Binary ✻ ✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
VCC +4.50 5 5.25 ✻ ✻ ✻ ✻ ✻ ✻ V
Quiescent Current, VANA tCYC ≥ 640µS, fCLK ≤ 25kHz 200 400 ✻ ✻ ✻ ✻ µA
tCYC = 90µS, fCLK = 200kHz 250 500 ✻ ✻ ✻ ✻ µA
Power Down CS = VCC 3 ✻ ✻ µA
TEMPERATURE RANGE
Specified Performance ADS1286, K, L 0 +70 ✻ ✻ ✻ ✻ °C
ADS1286A, B, C –40 +85 ✻ ✻ ✻ ✻ °C
✻ Specifications same as grade to the left.

TIMING CHARACTERISTICS
fCLK = 200kHz, TA = TMIN to TMAX.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tSMPL Analog Input Sample Time See Operating Sequence 1.5 2.0 Clk Cycles
tSMPL (MAX) Maximum Sampling Frequency ADS1286 20 kHz
tCONV Conversion Time See Operating Sequence 12 Clk Cycles
tdDO Delay TIme, DCLOCK↓ to DOUT Data Valid See Test Circuits 85 150 ns
tdis Delay TIme, CS↑ to DOUT Hi-Z See Test Circuits 25 50 ns
ten Delay TIme, DCLOCK↓ to DOUT Enable See Test Circuits 50 100 ns
thDO Output Data Remains Valid After DCLOCK↓ CLOAD = 100pF 15 30 ns
tf DOUT Fall Time See Test Circuits 70 100 ns
tr DOUT Rise Time See Test Circuits 60 100 ns
tCSD Delay Time, CS↓ to DCLOCK↓ See Operating Sequence 0 ns
tSUCS Delay Time, CS↓ to DCLOCK↑ See Operating Sequence 30 ns

ADS1286 2
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
+VCC ..................................................................................................... +6V
Analog Input ....................................................... –0.3V to (+VCC + 300mV) DISCHARGE SENSITIVITY
Logic Input ......................................................... –0.3V to (+VCC + 300mV)
Case Temperature ......................................................................... +100°C Electrostatic discharge can cause damage ranging from per-
Junction Temperature .................................................................... +150°C formance degradation to complete device failure. Burr-
Storage Temperature ..................................................................... +125°C Brown Corporation recommends that all integrated circuits
External Reference Voltage .............................................................. +5.5V
be handled and stored using appropriate ESD protection
NOTE: (1) Stresses above these ratings may permanently damage the device. methods.
ESD damage can range from subtle performance degrada-
PIN CONFIGURATION tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
VREF 1 8 +VCC published specifications.
+In 2 7 DCLOCK
ADS1286
–In 3 6 DOUT

GND 4 5 CS/SHDN

8-Pin Mini PDIP

8-Lead SOIC

PIN ASSIGNMENTS
PIN NAME DESCRIPTION
1 VREF Reference Input.
2 +In Non Inverting Input.
3 –In Inverting Input. Connect to ground or remote ground sense point.
4 GND Ground.
5 CS/SHDN Chip Select when low, Shutdown Mode when high.
6 DOUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed.
8 +VCC Power Supply.

PACKAGE/ORDERING INFORMATION
PACKAGE
INTEGRAL TEMPERATURE DRAWING
PRODUCT LINEARITY RANGE PACKAGE NUMBER(1)
ADS1286P ±2 0°C to +70°C Plastic DIP 006
ADS1286PK ±2 0°C to +70°C Plastic DIP 006
ADS1286PL ±1 0°C to +70°C Plastic DIP 006
ADS1286U ±2 0°C to +70°C SOIC 182
ADS1286UK ±2 0°C to +70°C SOIC 182
ADS1286UL ±1 0°C to +70°C SOIC 182
ADS1286PA ±2 –40°C to +85°C Plastic DIP 006
ADS1286PB ±2 –40°C to +85°C Plastic DIP 006
ADS1286PC ±1 –40°C to +85°C Plastic DIP 006
ADS1286UA ±2 –40°C to +85°C SOIC 182
ADS1286UB ±2 –40°C to +85°C SOIC 182
ADS1286UC ±1 –40°C to +85°C SOIC 182

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix
C of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3 ADS1286
TYPICAL PERFORMANCE CURVES
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.

REFERENCE CURRENT vs SAMPLE RATE REFERENCE CURRENT vs TEMPERATURE

2.5 4.0

3.5
2.0
Reference Current (µA)

Reference Current (µA)

3.0
1.5
2.5
1.0
2.0

0.5 1.5

0 1.0
0 2 4 6 8 10 12 –55 –40 –25 0 25 70 85
Sample Rate (kHz) Temperature (°C)

CHANGE IN OFFSET vs REFERENCE VOLTAGE CHANGE IN OFFSET vs TEMPERATURE

5 0.6
4.5
0.4
4
Change in Offset (LSB)

Delta from 25°C (LSB)

3.5
0.2
3
2.5 0
2
–0.2
1.5
1
–0.4
0.5
0 –0.6
1 2 3 4 5 –55 –40 –25 0 25 70 85
Reference Voltage (V) Temperature (°C)

CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL

LINEARITY vs REFERENCE VOLTAGE CHANGE IN GAIN vs REFERENCE VOLTAGE
0.10 4
Delta from +5V Reference (LSB)

3.5
0.05
3
Change in Gain (LSB)

Change in Differential
0.00
Linearity (LSB) 2.5

–0.05 2

1.5
–0.10
Change in Integral 1
–0.15 Linearity (LSB)
0.5

–0.20 0
1 2 3 4 5 1 2 3 4 5
Reference Voltage (V) Reference Voltage (V)

ADS1286 4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.

EFFECTIVE NUMBER OF BITS

vs REFERENCE VOLTAGE DIFFERENTIAL LINEARITY ERROR vs CODE
12 3.0

11.75

Differential Linearity Error (LSB)

Effective Number of Bits (rms)

2.0
11.5
1.0
11.25

11 0

10.75
–1.0
10.5
–2.0
10.25

10 –3.0
0.1 1 10 0 2048 4095
Reference Voltage (V) Code

SIGNAL-TO-(NOISE + DISTORTION) SPURIOUS FREE DYNAMIC RANGE

vs FREQUENCY AND SIGNAL-TO-NOISE RATIO vs FREQUENCY
100 100
90 90 Spurious Free Dynamic Range
Signal-to-(Noise + Distortion) (dB)

Spurious Free Dynamic Range

and Signal-to-Noise Ratio (dB)
80 80
70 70
60 60
Signal-to-Noise Ratio
50 50
40 40
30 30
20 20
10 10
0 0
0.1 1 10 0.1 1 10
Frequency (kHz) Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL TOTAL HARMONIC DISTORTION vs FREQUENCY

80 0
–10
Signal-to-(Noise + Distortion) (dB)

70
Total Harmonic Distortion (dB)

–20
60
–30
50 –40
40 –50

30 –60
–70
20
–80
10 –90
0 –100
–40 –35 –30 –25 –20 –15 –10 –5 0 0.1 1 10
Input Level (dB) Frequency (kHz)

5 ADS1286
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.

4096 POINT FFT PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

0 10
9

Peak-to-Peak Noise (LSB)

–25 8
7
Magnitude (dB)

–50 6
5
–75 4
3
–100 2
1
–125 0
0 2 4 6 0.1 1 10
Frequency (kHz) Reference Voltage (V)

POWER SUPPLY REJECTION vs RIPPLE FREQUENCY CHANGE GAIN vs TEMPERATURE

0 0.15

–10
VRIPPLE = 20mV 0.1
Power Supply Rejection (dB)

–20
Delta from 25°C (LSB)

–30 0.05

–40
0
–50

–60 –0.05

–70
–0.1
–80

–90 –0.15
1 10 100 1000 10000 –55 –40 –25 0 25 70 85
Ripple Frequency (kHz) Temperature (°C)

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE
3 400

2.5 350
Supply Current (µA)

Supply Current (µA)

2 300
fSAMPLE = 12.5kHz
1.5 250

1 200 fSAMPLE = 1.6kHz

0.5 150

0 100
–55 –40 –25 0 25 70 85 –55 –40 –25 0 25 70 85
Temperature (°C) Temperature (°C)

ADS1286 6
 TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25, VCC = +5V, VREF = +5V, fSAMPLE = 12.5kHz, fCLK = 16 • fSAMPLE, unless otherwise specified.

DIGITAL INPUT LINE THRESHOLD

INTEGRAL LINEARITY ERROR vs CODE vs SUPPLY VOLTAGE
3.0 3

Digital Input Threshold Voltage (V)

2.0 2.5
Integral Linearity Error (LSB)

1.0 2

0 1.5

–1.0 1

–2.0 0.5

–3.0 0
0 2048 4095 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Code Supply Voltage (V)

INPUT LEAKAGE CURRENT vs TEMPERATURE

10
Leakage Current (nA)

0.1

0.01
–55 –40 –25 0 25 70 85
Temperature (°C)

7 ADS1286
TIMING DIAGRAMS AND TEST CIRCUITS
1.4V

3kΩ VOH
DOUT
DOUT VOL
Test Point
tr tf
100pF
CLOAD

Load Circuit for tdDO, tr, and tf Voltage Waveforms for DOUT Rise and Fall Times tr, and tf

Test Point
DCLOCK VIL
VCC
tdDO 3kΩ tdis Waveform 2, ten
DOUT
VOH
DOUT tdis Waveform 1
100pF
VOL CLOAD
thDO

Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden

CS/SHDN VIH CS/SHDN

DOUT
90% DCLOCK 1 2
Waveform 1(1)
tdis
DOUT VOL
10% DOUT B11
Waveform 2(2)
ten
Voltage Waveforms for tdis

NOTES: (1) Waveform 1 is for an output with internal conditions such that Voltage Waveforms for ten
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.

ADS1286 8
 tCYC
CS/SHDN

tSUCS POWER
DOWN
DCLOCK
tCSD
NULL NULL
HI-Z BIT HI-Z BIT
DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1) B11 B10 B9 B8
tSMPL (MSB)
tCONV tDATA

Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.

tCYC
CS/SHDN

tSUCS POWER DOWN

DCLOCK
tCSD
NULL
HI-Z BIT HI-Z
DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(2)
tSMPL (MSB)
tCONV tDATA

Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.

tDATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.

FIGURE 1. ADS1286 Operating Sequence.

SERIAL INTERFACE leaving the DCLOCK running to clock out the LSB first
data or zeroes. If the CS input is not running rail-to-rail, the
The ADS1286 communicates with microprocessors and other input logic buffer will draw current. This current may be
external digital systems via a synchronous 3-wire serial inter- large compared to the typical supply current. To obtain the
face. DCLOCK synchronizes the data transfer with each bit lowest supply current, bring the CS pin to ground when it is
being transmitted on the falling DCLOCK edge and captured low and to supply voltage when it is high.
on the rising DCLOCK edge in the receiving system. A falling
CS initiates data transfer as shown in Figure 1. After CS falls,
the second DCLOCK pulse enables DOUT. After one null bit,
the A/D conversion result is output on the DOUT line. Bringing 1000
CS high resets the ADS1286 for the next data exchange. TA = 25°C
VCC = 5V
Supply Current (µA)

VREF = 5V
100
MICROPOWER OPERATION fCLK = 16 • fSAMPLE

With typical operating currents of 250µA and automatic

shutdown between conversions, the ADS1286 achieves ex- 10
tremely low power consumption over a wide range of
sample rates (see Figure 2). The auto-shutdown allows the
supply current to drop with sample rate.
1
0.1k 1k 10k 100k
SHUTDOWN Sample Rate (kHz)
The ADS1286 is equipped with automatic shutdown fea-
tures. The device draws power when the CS pin is LOW and FIGURE 2. Automatic Power Shutdown Between Conver-
shuts down completely when the pin is HIGH. The bias sions Allows Power Consumption to Drop with
circuit and comparator powers down and the reference input Sample Rate.
becomes high impedance at the end of each conversion

9 ADS1286
MINIMIZING POWER DISSIPATION REDUCED REFERENCE
In systems that have significant time between conversions,
the lowest power drain will occur with the minimum CS
OPERATION
LOW time. Bringing CS LOW, transferring data as quickly The effective resolution of the ADS1286 can be increased
as possible, and then bringing it back HIGH will result in the by reducing the input span of the converter. The ADS1286
lowest current drain. This minimizes the amount of time the exhibits good linearity and gain over a wide range of
device draws power. After a conversion the A/D automati- reference voltages (see Typical Performance Curves “ Change
cally shuts down even if CS is held LOW. If the clock is left in Linearity vs Reference Voltage” and “Change in Gain vs
running to clock out LSB-data or zero, the logic will draw a Reference Voltage”). However, care must be taken when
small amount of current (see Figure 3). operating at low values of VREF because of the reduced LSB
size and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
6.00 when operating at low VREF values:
TA = 25°C
5.00
VCC = +5V 1. Offset
VREF = +5V
fCLK = 16 • fSAMPLE 2. Noise
Supply Current (µA)

4.00

3.00 CS = LOW OFFSET WITH REDUCED VREF

(GND) The offset of the ADS1286 has a larger effect on the output
2.00 code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
1.00 CS HIGH becomes a larger fraction of an LSB as the size of the LSB
(VCC)
is reduced. The Typical Performance Curve “Change in
0.00
0.1 1 10 100 Offset vs Reference Voltage” shows how offset in LSBs is
Sample Rate (kHz) related to reference voltage for a typical value of VOS. For
example, a VOS of 122µV which is 0.1 LSB with a 5V
FIGURE 3. Shutdown Current with CS HIGH is Lower than reference becomes 0.5LSB with a 1V reference and 2.5LSBs
with CS LOW. with a 0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the negative input of the ADS1286.
RC INPUT FILTERING
It is possible to filter the inputs with an RC network as NOISE WITH REDUCED VREF
shown in Figure 4. For large values of CFILTER (e.g., 1µF), The total input referred noise of the ADS1286 can be
the capacitive input switching currents are averaged into a reduced to approximately 200µV peak-to-peak using a ground
net DC current. Therefore, a filter should be chosen with a plane, good bypassing, good layout techniques and minimiz-
small resistor and large capacitor to prevent DC drops across ing noise on the reference inputs. This noise is insignificant
the resistor. The magnitude of the DC current is approxi- with a 5V reference but will become a larger fraction of an
mately IDC = 20pF x VIN/tCYC and is roughly proportional to LSB as the size of the LSB is reduced.
VIN. When running at the minimum cycle time of 64µs, the
input current equals 1.56µA at VIN = 5V. In this case, a filter For operation with a 5V reference, the 200µV noise is only
resistor of 75Ω will cause 0.1LSB of full-scale error. If a 0.15LSB peak-to-peak. In this case, the ADS1286 noise will
larger filter resistor must be used, errors can be eliminated contribute virtually no uncertainty to the output code. How-
by increasing the cycle time. ever, for reduced references, the noise may become a signifi-
cant fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 2.5V reference this same
200µV noise is 0.3LSB peak-to-peak. If the reference is
RFILTER IDC
further reduced to 1V, the 200µV noise becomes equal to
VIN
0.8LSBs and a stable code may be difficult to achieve. In
this case averaging multiple readings may be necessary.
ADS1286
CFILTER

FIGURE 4. RC Input Filtering.

ADS1286 10
 +5V

+5V +5V
R8
46kΩ
0.4V
R7
R9
10Ω
R1 1kΩ
OPA237
D1 150kΩ C2 0.3V
R3 U2
0.1µF R10
500kΩ C1
MUX 1kΩ
R2 R6 VREF 10µF
59kΩ 1MΩ DCLOCK 0.2V
R11
C3 DOUT 1kΩ
TC1 ADS1286 A0
TC2 0.1µF
CS/SHDN 0.1V
Thermocouple A1
R12
TC3 C4 U1 1kΩ
R4 U3
10µF R5 C5
1kΩ
500Ω 0.1µF µP
ISO Thermal Block

3-Wire
Interface
U4

FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286.

+VCC

REF200
(100µA) 0.1µF

VREF

1 8
2 DCLOCK
DOUT µP
RTD ADS1286
CS/SHDN
3
4

FIGURE 6. ADS1286 with RTD Sensor.

11 ADS1286
 PACKAGE OPTION ADDENDUM

www.ti.com 12-Feb-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

ADS1286P LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br)
ADS1286PA LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br) A
ADS1286PAG4 LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br) A
ADS1286PC LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br) C
ADS1286PG4 LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br)
ADS1286PK LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br) K
ADS1286PL LIFEBUY PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 ADS1286P
& no Sb/Br) L
ADS1286U ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
ADS1286U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
ADS1286U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
ADS1286UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
A
ADS1286UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
A
ADS1286UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
A
ADS1286UAG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
A
ADS1286UB ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
B

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 12-Feb-2016

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

ADS1286UBG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
B
ADS1286UC ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS
& no Sb/Br) 1286U
C
ADS1286UCG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 ADS
& no Sb/Br) 1286U
C
ADS1286UG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
ADS1286UL ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
L
ADS1286UL/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
& no Sb/Br) 1286U
L

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 12-Feb-2016

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1286U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS1286UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS1286UL/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1286U/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS1286UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS1286UL/2K5 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 IMPORTANT NOTICE

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