CMOS 300 MSPS Quadrature

Complete DDS
AD9854
FEATURES Automatic bidirectional frequency sweeping
300 MHz internal clock rate Sin(x)/x correction
FSK, BPSK, PSK, chirp, AM operation Simplified control interfaces
Dual integrated 12-bit digital-to-analog converters (DACs) 10 MHz serial 2- or 3-wire SPI compatible
Ultrahigh speed comparator, 3 ps rms jitter 100 MHz parallel 8-bit programming
Excellent dynamic performance 3.3 V single supply
80 dB SFDR at 100 MHz (±1 MHz) AOUT Multiple power-down functions
4× to 20× programmable reference clock multiplier Single-ended or differential input reference clock
Dual 48-bit programmable frequency registers Small, 80-lead LQFP or TQFP with exposed pad
Dual 14-bit programmable phase offset registers APPLICATIONS
12-bit programmable amplitude modulation and
Agile, quadrature LO frequency synthesis
on/off output shaped keying function
Programmable clock generators
Single-pin FSK and BPSK data interfaces
FM chirp source for radar and scanning systems
PSK capability via input/output interface
Test and measurement equipment
Linear or nonlinear FM chirp functions with single-pin
Commercial and amateur RF exciters
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode

FUNCTIONAL BLOCK DIAGRAM

SYSTEM CLOCK DIGITAL MULTIPLIERS
DDS CORE INV
4× TO 20× 12 SINC 12
REF 12-BIT

MUX
REFERENCE REF CLK I FILTER ANALOG
I
MUX
CLK OUT
ACCUMULATOR
ACCUMULATOR

CLOCK IN MULTIPLIER DAC

BUFFER
CONVERTER
FREQUENCY

AMPLITUDE
PHASE-TO-

48 48 17 17
PHASE

SYSTEM
ACC 2
ACC 1

CLOCK DAC R SET

DIFF/SINGLE
SELECT MUX INV
SYSTEM 12 SINC 12 12-BIT
Q DAC OR ANALOG
MUX
CLOCK 48 14 FILTER OUT
MUX

CONTROL
Q DAC
DEMUX

3
FSK/BPSK/HOLD
DATA IN MUX MUX MUX 12 12 ANALOG
DELTA IN
FREQUENCY SYSTEM PROGRAMMABLE
RATE TIMER AMPLITUDE AND
CLOCK RATE CONTROL

2 48 SYSTEM 48 48 14 14 12 12 COMPARATOR
CLOCK
DELTA FREQUENCY FREQUENCY FIRST 14-BIT SECOND 14-BIT I AND Q 12-BIT 12-BIT DC CLOCK
FREQUENCY TUNING TUNING PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL OUT
WORD WORD 1 WORD 2 WORD WORD

MODE SELECT PROGRAMMING REGISTERS OSK

SYSTEM SYSTEM
CLOCK CK
Q ÷2 CLOCK
AD9854 BUS
D GND
BIDIRECTIONAL INT
INTERNAL/EXTERNAL INTERNAL I/O PORT BUFFERS
I/O UPDATE CLOCK PROGRAMMABLE +VS
UPDATE CLOCK
EXT

READ WRITE SERIAL/ 6-BIT ADDRESS 8-BIT MASTER

PARALLEL OR SERIAL PARALLEL RESET
00636-001

SELECT PROGRAMMING LOAD

LINES

Figure 1.

Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
AD9854

TABLE OF CONTENTS
Features .............................................................................................. 1 Programming the AD9854............................................................ 32

Applications....................................................................................... 1 MASTER RESET ........................................................................ 32

Functional Block Diagram .............................................................. 1 Parallel I/O Operation ............................................................... 34

Revision History ............................................................................... 3 Serial Port I/O Operation.......................................................... 34

General Description ......................................................................... 4 General Operation of the Serial Interface ................................... 36

Specifications..................................................................................... 5 Instruction Byte .......................................................................... 37

Absolute Maximum Ratings............................................................ 8 Serial Interface Port Pin Descriptions ..................................... 37

Thermal Resistance ...................................................................... 8 Notes on Serial Port Operation ................................................ 37

Explanation of Test Levels ........................................................... 8 MSB/LSB Transfers......................................................................... 38

ESD Caution.................................................................................. 8 Control Register Description.................................................... 38

Pin Configuration and Function Descriptions............................. 9 Power Dissipation and Thermal Considerations ....................... 40

Typical Performance Characteristics ........................................... 12 Thermal Impedance................................................................... 40

Typical Applications ....................................................................... 16 Junction Temperature Considerations .................................... 40

Theory of Operation ...................................................................... 19 Evaluation of Operating Conditions........................................ 41

Modes of Operation ................................................................... 19 Thermally Enhanced Package Mounting Guidelines ................ 41

Using the AD9854 .......................................................................... 29 Evaluation Board ............................................................................ 42

Internal and External Update Clock ........................................ 29 Evaluation Board Instructions.................................................. 42

On/Off Output Shaped Keying (OSK) .................................... 29 General Operating Instructions ............................................... 42

I and Q DACs.............................................................................. 30 Using the Provided Software .................................................... 44

Control DAC ............................................................................... 30 Support ........................................................................................ 44

Inverse Sinc Function ................................................................ 31 Outline Dimensions ....................................................................... 52

REFCLK Multiplier .................................................................... 31 Ordering Guide .......................................................................... 52

Rev. E | Page 2 of 52
 AD9854
REVISION HISTORY Changes to Ramped FSK (Mode 010) Section............................18
Changes to Basic FM Chirp Programming Steps Section .........23
7/07—Rev. D to Rev. E Changes to Figure 50 ......................................................................27
Changed AD9854ASQ to AD9854ASVZ ....................... Universal Changes to Evaluation Board Operating Instructions Section.40
Changed AD9854AST to AD9854ASTZ......................... Universal Changes to Filtered IOUT1 and the Filtered IOUT2 Section ...41
Changes to General Description .....................................................4 Changes to Using the Provided Software Section.......................42
Changes to Table 1 Endnotes...........................................................7 Changes to Figure 68 ......................................................................45
Changes to Absolute Maximum Ratings Section..........................8 Changes to Figure 69 ......................................................................46
Changes to Power Dissipation Section.........................................40 Updated Outline Dimensions........................................................50
Changes to Thermally Enhanced Package Mounting Changes to Ordering Guide...........................................................50
Guidelines Section......................................................................41
Changes to Figure 64 ......................................................................47 3/02—Rev. A to Rev. B
Changes to Outline Dimensions ...................................................52 Updated Format ................................................................. Universal
Changes to Ordering Guide...........................................................52 Renumbered Figures and Tables ...................................... Universal
Changes to General Description Section.......................................1
11/06—Rev. C to Rev. D Changes to Functional Block Diagram ..........................................1
Changes to General Description Section .......................................4 Changes to Specifications Section ..................................................4
Changes to Endnotes in the Power Supply Parameter .................7 Changes to Absolute Maximum Ratings Section .........................7
Changes to Absolute Maximum Ratings Section..........................8 Changes to Pin Function Descriptions ..........................................8
Added Endnotes to Table 2 ..............................................................8 Changes to Figure 3 ........................................................................10
Changes to Figure 50 ......................................................................29 Deleted two Typical Performance Characteristics Graphs........11
Changes to Power Dissipation Section.........................................39 Changes to Inverse SINC Function Section ................................28
Changes to Figure 68 ......................................................................45 Changes to Differential REFCLK Enable Section.......................28
Updated Outline Dimensions........................................................51 Changes to Figure 52 ......................................................................30
Changes to Ordering Guide...........................................................51 Changes to Parallel I/O Operation Section .................................32
9/04—Rev. B to Rev. C Changes to General Operation of the Serial Interface Section .33
Updated Format.................................................................. Universal Changes to Figure 57 ......................................................................34
Changes to Table 1 ............................................................................4 Replaced Operating Instructions Section ....................................40
Changes to Footnote 2 ......................................................................7 Changes to Figure 68 ......................................................................44
Changes to Explanation of Test Levels Section .............................8 Changes to Figure 69 ......................................................................45
Changes to Theory of Operation Section ....................................17 Changes to Customer Evaluation Board Table............................46
Changes to Single Tone (Mode 000) Section...............................17

Rev. E | Page 3 of 52
AD9854

GENERAL DESCRIPTION
The AD9854 digital synthesizer is a highly integrated device as a user-programmable control DAC if the quadrature function
that uses advanced DDS technology, coupled with two internal is not desired. When configured with the comparator, the 12-bit
high speed, high performance quadrature DACs to form a digitally control DAC facilitates static duty cycle control in high speed
programmable I and Q synthesizer function. When referenced clock generator applications.
to an accurate clock source, the AD9854 generates highly stable, Two 12-bit digital multipliers permit programmable amplitude
frequency-phase, amplitude-programmable sine and cosine modulation, on/off output shaped keying, and precise amplitude
outputs that can be used as an agile LO in communications, radar, control of the quadrature output. Chirp functionality is also
and many other applications. The innovative high speed DDS core included to facilitate wide bandwidth frequency sweeping
of the AD9854 provides 48-bit frequency resolution (1 μHz tuning applications. The programmable 4× to 20× REFCLK multiplier
resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures circuit of the AD9854 internally generates the 300 MHz system
excellent SFDR. clock from an external lower frequency reference clock. This
The circuit architecture of the AD9854 allows the generation of saves the user the expense and difficulty of implementing a
simultaneous quadrature output signals at frequencies up to 300 MHz system clock source.
150 MHz, which can be digitally tuned at a rate of up to Direct 300 MHz clocking is also accommodated with either single-
100 million new frequencies per second. The sine wave output ended or differential inputs. Single-pin conventional FSK and
(externally filtered) can be converted to a square wave by the the enhanced spectral qualities of ramped FSK are supported.
internal comparator for agile clock generator applications. The AD9854 uses advanced 0.35 μm CMOS technology to
The device provides two 14-bit phase registers and a single pin provide a high level of functionality on a single 3.3 V supply.
for BPSK operation.
The AD9854 is pin-for-pin compatible with the AD9852 single-
For higher-order PSK operation, the I/O interface can be used tone synthesizer. It is specified to operate over the extended
for phase changes. The 12-bit I and Q DACs, coupled with the industrial temperature range of −40°C to +85°C.
innovative DDS architecture, provide excellent wideband and
narrow-band output SFDR. The Q DAC can also be configured

Rev. E | Page 4 of 52
 AD9854

SPECIFICATIONS
VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ,
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted.

Table 1.
Test AD9854ASVZ AD9854ASTZ
Parameter Temp Level Min Typ Max Min Typ Max Unit
REFERENCE CLOCK INPUT CHARACTERISTICS 1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
External Reference Clock Frequency Range
REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
Duty Cycle 25°C IV 45 50 55 45 50 55 %
Input Capacitance 25°C IV 3 3 pF
Input Impedance 25°C IV 100 100 kΩ
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude 2 25°C IV 400 400 mV p-p
Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V
VIH (Single-Ended Mode) 25°C IV 2.3 2.3 V
VIL (Single-Ended Mode) 25°C IV 1 1 V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed Full I 300 200 MSPS
Resolution 25°C IV 12 12 Bits
I and Q Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA
I and Q DAC DC Gain Imbalance 3 25°C I −0.5 +0.15 +0.5 −0.5 +0.15 +0.5 dB
Gain Error 25°C I −6 +2.25 −6 +2.25 % FS
Output Offset 25°C I 2 2 μA
Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB
Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB
Output Impedance 25°C IV 100 100 kΩ
Voltage Compliance Range 25°C I −0.5 +1.0 −0.5 +1.0 V
DAC DYNAMIC OUTPUT CHARACTERISTICS
I and Q DAC Quadrature Phase Error 25°C IV 0.2 1 0.2 1 Degrees
DAC Wideband SFDR
1 MHz to 20 MHz AOUT 25°C V 58 58 dBc
20 MHz to 40 MHz AOUT 25°C V 56 56 dBc
40 MHz to 60 MHz AOUT 25°C V 52 52 dBc
60 MHz to 80 MHz AOUT 25°C V 48 48 dBc
80 MHz to 100 MHz AOUT 25°C V 48 48 dBc
100 MHz to 120 MHz AOUT 25°C V 48 48 dBc
DAC Narrow-Band SFDR
10 MHz AOUT (±1 MHz) 25°C V 83 83 dBc
10 MHz AOUT (±250 kHz) 25°C V 83 83 dBc
10 MHz AOUT (±50 kHz) 25°C V 91 91 dBc
41 MHz AOUT (±1 MHz) 25°C V 82 82 dBc
41 MHz AOUT (±250 kHz) 25°C V 84 84 dBc
41 MHz AOUT (±50 kHz) 25°C V 89 89 dBc
119 MHz AOUT (±1 MHz) 25°C V 71 71 dBc
119 MHz AOUT (±250 kHz) 25°C V 77 77 dBc
119 MHz AOUT (±50 kHz) 25°C V 83 83 dBc

Rev. E | Page 5 of 52
AD9854
Test AD9854ASVZ AD9854ASTZ
Parameter Temp Level Min Typ Max Min Typ Max Unit
Residual Phase Noise
(AOUT = 5 MHz, External Clock = 30 MHz
REFCLK Multiplier Engaged at 10×)
1 kHz Offset 25°C V 140 140 dBc/Hz
10 kHz Offset 25°C V 138 138 dBc/Hz
100 kHz Offset 25°C V 142 142 dBc/Hz
(AOUT = 5 MHz, External Clock = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset 25°C V 142 142 dBc/Hz
10 kHz Offset 25°C V 148 148 dBc/Hz
100 kHz Offset 25°C V 152 152 dBc/Hz
PIPELINE DELAYS 4, 5, 6
DDS Core (Phase Accumulator and 25°C IV 33 33 SYSCLK cycles
Phase-to-Amp Converter)
Frequency Accumulator 25°C IV 26 26 SYSCLK cycles
Inverse Sinc Filter 25°C IV 16 16 SYSCLK cycles
Digital Multiplier 25°C IV 9 9 SYSCLK cycles
DAC 25°C IV 1 1 SYSCLK cycles
I/O Update Clock (Internal Mode) 25°C IV 2 2 SYSCLK cycles
I/O Update Clock (External Mode) 25°C IV 3 3 SYSCLK cycles
MASTER RESET DURATION 25°C IV 10 10 SYSCLK cycles
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance 25°C V 3 3 pF
Input Resistance 25°C IV 500 500 kΩ
Input Current 25°C I ±1 ±5 ±1 ±5 μA
Hysteresis 25°C IV 10 20 10 20 mV p-p
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High-Z Load Full VI 3.1 3.1 V
Logic 0 Voltage, High-Z Load Full VI 0.16 0.16 V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm
Propagation Delay 25°C IV 3 3 ns
Output Duty Cycle Error 7 25°C I −10 ±1 +10 −10 ±1 +10 %
Rise/Fall Times, 5 pF Load 25°C V 2 2 ns
Toggle Rate, High-Z Load 25°C IV 300 350 300 350 MHz
Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz
Output Cycle-to-Cycle Jitter 8 IV 4.0 4.0 ps rms
COMPARATOR NARROW-BAND SFDR 9
10 MHz (±1 MHz) 25°C V 84 84 dBc
10 MHz (±250 MHz) 25°C V 84 84 dBc
10 MHz (±50 MHz) 25°C V 92 92 dBc
41 MHz (±1 MHz) 25°C V 76 76 dBc
41 MHz (±250 MHz) 25°C V 82 82 dBc
41 MHz (±50 MHz) 25°C V 89 89 dBc
119 MHz (±1 MHz) 25°C V 73 dBc
119 MHz (±250 MHz) 25°C V 73 dBc
119 MHz (±50 MHz) 25°C V 83 dBc
CLOCK GENERATOR OUTPUT JITTER9
5 MHz AOUT 25°C V 23 23 ps rms
40 MHz AOUT 25°C V 12 12 ps rms
100 MHz AOUT 25°C V 7 7 ps rms

Rev. E | Page 6 of 52
 AD9854
Test AD9854ASVZ AD9854ASTZ
Parameter Temp Level Min Typ Max Min Typ Max Unit
PARALLEL I/O TIMING CHARACTERISTICS
tASU (Address Setup Time to WR Signal Active) Full IV 8.0 7.5 8.0 7.5 ns
tADHW (Address Hold Time to WR Signal Inactive) Full IV 0 0 ns
tDSU (Data Setup Time to WR Signal Inactive) Full IV 3.0 1.6 3.0 1.6 ns
tDHD (Data Hold Time to WR Signal Inactive) Full IV 0 0 ns
tWRLOW (WR Signal Minimum Low Time) Full IV 2.5 1.8 2.5 1.8 ns
tWRHIGH (WR Signal Minimum High Time) Full IV 7 7 ns
tWR (Minimum WR Time) Full IV 10.5 10.5 ns
tADV (Address to Data Valid Time) Full V 15 15 15 15 ns
tADHR (Address Hold Time to RD Signal Inactive) Full IV 5 5 ns
tRDLOV (RD Low to Output Valid) Full IV 15 15 ns
tRDHOZ (RD High to Data Three-State) Full IV 10 10 ns
SERIAL I/O TIMING CHARACTERISTICS
tPRE (CS Setup Time) Full IV 30 30 ns
tSCLK (Period of Serial Data Clock) Full IV 100 100 ns
tDSU (Serial Data Setup Time) Full IV 30 30 ns
tSCLKPWH (Serial Data Clock Pulse Width High) Full IV 40 40 ns
tSCLKPWL (Serial Data Clock Pulse Width Low) Full IV 40 40 ns
tDHLD (Serial Data Hold Time) Full IV 0 0 ns
tDV (Data Valid Time) Full V 30 30 ns
CMOS LOGIC INPUTS 10
Logic 1 Voltage 25°C I 2.2 2.2 V
Logic 0 Voltage 25°C I 0.8 0.8 V
Logic 1 Current 25°C IV ±5 ±12 μA
Logic 0 Current 25°C IV ±5 ±12 μA
Input Capacitance 25°C V 3 3 pF
POWER SUPPLY 11, 15
VS Current11, 12, 15 25°C I 1050 1210 755 865 mA
VS Current11, 13, 15 25°C I 710 816 515 585 mA
VS Current 14 25°C I 600 685 435 495 mA
PDISS11, 12, 15 25°C I 3.475 4.190 2.490 3.000 W
PDISS11, 13, 15 25°C I 2.345 2.825 1.700 2.025 W
PDISS14 25°C I 1.975 2.375 1.435 1.715 W
PDISS Power-Down Mode 25°C I 1 50 1 50 mW
1
The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine wave centered at one-half the applied VDD or a 3 V TTL-level pulse input.
2
An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.
3
The I and Q gain imbalance is digitally adjustable to less than 0.01 dB.
4
Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are 0s, the delay appears longer. This is due to insufficient phase
accumulation per system clock period to produce enough LSB amplitude to the DAC.
5
If a feature such as the inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.
6
The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.
7
Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
8
Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075.
9
Comparator input originates from the analog output section via the external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output
terminated in 50 Ω.
10
Avoid overdriving digital inputs. (Refer to the equivalent circuits in Figure 3.)
11
If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum
internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal
Considerations section for derating and thermal management information.
12
All functions engaged.
13
All functions except inverse sinc engaged.
14
All functions except inverse sinc and digital multipliers engaged.
15
In most cases, disabling the inverse sinc filter reduces power consumption by approximately 30%.

Rev. E | Page 7 of 52
AD9854

ABSOLUTE MAXIMUM RATINGS

Table 2. To determine the junction temperature on the application PCB
use the following equation:
Parameter Rating
Maximum Junction Temperature 150°C TJ = Tcase + (ΨJT × PD)
VS 4V
Digital Inputs −0.7 V to +VS
where:
Digital Output Current 5 mA
TJ is the junction temperature expressed in degrees Celsius.
Storage Temperature Range −65°C to +150°C
Tcase is the case temperature expressed in degrees Celsius, as
measured by the user at the top center of the package.
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C ΨJT = 0.3°C/W.
Maximum Clock Frequency (ASVZ) 300 MHz PD is the power dissipation (PD); see the Power Dissipation and
Maximum Clock Frequency (ASTZ) 200 MHz Thermal Considerations section for the method to calculate PD.

EXPLANATION OF TEST LEVELS

Stresses above those listed under Absolute Maximum Ratings
Table 3.
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any Test Level Description
other conditions above those indicated in the operational I 100% production tested.
section of this specification is not implied. Exposure to absolute III Sample tested only.
maximum rating conditions for extended periods may affect IV Parameter is guaranteed by design and
characterization testing.
device reliability.
V Parameter is a typical value only.
THERMAL RESISTANCE VI Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
The heat sink of the AD9854ASVZ 80-lead TQFP package must for industrial operating temperature range.
be soldered to the PCB.

Table 3. ESD CAUTION

Thermal Characteristic TQFP LQFP
θJA (0 m/sec airflow)1, 2, 3 16.2°C/W 38°C/W
θJMA (1.0 m/sec airflow)2, 3, 4, 5 13.7°C/W
θJMA (2.5 m/sec airflow)2, 3, 4, 5 12.8°C/W
ΨJT1, 2 0.3°C/W
θJC6, 7 2.0°C/W
1
Per JEDEC JESD51-2 (heat sink soldered to PCB).
2
2S2P JEDEC test board.
3
Values of θJA are provided for package comparison and PCB design
considerations.
4
Per JEDEC JESD51-6 (heat sink soldered to PCB).
5
Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the
more metal that is directly in contact with the package leads from metal
traces through holes, ground, and power planes, the more θJA is reduced.
6
Per MIL-Std 883, Method 1012.1.
7
Values of θJC are provided for package comparison and PCB design
considerations when an external heat sink is required.

Rev. E | Page 8 of 52
 AD9854

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DIFF CLK ENABLE

MASTER RESET
S/P SELECT

PLL FILTER
REFCLK
REFCLK
DGND
DGND
DGND
DGND

DGND

AGND
AGND

AGND
DVDD
DVDD

DVDD
DVDD

AVDD

NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

D7 1 60 AVDD
PIN 1
D6 2 INDICATOR 59 AGND
D5 3 58 NC
D4 4 57 NC
D3 5 56 DAC R SET
D2 6 55 DACBP
D1 7 54 AVDD
D0 8 53 AGND
DVDD 9 52 IOUT2
DVDD 10 AD9854 51 IOUT2
TOP VIEW
DGND 11 50 AVDD
(Not to Scale)
DGND 12 49 IOUT1
NC 13 48 IOUT1
A5 14 47 AGND
A4 15 46 AGND
A3 16 45 AGND
A2/IO RESET 17 44 AVDD
A1/SDO 18 43 VINN
A0/SDIO 19 42 VINP
I/O UD CLK 20 41 AGND

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
WR/SCLK

FSK/BPSK/HOLD
OSK

VOUT
DGND
DGND
DGND

AVDD
AVDD
AGND
AGND
NC

AVDD
AVDD
AGND
AGND
DVDD
DVDD
DVDD
RD/CS

00636-002
NC = NO CONNECT

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 to 8 D7 to D0 8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
9, 10, 23, 24, 25, DVDD Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
73, 74, 79, 80 and DGND.
11, 12, 26, 27, 28, DGND Connections for the Digital Circuitry Ground Return. Same potential as AGND.
72, 75 to 78
13, 35, 57, 58, 63 NC No Internal Connection.
14 to 16 A5 to A3 Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0). Used only in parallel programming mode.
17 A2/IO RESET Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when
the serial programming mode is selected, allowing an IO RESET of the serial communication bus
that is unresponsive due to improper programming protocol. Resetting the serial bus in this
manner does not affect previous programming, nor does it invoke the default programming
values listed in Table 8. Active high.
18 A1/SDO Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming
mode. SDO is used in 3-wire serial communication mode when the serial programming mode is
selected.
19 A0/SDIO Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Bidirectional Serial Data I/O. A0 is used only in parallel programming mode. SDIO
is used in 2-wire serial communication mode.

Rev. E | Page 9 of 52
AD9854
Pin No. Mnemonic Description
20 I/O UD CLK Bidirectional I/O Update Clock. Direction is selected in control register. If this pin is selected as an
input, a rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O
UD CLK is selected as an output (default), an output pulse (low to high) with a duration of eight
system clock cycles indicates that an internal frequency update has occurred.
21 WR/SCLK Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated
with the serial programming bus. Data is registered on the rising edge. This pin is shared with WR
when the parallel mode is selected. The mode is dependent on Pin 70 (S/P SELECT).
22 RD/CS Read Parallel Data from Programming Registers. Shared function with CS. Chip-select signal
associated with the serial programming bus. Active low. This pin is shared with RD when the
parallel mode is selected.
29 FSK/BPSK/HOLD Multifunction pin according to the mode of operation selected in the programming control
register. In FSK mode, logic low selects F1 and logic high selects F2. In BPSK mode, logic low
selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high engages the hold
function, causing the frequency accumulator to halt at its current location. To resume or
commence chirp mode, logic low is asserted.
30 OSK Output Shaped Keying. Must first be selected in the programming control register to function. A
logic high causes the I and Q DAC outputs to ramp up from zero-scale to full-scale amplitude at a
preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at the
preprogrammed rate.
31, 32, 37, 38, 44, AVDD Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
50, 54, 60, 65 and DGND.
33, 34, 39, 40, 41, AGND Connections for Analog Circuitry Ground Return. Same potential as DGND.
45, 46, 47, 53, 59,
62, 66, 67
36 VOUT Noninverted Output of the Internal High Speed Comparator. Designed to drive 10 dBm to 50 Ω
load as well as standard CMOS logic levels.
42 VINP Voltage Input Positive. The noninverting input of the internal high speed comparator.
43 VINN Voltage Input Negative. The inverting input of the internal high speed comparator.
48 IOUT1 Unipolar Current Output of I, or the Cosine DAC. (Refer to Figure 3.)
49 IOUT1 Complementary Unipolar Current Output of I, or the Cosine DAC.
51 IOUT2 Complementary Unipolar Current Output of Q, or the Sine DAC.
52 IOUT2 Unipolar Current Output of Q, or the Sine DAC. This DAC can be programmed to accept external
12-bit data in lieu of internal sine data, allowing the AD9854 to emulate the AD9852 control DAC
function.
55 DACBP Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 μF chip capacitor from this
pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible, but
results in a slight degradation in SFDR.
56 DAC RSET Common Connection for Both I and Q DACs. Used to set the full-scale output current. RSET = 39.9/IOUT.
Normal RSET range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).
61 PLL FILTER Connection for the External Zero-Compensation Network of the REFCLK Multiplier’s PLL Loop
Filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF
capacitor. The other side of the network should be connected to AVDD as close as possible to
Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by setting
the bypass PLL bit in Control Register 1E hex.
64 DIFF CLK ENABLE Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and REFCLK (Pin 69 and Pin 68, respectively).
68 REFCLK Complementary (180° Out of Phase) Differential Clock Signal. User should tie this pin high or low
when single-ended clock mode is selected. Same signal levels as REFCLK.
69 REFCLK Single-Ended Reference Clock Input (CMOS Logic Levels Required) or One of Two Differential
Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have
greater than 400 mV p-p square or sine waves centered about 1.6 V dc.
70 S/P SELECT Selects serial programming mode (logic low) or parallel programming mode (logic high).
71 MASTER RESET Initializes the serial/parallel programming bus to prepare for user programming; sets
programming registers to a do-nothing state defined by the default values listed in Table 8.
Active on logic high. Asserting this pin is essential for proper operation upon power-up.

Rev. E | Page 10 of 52
 AD9854
DVDD

AVDD

AVDD AVDD DIGITAL

IN

IOUT IOUTB VINP/ AVOID OVERDRIVING

COMPARATOR VINN DIGITAL INPUTS. FORWARD
MUST TERMINATE OUTPUTS
FOR CURRENT FLOW. DO OUT BIASING ESD DIODES MAY
NOT EXCEED THE OUTPUT COUPLE DIGITAL NOISE
VOLTAGE COMPLIANCE RATING. ONTO POWER PINS.

00636-003
A. DAC OUTPUTS B. COMPARATOR OUTPUT C. COMPARATOR INPUT D. DIGITAL INPUTS

Figure 3. Equivalent Input and Output Circuits

Rev. E | Page 11 of 52
AD9854

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental
output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from 0 MHz to 150 MHz (Nyquist).
0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

00636-007
00636-004

–100 –100
START 0Hz 15MHz/ STOP 150MHz START 0Hz 15MHz/ STOP 150MHz

Figure 4. Wideband SFDR, 19.1 MHz Figure 7. Wideband SFDR, 79.1 MHz

0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90
00636-005

00636-008
–100 –100
START 0Hz 15MHz/ STOP 150MHz START 0Hz 15MHz/ STOP 150MHz
Figure 5. Wideband SFDR, 39.1 MHz Figure 8. Wideband SFDR, 99.1 MHz

0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90
00636-006

00636-009

–100 –100
START 0Hz 15MHz/ STOP 150MHz START 0Hz 15MHz/ STOP 150MHz
Figure 6. Wideband SFDR, 59.1 MHz Figure 9. Wideband SFDR, 119.1 MHz

Rev. E | Page 12 of 52
 AD9854
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal
REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of
Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of
sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth,
which effectively lowers the noise floor.
0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90

00636-012
00636-010

–100 –100
CENTER 39.1MHz 100kHz/ SPAN 1MHz CENTER 39.1MHz 100kHz/ SPAN 1MHz

Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW, Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed 30 MHz REFCLK with REFCLK Multiplier = 10×

0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90
00636-011

00636-013
–100 –100
CENTER 39.1MHz 5kHz/ SPAN 50kHz CENTER 39.1MHz 5kHz/ SPAN 50kHz

Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed 30 MHz REFCLK with REFCLK Multiplier = 10×

0 0

–10 –10

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

–70 –70

–80 –80

–90 –90
00636-015
00636-014

–100 –100
CENTER 39.1MHz 5kHz/ SPAN 50kHz CENTER 39.1MHz 5kHz/ SPAN 50kHz

Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
100 MHz REFCLK with REFCLK Multiplier Bypassed 10 MHz REFCLK with REFCLK Multiplier = 10×

Rev. E | Page 13 of 52
AD9854
Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the
REFCLK multiplier bypassed vs. a 20 MHz reference clock and the REFCLK multiplier enabled at 10×.
0 –90

–10
–100
–20
–110 AOUT = 80MHz
–30

PHASE NOISE (dBc/Hz)

–40 –120
–50
–130
–60

–70 –140

–80
–150
–90 AOUT = 5MHz

00636-016
–100 –160

00636-019
CENTER 39.1MHz 5kHz/ SPAN 50kHz 10 100 1k 10k 100k 1M
FREQUENCY (Hz)

Figure 16. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, Figure 19. Residual Phase Noise,
200 MHz REFCLK with REFCLK Multiplier Bypassed 30 MHz REFCLK with REFCLK Multiplier = 10×

0 55

–10
54
–20

–30 53

–40
SFDR (dBc)

52
–50
51
–60

–70 50
–80
49
–90
00636-017

–100 48

00636-020
CENTER 39.1MHz 5kHz/ SPAN 50kHz 0 5 10 15 20 25
DAC CURRENT (mA)

Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, Figure 20. SFDR vs. DAC Current, 59.1 AOUT,
20 MHz REFCLK with REFCLK Multiplier = 10× 300 MHz REFCLK with REFCLK Multiplier Bypassed

–100 620

–110
615

–120
SUPPLY CURRENT (mA)
PHASE NOISE (dBc/Hz)

610
AOUT = 80MHz
–130
605
–140

600
–150

–160 AOUT = 5MHz 595

–170 590
00636-021
00636-018

10 100 1k 10k 100k 1M 0 20 40 60 80 100 120 140

FREQUENCY (Hz) FREQUENCY (MHz)

Figure 18. Residual Phase Noise, Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal,
300 MHz REFCLK with REFCLK Multiplier Bypassed Expressed as a Percentage, and Heavily Dependent on Tuning Word)

Rev. E | Page 14 of 52
 AD9854
1200
MINIMUM COMPARATOR
INPUT DRIVE
VCM = 0.5V
1000

AMPLITUDE (mV p-p)

RISE TIME 800
1.04ns

JITTER 600
[10.6ps RMS]

400

200
–33ps 0ps +33ps

00636-022
0

00636-024
500ps/DIV 232mV/DIV 50Ω INPUT 0 100 200 300 400 500
FREQUENCY (MHz)

Figure 22. Typical Comparator Output Jitter, 40 MHz AOUT, Figure 24. Comparator Toggle Voltage Requirement
300 MHz RFCLK with REFCLK Multiplier Bypassed

REF1 RISE
1.174ns

C1 FALL
1.286ns
00636-023

CH1 500mVΩ M 500ps CH1 980mV

Figure 23. Comparator Rise/Fall Times

Rev. E | Page 15 of 52
AD9854

TYPICAL APPLICATIONS
LPF I BASEBAND

COS
LPF CHANNEL
RF/IF
INPUT AD9854 SELECT
REFCLK LPF FILTERS
SIN

00636-025
LPF Q BASEBAND

Figure 25. Quadrature Downconversion

I BASEBAND

COS
LPF
AD9854 RF OUTPUT
REFCLK LPF
SIN

00636-026
Q BASEBAND

Figure 26. Direct Conversion Quadrature Upconverter

I 8
I/Q MIXER
Rx DUAL DIGITAL Rx BASEBAND
AND
8-/10-BIT DEMODULATOR DIGITAL DATA
RF IN LOW-PASS Q 8
ADC OUT
FILTER
VCA AGC
ADC CLOCK FREQUENCY
LOCKED TO Tx CHIP/ ADC ENCODE
SYMBOL/PN RATE

AD9854
48
CLOCK
REFERENCE GENERATOR CHIP/SYMBOL/PN

00636-027
CLOCK RATE DATA

Figure 27. Chip Rate Generator in Spread Spectrum Application

BAND-PASS
FILTER AMPLIFIER

IOUT
AD9854
50Ω 50Ω

AD9854 FINAL OUTPUT

SPECTRUM SPECTRUM

FUNDAMENTAL
FC – FO FC + FO FC + FO
IMAGE IMAGE IMAGE

FCLK BAND-PASS
00636-028

FILTER

Figure 28. Using an Aliased Image to Generate a High Frequency

Rev. E | Page 16 of 52
 AD9854
REFERENCE
RF
CLOCK
FREQUENCY
OUT
PHASE LOOP
COMPARATOR VCO
FILTER

FILTER

REF CLK IN
AD9854
DAC OUT DDS
PROGRAMMABLE
DIVIDE-BY-N FUNCTION
(WHERE N = 248/TUNING WORD)

00636-029
TUNING
WORD

Figure 29. Programmable Fractional Divide-by-N Synthesizer

REF
CLOCK RF
FREQUENCY
AD9854 FILTER OUT
DDS PHASE LOOP
COMPARATOR VCO
FILTER

00636-030
TUNING
WORD DIVIDE-BY-N

Figure 30. Agile High Frequency Synthesizer

AD8346 QUADRATURE
36dB MODULATOR
TYPICAL
COSINE (DC TO 70MHz)
SSB
LO
REJECTION 50Ω
90
VOUT
PHASE 0.8 TO AD9854
Σ SPLITTER 2.5GHz QUADRATURE
DDS
0
LO
SINE (DC TO 70MHz)

DDS – LO LO DDS
+ LO
NOTES
1. FLIP DDS QUADRATURE SIGNALS TO SELECT ALTERNATE SIDEBAND. ADJUST DDS
00636-031

SINE OR COSINE SIGNAL AMPLITUDE FOR GREATEST SIDEBAND SUPPRESSION.

DDS DAC OUTPUTS MUST BE LOW-PASS FILTERED PRIOR TO USE WITH THE AD8346.

Figure 31. Single Sideband Upconversion

DIFFERENTIAL
TRANSFORMER-COUPLED
OUTPUT
REFERENCE IOUT
CLOCK FILTER
DDS 50Ω
AD9854 IOUT

50Ω
00636-032

1:1 TRANSFORMER
(Mini-Circuits® T1-1T)
Figure 32. Differential Output Connection for Reduction of Common-Mode Signals

Rev. E | Page 17 of 52
AD9854
COMPARATORS

AOUT = 100MHz
REFERENCE SIN
CLOCK LPF

AD9854
LPF CLOCK OUT = 200MHz

00636-033
COS

Figure 33. Clock Frequency Doubler

AD9854 LOW-PASS
FILTER
8-BIT PARALLEL OR I DAC NOTES
µPROCESSOR/
SERIAL PROGRAMMING 1 1. IOUT = APPROX 20mA MAX WHEN RSET = 2kΩ.
CONTROLLER DATA AND CONTROL LOW-PASS
FPGA, ETC. FILTER 2. SWITCH POSITION 1 PROVIDES COMPLEMENTARY
SIGNALS
Q DAC OR 2 SINUSOIDAL SIGNALS TO THE COMPARATOR
CONTROL TO PRODUCE A FIXED 50% DUTY CYCLE FROM THE
300MHz MAX DIRECT DAC COMPARATOR.
REFERENCE MODE OR 15MHz TO 75MHz 3. SWITCH POSITION 2 PROVIDES THE SAME DUTY CYCLE
MAX IN THE 4× TO 20× + USING QUADRATURE SINUSOIDAL SIGNALS TO THE
CLOCK
CLOCK COMPARATOR OR A DC THRESHOLD VOLTAGE TO
MULTIPLIER MODE ALLOW SETTING OF THE COMPARATOR DUTY CYCLE
2kΩ (DEPENDS ON THE CONFIGURATION OF THE Q DAC).
RSET

00636-034
CMOS LOGIC CLOCK OUT

Figure 34. Frequency Agile Clock Generator Applications for the AD9854

Rev. E | Page 18 of 52
 AD9854

THEORY OF OPERATION
The AD9854 quadrature output digital synthesizer is a highly In each mode, some functions may be prohibited. Table 6 lists
flexible device that addresses a wide range of applications. The the functions and their availability for each mode.
device consists of an NCO with a 48-bit phase accumulator, a
programmable reference clock multiplier, inverse sinc filters,
Single Tone (Mode 000)
digital multipliers, two 12-bit/300 MHz DACs, a high speed This is the default mode when the MASTER RESET pin is
analog comparator, and interface logic. This highly integrated asserted. It can also be accessed if the user programs this mode
device can be configured to serve as a synthesized LO, an agile into the control register. The phase accumulator, responsible for
clock generator, or an FSK/BPSK modulator. generating an output frequency, is presented with a 48-bit value
from the Frequency Tuning Word 1 registers that have default
Analog Devices, Inc., provides a technical tutorial about the values of 0. Default values from the remaining applicable
operational theory of the functional blocks of the device. The registers further define the single-tone output signal qualities.
tutorial includes a technical description of the signal flow
through a DDS device and provides basic applications The default values after a master reset configure the device
information for a variety of digital synthesis implementations. with an output signal of 0 Hz and zero phase. At power-up and
The document, A Technical Tutorial on Digital Signal Synthesis, reset, the output from the I and Q DACs is a dc value equal to
is available from the DDS Technical Library, on the Analog the midscale output current. This is the default mode amplitude
Devices DDS website at www.analog.com/dds. setting of 0. See the On/Off Output Shaped Keying (OSK)
section for more details about the output amplitude control. All
MODES OF OPERATION or some of the 28 program registers must be programmed to
The AD9854 has five programmable operational modes. To produce a user-defined output signal.
select a mode, three bits in the control register (parallel Address
Figure 35 shows the transition from the default condition
1F hex) must be programmed, as described in Table 5.
(0 Hz) to a user-defined output frequency (F1).
Table 5. Mode Selection Table
Mode 2 Mode 1 Mode 0 Result
0 0 0 Single tone
0 0 1 FSK
0 1 0 Ramped FSK
0 1 1 Chirp
1 0 0 BPSK

Table 6. Functions Available for Modes

Mode
Function Single Tone FSK Ramped FSK Chirp BPSK
Phase Adjust 1 ● ● ● ● ●
Phase Adjust 2 ●
Single-Pin FSK/BPSK or HOLD ● ● ● ●
Single-Pin Shaped Keying ● ● ● ● ●
Phase Offset or Modulation ● ● ● ●
Amplitude Control or Modulation ● ● ● ● ●
Inverse Sinc Filter ● ● ● ● ●
Frequency Tuning Word 1 ● ● ● ● ●
Frequency Tuning Word 2 ● ●
Automatic Frequency Sweep ● ●

Rev. E | Page 19 of 52
AD9854

FREQUENCY
F1

MODE 000 (DEFAULT) 000 (SINGLE TONE)

TW1 0 F1

MASTER RESET

00636-035
I/O UD CLK

Figure 35. Default State to User-Defined Output Transition

As with all Analog Devices DDS devices, the value of the a 10 MHz serial rate. Incorporating this attribute permits FM,
frequency tuning word is determined by AM, PM, FSK, PSK, and ASK operation in single-tone mode.

FTW = (Desired Output Frequency × 2N)/SYSCLK Unramped FSK (Mode 001)

When the unramped FSK mode is selected, the output frequency of
where:
the DDS is a function of the values loaded into Frequency Tuning
N is the phase accumulator resolution (48 bits in this instance).
Word Register 1 and Frequency Tuning Word Register 2 and the
Desired Output Frequency is expressed in hertz.
logic level of Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29
FTW (frequency tuning word) is a decimal number.
chooses F1 (Frequency Tuning Word 1, Parallel Address 4 hex to
After a decimal number has been calculated, it must be rounded Parallel Address 9 hex), and a logic high chooses F2 (Frequency
to an integer and then converted to binary format, that is, a Tuning Word 2, Parallel Register Address A hex to Parallel
series of 48 binary-weighted 1s and 0s. The fundamental sine Register Address F hex). Changes in frequency are phase
wave DAC output frequency range is from dc to one-half SYSCLK. continuous and are internally coincident with the FSK data pin
(Pin 29); however, there is deterministic pipeline delay between
Changes in frequency are phase continuous, meaning that the the FSK data signal and the DAC output. (Refer to the pipeline
first sampled phase value of the new frequency is referenced from delays in Table 1.)
the time of the last sampled phase value of the previous frequency.
The unramped FSK mode, shown in Figure 36, represents
The I and Q DACs of the AD9854 are always 90° out of phase. traditional FSK, radio teletype (RTTY), or teletype (TTY)
The 14-bit phase registers do not independently adjust the transmission of digital data. FSK is a very reliable means of
phase of each DAC output. Instead, both DACs are affected digital communication; however, it makes inefficient use of
equally by a change in phase offset. the bandwidth in the RF spectrum. Ramped FSK, shown in
Figure 37, is a method of conserving bandwidth.
The single-tone mode allows the user to control the following
signal qualities: Ramped FSK (Mode 010)
• Output frequency to 48-bit accuracy This mode is a method of FSK whereby changes from F1 to F2
• Output amplitude to 12-bit accuracy are not instantaneous, but are accomplished in a frequency sweep
• Fixed, user-defined amplitude control or ramped fashion (the ramped notation implies that the sweep
• Variable, programmable amplitude control is linear). Although linear sweeping, or frequency ramping, is
• Automatic, programmable, single-pin-controlled easily and automatically accomplished, it is only one of many
on/off output shaped keying schemes. Other frequency transition schemes can be
• Output phase to 14-bit accuracy implemented by changing the ramp rate and ramp step size on
the fly in a piecewise fashion.
These qualities can be changed or modulated via the 8-bit
parallel programming port at a 100 MHz parallel byte rate or at

Rev. E | Page 20 of 52
 AD9854

F2

FREQUENCY
F1

MODE 000 (DEFAULT) 001 (FSK NO RAMP)

TW1 0 F1

TW2 0 F2

I/O UD CLK

00636-036
FSK DATA (PIN 29)

Figure 36. Unramped (Traditional) FSK Mode

F2
FREQUENCY

F1

MODE 000 (DEFAULT) 010 (RAMPED FSK)

TW1 0 F1

TW2 0 F2

DFW REQUIRES A POSITIVE TWOS COMPLEMENT VALUE

RAMP RATE

I/O UD CLK

00636-037
FSK DATA (PIN 29)

Figure 37. Ramped FSK Mode (Start at F1)

F2
FREQUENCY

F1

MODE 000 (DEFAULT) 010 (RAMPED FSK)

TW1 0 F1

TW2 0 F2

I/O UD CLK
00636-038

FSK DATA

Figure 38. Ramped FSK Mode (Start at F2)

Rev. E | Page 21 of 52
AD9854
Frequency ramping, whether linear or nonlinear, necessitates The allowable range of N is from 1 to (220 − 1). The output of
that many intermediate frequencies between F1 and F2 are this counter clocks the 48-bit frequency accumulator shown in
output in addition to the primary F1 and F2 frequencies. Figure 39. The ramp rate clock determines the amount of time
Figure 37 and Figure 38 depict the frequency vs. time spent at each intermediate frequency between F1 and F2. The
characteristics of a linear ramped FSK signal. counter stops automatically when the destination frequency is
achieved. The dwell time spent at F1 and F2 is determined by
Note that in ramped FSK mode, the delta frequency word (DFW) the duration that the FSK input, Pin 29, is held high or low after
is required to be programmed as a positive twos complement the destination frequency has been reached.
value. Another requirement is that the lowest frequency (F1)
be programmed in the Frequency Tuning Word 1 register.

The purpose of ramped FSK is to provide better bandwidth PHASE

ADDER ACCUMULATOR
containment than traditional FSK by replacing the instantaneous
frequency changes with more gradual, user-defined frequency FREQUENCY
ACCUMULATOR
changes. The dwell time at F1 and F2 can be equal to or much
48-BIT DELTA INSTANTANEOUS
greater than the time spent at each intermediate frequency. The FREQUENCY
FSK (PIN 29) PHASE OUT
WORD (TWOS
user controls the dwell time at F1 and F2, the number of inter- COMPLEMENT)

mediate frequencies, and the time spent at each frequency. Unlike

unramped FSK, ramped FSK requires the lowest frequency to be FREQUENCY FREQUENCY
TUNING TUNING
loaded into F1 registers and the highest frequency to be loaded WORD 1 WORD 2
into F2 registers.

Several registers must be programmed to instruct the DDS on 20-BIT

SYSTEM

00636-039
RAMP RATE
CLOCK
the resolution of intermediate frequency steps (48 bits) and the CLOCK

time spent at each step (20 bits). Furthermore, the CLR ACC1 bit Figure 39. Block Diagram of Ramped FSK Function
in the control register should be toggled (low-high-low) prior to
operation to ensure that the frequency accumulator is starting Parallel Register Address 10 hex to Parallel Register Address 15 hex
from an all 0s output condition. For piecewise, nonlinear frequency comprise the 48-bit, twos complement, delta frequency word
transitions, it is necessary to reprogram the registers while the registers. This 48-bit word is accumulated (added to the
frequency transition is in progress to affect the desired response. accumulator’s output) every time it receives a clock pulse from
the ramp rate counter. The output of this accumulator is added to
Parallel Register Address 1A hex to Parallel Register Address 1C hex or subtracted from the F1 or F2 frequency word, which is then
comprise the 20-bit ramp rate clock registers. This is a countdown fed into the input of the 48-bit phase accumulator that forms
counter that outputs a single pulse whenever the count reaches the numerical phase steps for the sine and cosine wave outputs.
0. The counter is activated when a logic level change occurs on In this fashion, the output frequency is ramped up and down in
the FSK input, Pin 29. This counter is run at the system clock frequency according to the logic state of Pin 29. This ramping
rate, 300 MHz maximum. The time period between each output rate is a function of the 20-bit ramp rate clock. When the
pulse is given as destination frequency is achieved, the ramp rate clock is
(N + 1) × System Clock Period stopped, halting the frequency accumulation process.

where N is the 20-bit ramp rate clock value programmed by Generally speaking, the delta frequency word is a much smaller
the user. value compared with the value of the F1 or F2 tuning word. For
example, if F1 and F2 are 1 kHz apart at 13 MHz, the delta
frequency word might be only 25 Hz.

Rev. E | Page 22 of 52
 AD9854

F2

FREQUENCY
F1

MODE 010 (RAMPED FSK)

TW1 F1

TW2 F2

FSK DATA

TRIANGLE
BIT

00636-040
I/O UD CLK

Figure 40. Effect of Triangle Bit in Ramped FSK Mode

F2
FREQUENCY

F1

MODE 000 (DEFAULT) 010 (RAMPED FSK)

TW1 0 F1

TW2 0 F2

I/O UD CLK

FSK DATA 00636-041

Figure 41. Effect of Premature Ramped FSK Data

Figure 41 shows that premature toggling causes the ramp to to the logic level on Pin 29 (FSK input pin) when the triangle
immediately reverse itself and proceed at the same rate and bit’s rising edge occurs (Figure 42). If the FSK data bit is high
resolution until the original frequency is reached. instead of low, F2, rather than F1, is chosen as the start frequency.

The control register contains a triangle bit at Parallel Register Additional flexibility in the ramped FSK mode is provided by
Address 1F hex. Setting this bit high in Mode 010 causes an the AD9854’s ability to respond to changes in the 48-bit delta
automatic ramp-up and ramp-down between F1 and F2 to frequency word and/or the 20-bit ramp rate counter at any time
occur without toggling Pin 29, as shown in Figure 40. The logic during the ramping from F1 to F2 or vice versa. To create these
state of Pin 29 has no effect once the triangle bit is set high. This nonlinear frequency changes, it is necessary to combine several
function uses the ramp rate clock time period and the step size linear ramps with different slopes in a piecewise fashion. This is
of the delta frequency word to form a continuously sweeping done by programming and executing a linear ramp at a rate or
linear ramp from F1 to F2 and back to F1 with equal dwell slope and then altering the slope (by changing the ramp rate
times at every frequency. Use this function to automatically clock or delta frequency word, or both). Changes in slope can
sweep between any two frequencies from dc to Nyquist. be made as often as needed before the destination frequency has
been reached to form the desired nonlinear frequency sweep
In the ramped FSK mode with the triangle bit set high, an response. These piecewise changes can be precisely timed using
automatic frequency sweep begins at either F1 or F2, according
Rev. E | Page 23 of 52
AD9854
the 32-bit internal update clock (see the Internal and External Alternatively, the CLR ACC2 control bit (Register Address 1F
Update Clock section). hex) is available to clear both the frequency accumulator
Nonlinear ramped FSK has the appearance of the chirp function (ACC1) and the phase accumulator (ACC2). When this bit is
shown in Figure 43. The difference between a ramped FSK set high, the output of the phase accumulator results in 0 Hz
function and a chirp function is that FSK is limited to operation output from the DDS. As long as this bit is set high, the
between F1 and F2, whereas chirp operation has no F2 limit frequency and phase accumulators are cleared, resulting in 0 Hz
frequency. output. To return to previous DDS operation, CLR ACC2 must
be set to logic low.
Two additional control bits (CLR ACC1 and CLR ACC2) are
available in the ramped FSK mode that allow more options. If
Chirp (Mode 011)
CLR ACC1 (Register Address 1F hex) is set high, it clears the This mode is also known as pulsed FM. Most chirp systems use
48-bit frequency accumulator (ACC1) output with a retriggerable a linear FM sweep pattern, but the AD9854 can also support
one-shot pulse of one system clock duration. If the CLR ACC1 nonlinear patterns. In radar applications, use of chirp or pulsed
bit is left high, a one-shot pulse is delivered on the rising edge of FM allows operators to significantly reduce the output power
every update clock. The effect is to interrupt the current ramp, needed to achieve the result that a single-frequency radar
reset the frequency to the start point (F1 or F2), and then continue system would produce. Figure 43 shows a very low resolution
to ramp up (or down) at the previous rate. This occurs even when nonlinear chirp, demonstrating the different slopes that are created
a static F1 or F2 destination frequency has been achieved. by varying the time steps (ramp rate) and frequency steps (delta
frequency word).

F2
FREQUENCY

F1

MODE 000 (DEFAULT) 010 (RAMPED FSK)

TW1 0 F1

TW2 0 F2

FSK DATA
00636-042

TRIANGLE BIT

Figure 42. Automatic Linear Ramping Using the Triangle Bit

FREQUENCY

F1

MODE 000 (DEFAULT) 010 (RAMPED FSK)

TW1 0 F1

DFW

RAMP RATE
00636-043

I/O UD CLK

Figure 43. Example of a Nonlinear Chirp

Rev. E | Page 24 of 52
 AD9854
The AD9854 permits precise, internally generated linear, or Two control bits (CLR ACC1 and CLR ACC2) are available
externally programmed nonlinear, pulsed or continuous FM in the FM chirp mode that allow the return to the beginning
over the complete frequency range, duration, frequency frequency, FTW1, or to 0 Hz. When the CLR ACC1 bit
resolution, and sweep direction(s). All of these are user (Register Address 1F hex) is set high, the 48-bit frequency
programmable. Figure 44 shows a block diagram of the FM accumulator (ACC1) output is cleared with a retriggerable
chirp components. one-shot pulse of one system clock duration. The 48-bit delta
frequency word input to the accumulator is unaffected by the
CLR ACC1 bit. If the CLR ACC1 bit is held high, a one-shot
OUT pulse is delivered to the frequency accumulator (ACC1) on every
ADDER PHASE
ACCUMULATOR rising edge of the I/O update clock. The effect is to interrupt the
FREQUENCY current chirp, reset the frequency to that programmed into FTW1,
ACCUMULATOR CLR ACC2
and continue the chirp at the previously programmed rate and
48-BIT DELTA
FREQUENCY direction. Clearing the output of the frequency accumulator in
WORD (TWOS CLR ACC1
COMPLEMENT) the chirp mode is illustrated in Figure 45. Shown in the diagram
FREQUENCY is the I/O update clock, which is either user supplied or internally
TUNING
WORD 1 generated.
20-BIT
SYSTEM
00636-044
HOLD RAMP RATE Alternatively, the CLR ACC2 control bit (Register Address 1F hex)
CLOCK
CLOCK
is available to clear both the frequency accumulator (ACC1)
Figure 44. FM Chirp Components and the phase accumulator (ACC2). When this bit is set high,
Basic FM Chirp Programming Steps the output of the phase accumulator results in 0 Hz output from
the DDS. As long as this bit is set high, the frequency and phase
1. Program a start frequency into Frequency Tuning Word 1 accumulators are cleared, resulting in 0 Hz output. To return to
(FTW1) at Parallel Register Address 4 hex to Parallel Register the previous DDS operation, CLR ACC2 must be set to logic
Address 9 hex. low. This bit is useful in generating pulsed FM.
2. Program the frequency step resolution into the 48-bit,
twos complement delta frequency word (Parallel Register Figure 46 illustrates the effect of the CLR ACC2 bit on the DDS
Address 10 hex to Parallel Register Address 15 hex). output frequency. Note that reprogramming the registers while
3. Program the rate of change (time at each frequency) into the CLR ACC2 bit is high allows a new FTW1 frequency and
the 20-bit ramp rate clock (Parallel Register Address 1A hex slope to be loaded.
to Parallel Register Address 1C hex).
Another function that is available only in chirp mode is the
When programming is complete, an I/O update pulse at Pin 20 HOLD pin (Pin 29). This function stops the clock signal to the
engages the program commands. ramp rate counter, halting any further clocking pulses to
the frequency accumulator, ACC1. The effect is to halt the chirp
The necessity for a twos complement delta frequency word is to at the frequency existing just before the HOLD pin is pulled
define the direction in which the FM chirp moves. If the 48-bit high. When Pin 29 is returned low, the clock and chirp resumes.
delta frequency word is negative (MSB is high), the incremental During a hold condition, the user can change the programming
frequency changes are in a negative direction from FTW1. If the registers; however, the ramp rate counter must resume operation at
48-bit word is positive (MSB is low), the incremental frequency its previous rate until a count of 0 is obtained before a new ramp
changes are in a positive direction from FTW1. rate count can be loaded. Figure 47 shows the effect of the hold
function on the DDS output frequency.
It is important to note that FTW1 is only a starting point for FM
chirp. There is no built-in restraint requiring a return to FTW1.
Once the FM chirp begins, it is free to move (under program
control) within the Nyquist bandwidth (dc to one-half the system
clock). However, instant return to FTW1 can be easily achieved.

Rev. E | Page 25 of 52
AD9854

FREQUENCY
F1

MODE 000 (DEFAULT) 011 (CHIRP)

FTW1 0 F1

DFW DELTA FREQUENCY WORD

RAMP RATE RAMP RATE

I/O UD CLK

00636-045
CLR ACC1

Figure 45. Effect of CLR ACC1 in FM Chirp Mode

FREQUENCY

F1

MODE 000 (DEFAULT) 011 (CHIRP)

TW1 0

DPW

RAMP RATE

CLR ACC2
00636-046

I/O UD CLK

Figure 46. Effect of CLR ACC2 in Chirp Mode

Rev. E | Page 26 of 52
 AD9854

FREQUENCY
F1

MODE 000 (DEFAULT) 011 (CHIRP)

TW1 0 F1

DFW DELTA FREQUENCY WORD

RAMP RATE RAMP RATE

HOLD

00636-047
I/O UD CLK

Figure 47. Example of Hold Function

360
PHASE

MODE 000 (DEFAULT) 100 (BPSK)

FTW1 0 F1

PHASE ADJUST 1 270°

PHASE ADJUST 2 90°

BPSK DATA

00636-048

I/O UD CLK

Figure 48. BPSK Mode

The 32-bit automatic I/O update counter can be used to • Stop at the destination frequency by using the HOLD pin
construct complex chirp or ramped FSK sequences. Because or by loading all 0s into the delta frequency word registers
this internal counter is synchronized with the AD9854 system of the frequency accumulator (ACC1).
clock, precisely timed program changes are possible. For such • Use the HOLD pin function to stop the chirp, and then ramp
changes, the user need only reprogram the desired registers down the output amplitude by using the digital multiplier
before the automatic I/O update clock is generated. stages and the output shaped keying pin (Pin 30), or by using
the program register control (Address 21 to Address 24 hex).
In chirp mode, the destination frequency is not directly specified. • Abruptly end the transmission with the CLR ACC2 bit.
If the user fails to control the chirp, the DDS automatically confines • Continue chirp by reversing direction and returning to
itself to the frequency range between dc and Nyquist. Unless the previous or another destination frequency in a linear or
terminated by the user, the chirp continues until power is removed. user-directed manner. If this involves reducing the
When the chirp destination frequency is reached, the user can frequency, a negative 48-bit delta frequency word (the
choose any of the following actions: MSB is set to 1) must be loaded into Register 10 hex to
Register 15 hex. Any decreasing frequency step of the delta
frequency word requires the MSB to be set to logic high.
Rev. E | Page 27 of 52
AD9854
• Continue chirp by immediately returning to the beginning selection of Phase Adjust Register 1 or Phase Adjust Register 2.
frequency (F1) in a sawtooth fashion, and then repeating the When low, Pin 29 selects Phase Adjust Register 1; when high, it
previous chirp process using the CLR ACC1 control bit. selects Phase Adjust Register 2. Figure 48 illustrates phase
An automatic, repeating chirp can be set up by using the changes made to four cycles of an output carrier.
32-bit update clock to issue the CLR ACC1 command at
Basic BPSK Programming Steps
precise time intervals. Adjusting the timing intervals or
changing the delta frequency word changes the chirp 1. Program a carrier frequency into Frequency Tuning Word 1.
range. It is incumbent upon the user to balance the chirp 2. Program the appropriate 14-bit phase words into Phase
duration and frequency resolution to achieve the proper Adjust Register 1 and Phase Adjust Register 2.
frequency range. 3. Attach the BPSK data source to Pin 29.
4. Activate the I/O update clock when ready.
BPSK (Mode 100)
Binary, biphase, or bipolar phase shift keying is a means to Note that for higher-order PSK modulation, the user can select
rapidly select between two preprogrammed 14-bit output phase the single-tone mode and program Phase Adjust Register 1
offsets that equally affect both the I and Q outputs of the using the serial or high speed parallel programming bus.
AD9854. The logic state of Pin 29, the BPSK pin, controls the

Rev. E | Page 28 of 52
 AD9854

USING THE AD9854

INTERNAL AND EXTERNAL UPDATE CLOCK ON/OFF OUTPUT SHAPED KEYING (OSK)
This update clock function is comprised of a bidirectional The on/off OSK feature allows the user to control the amplitude vs.
I/O pin (Pin 20) and a programmable 32-bit down-counter. To time slope of the I and Q DAC output signals. This function is
program changes that are to be transferred from the I/O buffer used in burst transmissions of digital data to reduce the adverse
registers to the active core of the DDS, a clock signal (low-to- spectral impact of short, abrupt bursts of data. Users must first
high edge) must be externally supplied to Pin 20 or internally enable the digital multipliers by setting the OSK EN bit (Control
generated by the 32-bit update clock. Register Address 20 hex) to logic high in the control register.
Otherwise, if the OSK EN bit is set low, the digital multipliers
When the user provides an external update clock, it is internally responsible for amplitude control are bypassed and the I and
synchronized with the system clock to prevent a partial transfer Q DAC outputs are set to full-scale amplitude.
of program register information due to a violation of data setup
or hold time. This mode allows the user to completely control when In addition to setting the OSK EN bit, a second control bit, OSK
updated program information becomes effective. The default INT (also at Address 20 hex), must be set to logic high. Logic high
mode for the update clock is internal (the internal update clock selects the linear internal control of the output ramp-up or ramp-
control register bit is logic high). To switch to external update down function. A logic low in the OSK INT bit switches control
clock mode, the internal update clock control register bit must of the digital multipliers to user-programmable 12-bit registers,
be set to logic low. The internal update mode generates automatic, allowing users to dynamically shape the amplitude transition in
periodic update pulses at intervals set by the user. practically any fashion. These 12-bit registers, labeled Output
Shape Key I and Output Shape Key Q, are located at Address 21 hex
An internally generated update clock can be established by through Address 24 hex, as listed in Table 8. The maximum output
programming the 32-bit update clock registers (Address 16 hex amplitude is a function of the RSET resistor and is not programmable
to Address 19 hex) and setting the internal update clock control when OSK INT is enabled.
register bit (Address 1F hex) to logic high. The update clock
ABRUPT ON/OFF KEYING
down-counter function operates at half the rate of the system
clock (150 MHz maximum) and counts down from a 32-bit ZERO FULL
binary value (programmed by the user). When the count SCALE SCALE

reaches 0, an automatic I/O update of the DDS output or

functions is generated. The update clock is internally and
externally routed to Pin 20 to allow users to synchronize the ZERO FULL
SCALE SCALE
programming of update information with the update clock rate.

00636-049
The time between update pulses is given as
SHAPED ON/OFF KEYING
(N + 1)(System Clock Period × 2) Figure 49. On/Off Output Shaped Keying

where N is the 32-bit value programmed by the user, and the The transition time from zero scale to full scale must also be
allowable range of N is from 1 to (232 − 1). programmed. The transition time is a function of two fixed
elements and one variable. The variable element is the program-
The internally generated update pulse that is output from Pin 20
mable 8-bit ramp rate counter. This is a down-counter that is
has a fixed high time of eight system clock cycles.
clocked at the system clock rate (300 MHz maximum) and that
Programming the update clock register to a value less than five generates one pulse whenever the counter reaches 0. This pulse
causes the I/O UD CLK pin to remain high. Although the update is routed to a 12-bit counter that increments with each pulse
clock can function in this state, it cannot be used to indicate when received. The outputs of the 12-bit counter are connected to the
data is transferring. This is an effect of the minimum high pulse 12-bit digital multiplier. When the digital multiplier has a value
time when I/O UD CLK functions as an output. of all 0s at its inputs, the input signal is multiplied by 0, producing
zero scale. When the multiplier has a value of all 1s, the input
signal is multiplied by a value of 4095 or 4096, producing nearly
full scale. There are 4094 remaining fractional multiplier values that
produce output amplitudes scaled according to their binary values.

Rev. E | Page 29 of 52
AD9854
(BYPASS MULTIPLIER)
DIGITAL OSK EN = 0 OSK EN = 0
DDS DIGITAL SIGNAL IN 12 12-BIT DIGITAL 12
OUTPUT MULTIPLIER SINE DAC
OSK EN = 1 OSK EN = 1

12
USER-PROGRAMMABLE
12-BIT Q CHANNEL OSK INT = 0
MULTIPLIER 12
OUTPUT SHAPED
KEYING Q MULTIPLIER OSK INT = 0 12
REGISTER
12-BIT 1 8-BIT RAMP
SYSTEM
UP/DOWN RATE
CLOCK
COUNTER COUNTER

00636-050
ON/OFF OUTPUT SHAPED
KEYING PIN

Figure 50. Block Diagram of Q DAC Pathway of the Digital Multiplier Section Responsible for the Output Shaped Keying Function

The two fixed elements of the transition time are the period of of RSET is 39.93/IOUT, where IOUT is expressed in amps. DAC output
the system clock (which drives the ramp rate counter) and the compliance specifications limit the maximum voltage developed
number of amplitude steps (4096). For example, if the system at the outputs to −0.5 V to +1 V. Voltages developed beyond this
clock of the AD9854 is 100 MHz (10 ns period) and the ramp limitation cause excessive DAC distortion and possibly permanent
rate counter is programmed for a minimum count of 3, the damage. The user must choose a proper load impedance to limit
transition takes two system clock periods (one rising edge loads the output voltage swing to the compliance limits. Both DAC
the countdown value, and the next edge decrements the counter outputs should be terminated equally for best SFDR, especially
from 3 to 2). If the countdown value is less than 3, the ramp rate at higher output frequencies, where harmonic distortion errors
counter stalls and therefore produces a constant scaling value to are more prominent.
the digital multipliers. This stall condition may have an application Both DACs are preceded by inverse sin(x)/x filters (also called
for the user. inverse sinc filters) that precompensate for DAC output amplitude
The relationship of the 8-bit countdown value to the time variations over frequency to achieve flat amplitude response from
between output pulses is given as dc to Nyquist. Both DACs can be powered down when not needed
by setting the DAC PD bit high (Address 1D hex of the control
(N + 1) × System Clock Period register). I DAC outputs are designated as IOUT1 and IOUT1,
where N is the 8-bit countdown value. Pin 48 and Pin 49, respectively. Q DAC outputs are designated
as IOUT2 and IOUT2, Pin 52 and Pin 51, respectively.
It takes 4096 of these pulses to advance the 12-bit up-counter
from zero scale to full scale. Therefore, the minimum output CONTROL DAC
shaped keying ramp time for a 100 MHz system clock is The 12-bit Q DAC can be reconfigured to perform as a control
4096 × 4 × 10 ns ≈ 164 μs or auxiliary DAC. The control DAC output can provide dc
control levels to external circuitry, generate ac signals, or enable
The maximum ramp time is duty cycle control of the on-board comparator. When the SRC
4096 × 256 × 10 ns ≈ 10.5 ms Q DAC bit in the control register (Parallel Address 1F hex) is
set high, the Q DAC inputs are switched from internal 12-bit
Finally, changing the logic state of Pin 30, output shaped keying Q data source (default setting) to external 12-bit, twos complement
automatically performs the programmed output envelope functions data supplied by the user. Data is channeled through the serial
when OSK INT is high. A logic high on Pin 30 causes the outputs or parallel interface to the 12-bit Q DAC register (Address 26 hex
to linearly ramp up to full-scale amplitude and to hold until the and Address 27 hex) at a maximum data rate of 100 MHz. This
logic level is changed to low, causing the outputs to ramp down DAC is clocked at the system clock, 300 MSPS (maximum), and
to zero scale. has the same maximum output current capability as that of the I
DAC. The single RSET resistor on the AD9854 sets the full-scale
I AND Q DACS
output current for both DACs. When not needed, the control
The sine and cosine outputs of the DDS drive the Q and I DACs, DAC can be separately powered down to conserve power by
respectively (300 MSPS maximum). The maximum amplitudes setting the Q DAC power-down bit high (Address 1D hex).
of these output are set by the DAC RSET resistor at Pin 56. These Control DAC outputs are designated as IOUT2 and IOUT2,
are current-output DACs with a full-scale maximum output of Pin 52 and Pin 51, respectively.
20 mA; however, a nominal 10 mA output current provides the
best spurious-free dynamic range (SFDR) performance. The value
Rev. E | Page 30 of 52
 AD9854
INVERSE SINC FUNCTION should be set to Logic 0. The PLL range bit adjusts the PLL loop
The inverse sinc function precompensates input data to both parameters for best phase noise performance within each range.
DACs for the sin(x)/x roll-off characteristic inherent in the PLL Filter
DAC’s output spectrum. This allows wide bandwidth signals
The PLL FILTER pin (Pin 61) provides the connection for the
(such as QPSK) to be output from the DACs without
external zero-compensation network of the PLL loop filter. The
appreciable amplitude variations as a function of frequency. The
zero-compensation network consists of a 1.3 kΩ resistor in
inverse sinc function can be bypassed to reduce power
series with a 0.01 μF capacitor. The other side of the network
consumption significantly, especially at higher clock speeds.
should be connected as close as possible to Pin 60, AVDD. For
When the Q DAC is configured as a control DAC, the inverse
optimum phase noise performance, the clock multiplier can be
sinc function does not apply to the Q path.
bypassed by setting the bypass PLL bit in Control Register
Inverse sinc is engaged by default and is bypassed by bringing Address 1E hex.
the bypass inverse sinc bit high in Control Register 20 hex, as
Differential REFCLK Enable
noted in Table 8.
A high level on the DIFF CLK ENABLE pin enables the differ-
4.0
3.5
ential clock inputs, REFCLK and REFCLK (Pin 69 and Pin 68,
3.0 respectively). The minimum differential signal amplitude required
2.5
is 400 mV p-p at the REFCLK input pins. The center point or
2.0 ISF
1.5 common-mode range of the differential signal can range from
MAGNITUDE (dB)

1.0 1.6 V to 1.9 V.

0.5 SYSTEM
0
When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK
–0.5
–1.0 (Pin 69) is the only active clock input. This is referred to as
–1.5 single-ended mode. In this mode, Pin 68 (REFCLK) should
–2.0 SINC
–2.5
be tied low or high.
–3.0
–3.5 High Speed Comparator
–4.0
00636-051

0 0.1 0.2 0.3 0.4 0.5 The comparator is optimized for high speed and has a toggle rate
FREQUENCY NORMALIZED TO SAMPLE RATE greater than 300 MHz, low jitter, sensitive input, and built-in
Figure 51. Inverse Sinc Filter Response hysteresis. It also has an output level of 1 V p-p minimum into 50 Ω
or CMOS logic levels into high impedance loads. The comparator
REFCLK MULTIPLIER
can be powered down separately to conserve power. This com-
The REFCLK multiplier is a programmable PLL-based parator is used in clock-generator applications to square up the
reference clock multiplier that allows the user to select an filtered sine wave generated by the DDS.
integer clock multiplying value over the range of 4× to 20×.
With this function, users can input as little as 15 MHz at the Power-Down
REFCLK input to produce a 300 MHz internal system clock. The programming registers allow several individual stages to be
Five bits in Control Register 1E hex set the multiplier value, as powered down to reduce power consumption while maintaining
detailed in Table 7. the functionality of the desired stages. These stages are identified
in Table 8, Address 1D hex. Power-down is achieved by setting
The REFCLK multiplier function can be bypassed to allow
the specified bits to logic high. A logic low indicates that the
direct clocking of the AD9854 from an external clock source.
stages are powered up.
The system clock for the AD9854 is either the output of the
REFCLK multiplier (if it is engaged) or the REFCLK inputs. Furthermore, and perhaps most significantly, the inverse sinc
REFCLK can be either a single-ended or differential input by filters and the digital multiplier stages can be bypassed to achieve
setting Pin 64, DIFF CLK ENABLE, low or high, respectively. significant power reduction by programming the control registers
in Address 20 hex. Again, logic high causes the stage to be bypassed.
PLL Range Bit
Of particular importance is the inverse sinc filter; this stage
The PLL range bit selects the frequency range of the REFCLK consumes a significant amount of power.
multiplier PLL. For operation from 200 MHz to 300 MHz
(internal system clock rate), the PLL range bit should be set to A full power-down occurs when all four PD bits in Control
Logic 1. For operation below 200 MHz, the PLL range bit Register 1D hex are set to logic high. This reduces power
consumption to approximately 10 mW (3 mA).

Rev. E | Page 31 of 52
AD9854

PROGRAMMING THE AD9854

The AD9854 register layout table (Table 8) contains information Table 7. REFCLK Multiplier Control Register Values
for programming the chip for the desired functionality. Although Reference Multiplier
many applications require very little programming to configure
Multiplier Value Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
the AD9854, some use all 12 accessible register banks. The
4 0 0 1 0 0
AD9854 supports an 8-bit parallel I/O operation or an SPI®-
5 0 0 1 0 1
compatible serial I/O operation. All accessible registers can be
6 0 0 1 1 0
written and read back in either I/O operating mode.
7 0 0 1 1 1
S/P SELECT (Pin 70) is used to configure the I/O mode. 8 0 1 0 0 0
Systems that use the parallel I/O mode must connect the S/P 9 0 1 0 0 1
SELECT pin to VDD. Systems that operate in the serial I/O mode 10 0 1 0 1 0
must tie the S/P SELECT pin to GND. 11 0 1 0 1 1
12 0 1 1 0 0
Regardless of the mode, the I/O port data is written to a buffer 13 0 1 1 0 1
memory and only affects operation of the part after the contents 14 0 1 1 1 0
of the buffer memory are transferred to the register banks. This 15 0 1 1 1 1
transfer of information occurs synchronously to the system 16 1 0 0 0 0
clock in one of two ways: 17 1 0 0 0 1
18 1 0 0 1 0
• Internally, at a rate programmable by the user.
19 1 0 0 1 1
• Externally, by the user. I/O operations can occur in the
20 1 0 1 0 0
absence of REFCLK, but the data cannot be moved from
the buffer memory to the register bank without REFCLK.
(See the Internal and External Update Clock section for
more details.)

MASTER RESET
The MASTER RESET pin must be held at logic high active
for a minimum of 10 system clock cycles. This initializes the
communications bus and loads the default values listed in the
Table 8 section.

Rev. E | Page 32 of 52
 AD9854

Table 8. Register Layout 1

Parallel Serial AD9854 Register Layout Default
Address Address Value
(Hex) (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex)
00 0 Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care) Phase 1 00
01 Phase Adjust Register 1 <7:0> 00
02 1 Phase Adjust Register 2 <13:8> (Bits 15, 14, don’t care) Phase 2 00
03 Phase Adjust Register 2 <7:0> 00
04 2 Frequency Tuning Word 1 <47:40> Freq 1 00
05 Frequency Tuning Word 1 <39:32> 00
06 Frequency Tuning Word 1 <31:24> 00
07 Frequency Tuning Word 1 <23:16> 00
08 Frequency Tuning Word 1 <15:8> 00
09 Frequency Tuning Word 1 <7:0> 00
0A 3 Frequency Tuning Word 2 <47:40>
0B Frequency Tuning Word 2 <39:32> 00
0C Frequency Tuning Word 2 <31:24> 00
0D Frequency Tuning Word 2 <23:16> 00
0E Frequency Tuning Word 2 <15:8> 00
0F Frequency Tuning Word 2 <7:0> 00
10 4 Delta frequency word <47:40> 00
11 Delta frequency word <39:32> 00
12 Delta frequency word <31:24> 00
13 Delta frequency word <23:16> 00
14 Delta frequency word <15:8> 00
15 Delta frequency word <7:0> 00
16 5 Update clock <31:24> 00
17 Update clock <23:16> 00
18 Update clock <15:8> 00
19 Update clock <7:0> 40
1A 6 Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care) 00
1B Ramp rate clock <15:8> 00
1C Ramp rate clock <7:0> 00
1D 7 Don’t Don’t Don’t Comp Reserved, QDAC PD DAC PD DIG PD 10
care care care PD always low
CR [31]
1E Don’t PLL Bypass Ref Ref Mult 3 Ref Mult 2 Ref Ref Mult 0 64
care range PLL Mult 4 Mult 1
1F CLR CLR Triangle SRC Mode 2 Mode 1 Mode 0 Internal/external 01
ACC 1 ACC 2 QDAC update clock
20 Don’t Bypass OSK EN OSK Don’t care Don’t care LSB first SDO active CR [0] 20
care inv sinc INT
21 8 Output shaped keying I multiplier <11:8> (Bits 15, 14, 13, 12 don’t care) 00
22 Output shaped keying I multiplier <7:0> 00
23 9 Output shaped keying Q multiplier <11:8> (Bits 15, 14, 13, 12 don’t care) 00
24 Output shaped keying Q multiplier <7:0> 00
25 A Output shaped keying ramp rate <7:0> 80
26 B QDAC <11:8> (Bits 15, 14, 13, 12 don’t care) 00
27 QDAC <7:0> (data is required to be in twos complement format)
1
The shaded sections comprise the control register.

Rev. E | Page 33 of 52
AD9854
PARALLEL I/O OPERATION interface allows read/write access to all 12 registers that configure
the AD9854 and can be configured as a single-pin I/O (SDIO) or
With the S/P SELECT pin tied high, the parallel I/O mode is active. two unidirectional pins for input and output (SDIO/SDO). Data
The I/O port is compatible with industry-standard DSPs and transfers are supported in MSB-or the LSB-first format for up
microcontrollers. Six address bits, eight bidirectional data bits, to 10 MHz.
and separate write/read control inputs comprise the I/O port pins.
When configured for serial I/O operation, most AD9854 parallel
Parallel I/O operation allows write access to each byte of any port pins are inactive; only some pins are used for the serial I/O
register in a single I/O operation of up to one per 10.5 ns. operation. Table 9 describes pin requirements for serial I/O
Readback capability for each register is included to ease designing operation.
with the AD9854. (Reads are not guaranteed at 100 MHz because
they are intended for software debugging only.) Note that when operating the device in serial I/O mode, it
is best to use the external I/O update clock mode to avoid an
Parallel I/O operation timing diagrams are shown in Figure 52 update occurring during a serial communication cycle. Such an
and Figure 53. occurrence may cause incorrect programming due to a partial
SERIAL PORT I/O OPERATION data transfer. To exit the default internal update mode, program
the device for external update operation at power-up before
With the S/P SELECT pin tied low, the serial I/O mode is active.
starting the REFCLK signal but after a master reset. Starting the
The serial port is a flexible, synchronous, serial communication
REFCLK causes this information to transfer to the register bank,
port, allowing easy interface to many industry-standard micro-
forcing the device to switch to external update mode.
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola® 6905/11 SPI and Intel® 8051 SSR protocols. The

Table 9. Serial I/O Pin Requirements

Pin Number Mnemonic Serial I/O Description
1 to 8 D [7:0] The parallel data pins are not active; tie to VDD or GND.
14 to 16 A [5:3] The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.
17 A2/IO RESET IO RESET.
18 A1/SDO SDO.
19 A0/SDIO SDIO.
20 I/O UD CLK Update Clock. Same functionality for serial mode as parallel mode.
21 WR/SCLK SCLK.
22 RD/CS CS—Chip Select.

Rev. E | Page 34 of 52
 AD9854

A<5:0> A1 A2 A3

D<7:0> D1 D2 D3

RD

t RDHOZ t RDLOV

t AHD t ADV

SPECIFICATION VALUE DESCRIPTION

t ADV 15ns ADDRESS TO DATA VALID TIME (MAXIMUM)
t AHD 5ns ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)

00636-052
t RDLOV 15ns RD LOW TO OUTPUT VALID (MAXIMUM)
t RDHOZ 10ns RD HIGH TO DATA THREE-STATE (MAXIMUM)

Figure 52. Parallel Port Read Timing Diagram

t WR

A<5:0> A1 A2 A3

D<7:0> D1 D2 D3

WR
t ASU t AHD
t DSU
t WRHIGH t WRLOW t DHD

SPECIFICATION VALUE DESCRIPTION

t ASU 8.0ns ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
t DSU 3.0ns DATA SETUP TIME TO WR SIGNAL ACTIVE
t ADH 0ns ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
t DHD 0ns DATA HOLD TIME TO WR SIGNAL INACTIVE
t WRLOW 2.5ns WR SIGNAL MINIMUM LOW TIME

00636-053
t WRHIGH 7ns WR SIGNAL MINIMUM HIGH TIME
t WR 10.5ns MINIMUM WRITE TIME

Figure 53. Parallel Port Write Timing Diagram

Rev. E | Page 35 of 52
AD9854

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases of a serial communication cycle with the transferred.) The AD9854 internal serial I/O controller expects
AD9854. Phase 1 is the instruction cycle, which is the writing of every byte of the register being accessed to be transferred.
an instruction byte into the AD9854 coincident with the first Therefore, the user should write between I/O update clocks.
eight SCLK rising edges. The instruction byte provides the
AD9854 serial port controller with information regarding the At the completion of a communication cycle, the AD9854 serial
data transfer cycle, which is Phase 2 of the communication port controller expects the subsequent eight rising SCLK edges
cycle. The Phase 1 instruction byte defines whether the to be the instruction byte of the next communication cycle. In
upcoming data transfer is a read or write and the register addition, an active high input on the IO RESET pin immediately
address to be acted upon. terminates the current communication cycle. After IO RESET
returns low, the AD9854 serial port controller requires the
The first eight SCLK rising edges of each communication cycle subsequent eight rising SCLK edges to be the instruction byte
are used to write the instruction byte into the AD9854. The of the next communication cycle.
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9854 All data input to the AD9854 is registered on the rising edge of
and the system controller. The number of data bytes transferred SCLK, and all data is driven out of the AD9854 on the falling
in Phase 2 of the communication cycle is a function of the edge of SCLK.
register address. (Table 10 describes how many bytes must be Figure 54 and Figure 55 show the general operation of the
AD9854 serial port.

Table 10. Register Address vs. Data Bytes Transferred

Serial Register Address Register Name Number of Bytes Transferred
0 Phase Offset Tuning Word Register 1 2
1 Phase Offset Tuning Word Register 2 2
2 Frequency Tuning Word 1 6
3 Frequency Tuning Word 2 6
4 Delta frequency register 6
5 Update clock rate register 4
6 Ramp rate clock register 3
7 Control register 4
8 I path digital multiplier register 2
9 Q path digital multiplier register 2
A Shaped on/off keying ramp rate register 1
B Q DAC register 2

CS
INSTRUCTION
BYTE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDIO
00636-054

INSTRUCTION DATA TRANSFER

CYCLE

Figure 54. Using SDIO as a Read/Write Transfer

CS
INSTRUCTION
BYTE
SDIO

INSTRUCTION DATA TRANSFER

CYCLE
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
SDO
00636-055

DATA TRANSFER

Figure 55. Using SDIO as an Input and SDO as an Output

Rev. E | Page 36 of 52
 AD9854
INSTRUCTION BYTE NOTES ON SERIAL PORT OPERATION
The instruction byte contains the following information: The AD9854 serial port configuration bits reside in Bit 1 and
MSB LSB Bit 0 of Register Address 20 hex. It is important to note that the
D7 D6 D5 D4 D3 D2 D1 D0 configuration changes immediately upon a valid I/O update.
R/W X X X A3 A2 A1 A0 For multibyte transfers, writing to this register can occur during
the middle of a communication cycle. The user must compensate
for this new configuration for the remainder of the current com-
R/W—Bit 7 determines whether a read or write data transfer munication cycle.
occurs following the instruction byte. Logic high indicates read
operation. Logic 0 indicates a write operation. The system must maintain synchronization with the AD9854;
otherwise, the internal control logic is not able to recognize further
Bit 6, Bit 5, and Bit 4 are dummy bits (don’t care). instructions. For example, if the system sends the instruction to
write a 2-byte register and then pulses the SCLK pin for a 3-byte
A3, A2, A1, A0—Bit 3, Bit 2, Bit 1, and Bit 0 determine which
register (24 additional SCLK rising edges), communication
register is accessed during the data transfer portion of the
synchronization is lost. In this case, the first 16 SCLK rising
communication cycle (see Table 8 for register address details).
edges after the instruction cycle properly write the first two data
SERIAL INTERFACE PORT PIN DESCRIPTIONS bytes into the AD9854, but the subsequent eight rising SCLK
SCLK edges are interpreted as the next instruction byte, not the final
byte of the previous communication cycle.
Serial Clock (Pin 21). The serial clock pin is used to synchronize
data to and from the AD9854 and to run the internal state In the case where synchronization is lost between the system
machines. The SCLK maximum frequency is 10 MHz. and the AD9854, the IO RESET pin provides a means to re-
establish synchronization without reinitializing the entire chip.
CS Asserting the IO RESET pin (active high) resets the AD9854 serial
port state machine, terminating the current I/O operation and
Chip Select (Pin 22). Active low input that allows more than
forcing the device into a state in which the next eight SCLK rising
one device on the same serial communication line. The SDO
edges are understood to be an instruction byte. The IO RESET pin
and SDIO pins go to a high impedance state when this input is
must be deasserted (low) before the next instruction byte write
high. If this pin is driven high during a communication cycle,
can begin. Any information written to the AD9854 registers
the cycle is suspended until CS is reactivated low. The chip select
during a valid communication cycle prior to loss of synchroni-
pin can be tied low in systems that maintain control of SCLK. zation remains intact.
SDIO t PRE
t SCLK
CS
Serial Data I/O (Pin 19). Data is always written to the AD9854 t SCLKPWH t SCLKPWL
t DSU
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 0 of SCLK

Register Address 20 hex. The default is Logic 0, which t DHLD

configures the SDIO pin as bidirectional.
SDIO FIRST BIT SECOND BIT

SDO SYMBOL MIN DEFINITION

t PRE 30ns CS SETUP TIME
Serial Data Out (Pin 18). Data is read from this pin for protocols t SCLK 100ns PERIOD OF SERIAL DATA CLOCK
t DSU 30ns SERIAL DATA SETUP TIME
that use separate lines for transmitting and receiving data. In t SCLKPWH 40ns SERIAL DATA CLOCK PULSE WIDTH HIGH
00636-056

the case where the AD9854 operates in a single bidirectional t SCLKPWL 40ns SERIAL DATA CLOCK PULSE WIDTH LOW
t DHLD 0ns SERIAL DATA HOLD TIME
I/O mode, this pin does not output data and is set to a high
Figure 56. Timing Diagram for Data Write to AD9854
impedance state.

IO RESET CS
INSTRUCTION
Synchronize I/O Port (Pin 17). Synchronizes the I/O port state BYTE

machines without affecting the contents of the addressable SDIO

registers. An active high input on the IO RESET pin causes the INSTRUCTION DATA TRANSFER
CYCLE
DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
current communication cycle to terminate. After the IO RESET
SDO
00636-057

pin returns low (Logic 0), another communication cycle can begin,
DATA TRANSFER
starting with the instruction byte.
Figure 57. Timing Diagram for Read from AD9854

Rev. E | Page 37 of 52
AD9854

MSB/LSB TRANSFERS
The AD9854 serial port can support MSB- and LSB-first data CR [22] is the PLL range bit, which controls the VCO gain. The
formats. This functionality is controlled by Bit 1 of Serial power-up state of the PLL range bit is Logic 1; a higher gain is
Register Bank 20 hex. When this bit is set active high, the required for frequencies greater than 200 MHz.
AD9854 serial port is in LSB-first format. This bit defaults low,
to the MSB-first format. The instruction byte must be written in CR [21] is the bypass PLL bit, active high. When this bit is
the format indicated by Bit 1 of Serial Register Bank 20 hex. active, the PLL is powered down and the REFCLK input is used
Therefore, if the AD9854 is in LSB-first mode, the instruction to drive the system clock signal. The power-up state of the
byte must be written from least significant bit to most bypass PLL bit is Logic 1 with PLL bypassed.
significant bit. CR [20:16] bits are the PLL multiplier factor. These bits are the
CONTROL REGISTER DESCRIPTION REFCLK multiplication factor unless the bypass PLL bit is set.
The PLL multiplier valid range is from 4 to 20, inclusive.
The control register is located in the shaded portion of Table 8
at Address 1D to Address 20 hex. It is composed of 32 bits. CR [15] is the Clear Accumulator 1 bit. This bit has a one-shot
Bit 31 is located at the top left position, and Bit 0 is located in type of function. When this bit is written active (Logic 1), a
the lower right position of the shaded portion. In the text that Clear Accumulator 1 signal is sent to the DDS logic, resetting
follows, the register descriptions have been subdivided to make it the accumulator value to 0. The bit is then automatically reset,
easier to locate the text associated with specific control categories. but the buffer memory is not reset. This bit allows the user to
easily create a sawtooth frequency sweep pattern with minimal
CR [31:29] are open. intervention. This bit is intended for chirp mode only, but its
CR [28] is the comparator power-down bit. When this bit is set function is still retained in other modes.
(Logic 1), its signal indicates to the comparator that a power- CR [14] is the clear accumulator bit. When this bit is active high,
down mode is active. This bit is an output of the digital section it holds both the Accumulator 1 and Accumulator 2 values at 0
and is an input to the analog section. for as long as the bit is active. This allows the DDS phase to be
CR [27] must always be written to Logic 0. Writing this bit to initialized via the I/O port.
Logic 1 causes the AD9854 to stop functioning until a master CR [13] is the triangle bit. When this bit is set, the AD9854
reset is applied. automatically performs a continuous frequency sweep from F1
CR [26] is the Q DAC power-down bit. When this bit is set to F2 frequencies and back. This results in a triangular
(Logic 1), it indicates to the Q DAC that a power-down mode frequency sweep. When this bit is set, the operating mode must
is active. be set to ramped FSK.

CR [25] is the full DAC power-down bit. When this bit is set CR [12] is the source Q DAC bit. When this bit is set high, the
(Logic 1), it indicates to both the I and Q DACs, as well as the Q path DAC accepts data from the Q DAC register.
reference, that a power-down mode is active. CR [11:9] are the three bits that describe the five operating
CR [24] is the digital power-down bit. When this bit is set modes of the AD9854:
(Logic 1), its signal indicates to the digital section that a power- 0x0 = single-tone mode
down mode is active. Within the digital section, the clocks are
forced to dc, effectively powering down the digital section. In 0x1 = FSK mode
this state, the PLL still accepts the REFCLK signal and
continues to output the higher frequency. 0x2 = ramped FSK mode

CR [23] is reserved. Write to 0. 0x3 = chirp mode

0x4 = BPSK mode

Rev. E | Page 38 of 52
 AD9854
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CS

SCLK

00636-058
SDIO I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 58. Serial Port Write Timing Clock Stall Low

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

SDIO I7 I6 I5 I4 I3 I2 I1 I0 DON'T CARE

00636-059
SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 59. 3-Wire Serial Port Read Timing Clock Stall Low

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

00636-060
SDIO I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 60. Serial Port Write Timing Clock Stall High

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

00636-061
SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 61. 2-Wire Serial Port Read Timing Clock Stall High

CR [8] is the internal update active bit. When this bit is set to CR [4] is the internal/external output shaped keying control bit.
Logic 1, the I/O UD CLK pin is an output and the AD9854 When this bit is set to Logic 1, the output shaped keying factor is
generates the I/O UD CLK signal. When this bit is set to Logic 0, internally generated and applied to both the I and Q paths.
external I/O UD CLK functionality is performed and the I/O When this bit is cleared (default), the output shaped keying
UD CLK pin is configured as an input. function is externally controlled by the user, and the ouput
shaped keying factor is the value of the I and Q output shaped
CR [7] is reserved. Write to 0. keying factor register. The two registers that are the output
CR [6] is the inverse sinc filter bypass bit. When this bit is set, shaped keying factors also default low such that the output is off
the data from the DDS block goes directly to the output shaped at power-up until the device is programmed by the user.
keying logic, and the clock to the inverse sinc filter is stopped. CR [3:2] are reserved. Write to 0.
Default is clear with the filter enabled.
CR [1] is the serial port MSB-/LSB-first bit. Default is low,
CR [5] is the shaped keying enable bit. When this bit is set, the MSB first.
output ramping function is enabled and is performed in
accordance with the CR [4] bit requirements. CR [0] is the serial port SDO active bit. Default is low, inactive.

Rev. E | Page 39 of 52
AD9854

POWER DISSIPATION AND THERMAL CONSIDERATIONS

The AD9854 is a multifunctional, high speed device that targets JUNCTION TEMPERATURE CONSIDERATIONS
a wide variety of synthesizer and agile clock applications. The The power dissipation (PDISS) of the AD9854 in a given
numerous innovative features contained in the device each application is determined by many operating conditions. Some
consume incremental power. If enabled in combination, the safe of the conditions have a direct relationship with PDISS, such as
thermal operating conditions of the device may be exceeded. supply voltage and clock speed, but others are less deterministic.
Careful analysis and consideration of power dissipation and The total power dissipation within the device and its effect on
thermal management is a critical element in the successful the junction temperature must be considered when using the
application of the AD9854. However, in most cases, disabling device. The junction temperature of the device is given by
the inverse sinc filter prevents exceeding the maximum die
temperature, because the inverse sinc filter consumes (Thermal Impedance × Power Consumption) +
approximately 30% of the total power. Ambient Temperature

The AD9854 is specified to operate within the industrial tem- The maximum ambient temperature combined with the
perature range of −40°C to +85°C. This specification is conditional, maximum junction temperature establishes the following power
however, such that the absolute maximum junction temperature consumption limits for each package: 4.06 W for ASVZ models
of 150°C is not exceeded. At high operating temperatures, extreme and 1.71 W for ASTZ models.
care must be taken when operating the device to avoid exceeding Supply Voltage
the junction temperature and potentially damaging the device.
The supply voltage affects power dissipation and junction
Many variables contribute to the operating junction temperature because PDISS = V × I. Users should design for 3.3 V
temperature within the device, including nominal; however, the device is guaranteed to meet specifications
over the full temperature range and over the supply voltage
• Package style range of 3.135 V to 3.465 V.
• Selected mode of operation
• Internal system clock speed Clock Speed
• Supply voltage Clock speed directly and linearly influences the total power
• Ambient temperature dissipation of the device and therefore the junction temperature. As
a rule, to minimize power dissipation, the user should select the
The combination of these variables determines the junction lowest possible internal clock speed to support a given application.
temperature within the AD9854 for a given set of operating Typically, the usable frequency output bandwidth from a DDS is
conditions. limited to 40% of the clock rate to ensure that the requirements
of the output low-pass filter are reasonable. For a typical DDS
The AD9854 is available in two package styles: a thermally
application, the system clock frequency should be 2.5 times the
enhanced surface-mount package with an exposed heat sink and
highest desired output frequency.
a standard (nonthermally enhanced) surface-mount package. The
thermal impedance of these packages is 16.2°C/W and 38°C/W, Mode of Operation
respectively, measured under still air conditions. The selected mode of operation of the AD9854 significantly
THERMAL IMPEDANCE influences the total power consumption. Although the AD9854
offers many features targeting a wide variety of applications, the
The thermal impedance of a package can be thought of as a
device is designed to operate with only a few features enabled at
thermal resistor that exists between the semiconductor surface
once for a given application. If multiple features are enabled at
and the ambient air. The thermal impedance is determined by
higher clock speeds, the maximum junction temperature of the
the package material and the physical dimensions of the package.
die may be exceeded, severely limiting the long-term reliability of
The dissipation of the heat from the package is directly dependent
the device. Figure 62 and Figure 63 show the power requirements
on the ambient air conditions and the physical connection made
associated with each feature of the AD9854. These graphs should
between the IC package and the PCB.
be used as a guide in determining power consumption for
Adequate dissipation of heat from the AD9854 relies on all specific feature sets.
power and ground pins of the device being soldered directly to
Figure 62 shows the supply current consumed by the AD9854
a copper plane on a PCB. In addition, the thermally enhanced
over a range of frequencies for two possible configurations. All
package of the AD9854ASVZ has an exposed paddle on the
circuits enabled means that the output scaling multipliers, the
bottom of the package that must be soldered to a large copper
inverse sinc filter, the Q DAC, and the on-board comparator are
plane, which, for convenience, can be the ground plane. Sockets
enabled. Basic configuration means that the output scaling
for either package style of the device are not recommended.

Rev. E | Page 40 of 52
 AD9854
multipliers, the inverse sinc filter, the Q DAC, and the on-board EVALUATION OF OPERATING CONDITIONS
comparator are disabled.
The first step in applying the AD9854 is to select the internal
1400
clock frequency. Clock frequency selections greater than
1200
200 MHz require the use of the thermally enhanced package
ALL CIRCUITS ENABLED (AD9854ASVZ); other clock frequencies may allow the use of the
standard plastic surface-mount package, but more information is
SUPPLY CURRENT (mA)

1000
needed to make that determination.
800
The second evaluation step is to determine the maximum
600 required operating temperature for the AD9854 in a given
application. Subtract this value from 150°C, which is the
400
maximum junction temperature allowed for the AD9854. For
200 the extended industrial temperature range, the maximum
BASIC CONFIGURATION operating temperature is 85°C, which results in a difference of
0 65°C. This is the maximum temperature gradient that the
20 60 100 140 180 220 260 300
FREQUENCY (MHz) device can experience due to power dissipation.
NOTES
THIS GRAPH ASSUMES THAT THE AD9854 DEVICE IS SOLDERED The third evaluation step is to divide the maximum temper-
00636-062

TO A MULTILAYER PCB PER THE RECOMMENDED BEST

MANUFACTURING PRACTICES AND PROCEDURES FOR THE
ature gradient by the thermal impedance to determine the
GIVEN PACKAGE TYPE. maximum power dissipation allowed for the application.
Figure 62. Current Consumption vs. Clock Frequency For example, 65°C divided by the thermal impedance of the
package being used yields the total power dissipation limit (4.06
Figure 63 shows the approximate current consumed by each of W for the ASVZ models and 1.71 W for the ASTZ models).
four functions. Therefore, for a 3.3 V nominal power supply voltage, the
500 current consumed by the device with full operating conditions
450 INVERSE SINC FILTER must not exceed 515 mA for the standard plastic package and
400
1242 mA for the thermally enhanced package. The total set of
enabled functions and operating conditions of the AD9854
SUPPLY CURRENT (mA)

350
application must support these current consumption limits.
300

250 To determine the suitability of a given AD9854 application

200 OUTPUT SCALING in terms of the power dissipation requirements use Figure 62
MULTIPLIERS
and Figure 63. These graphs assume that the AD9854 device is
150
soldered to a multilayer PCB per the recommended best
100 Q DAC manufacturing practices and procedures for the given package
COMPARATOR
50 type. This ensures that the specified thermal impedance
0 specifications are achieved.
20 60 100 140 180 220 260 300
FREQUENCY (MHz) THERMALLY ENHANCED PACKAGE
NOTES MOUNTING GUIDELINES
THIS GRAPH ASSUMES THAT THE AD9854 DEVICE IS
SOLDERED TO A MULTILAYER PCB PER THE RECOMMENDED
Refer to the AN-772 Application Note for details on mounting
00636-063

BEST MANUFACTURING PRACTICES AND PROCEDURES FOR

THE GIVEN PACKAGE TYPE. devices with an exposed paddle.
Figure 63. Current Consumption by Function vs. Clock Frequency

Rev. E | Page 41 of 52
AD9854

EVALUATION BOARD
An evaluation board package is available for the AD9854 DDS Hardware Preparation
device. This package consists of a PCB, software, and Use the schematics (see Figure 64 and Figure 65) in conjunction
documentation to facilitate bench analysis of the device’s with these instructions to become acquainted with the electrical
performance. To ensure optimum dynamic performance from functioning of the evaluation board.
the device, users should familiarize themselves with the operation
and performance capabilities of the AD9854 with the evaluation Attach power wires to the connector labeled TB1 using the
board and use the evaluation board as a PCB reference design. screw-down terminals. This connector is plastic and press-fits
over a 4-pin header soldered to the board. Table 11 lists the
EVALUATION BOARD INSTRUCTIONS connections to each pin.
The AD9852/AD9854 Revision E evaluation board includes
either an AD9852ASVZ or AD9854ASVZ IC. Table 11. Power Requirements for DUT Pins1
AVDD 3.3 V DVDD 3.3 V VCC 3.3 V Ground
The ASVZ package permits 300 MHz operation by virtue of its For all DUT For all DUT For all other For all
thermally enhanced design. This package has a bottom-side analog pins digital pins devices devices
heat slug that must be soldered to the ground plane of the PCB
1
directly beneath the IC. In this manner, the evaluation board DUT = device under test.

PCB ground plane layer extracts heat from the AD9852 or

AD9854 IC package. If device operation is limited to 200 MHz Clock Input, J25
or less, the ASTZ package can be used without a heat slug in Attach REFCLK to the clock input, J25. This is a single-ended
customer installations over the full temperature range. input that is routed to the MC100LVEL16D for conversion to
differential PECL output. This is accomplished by attaching a 2 V
Evaluation boards for both the AD9852 and AD9854 are
p-p clock or sine wave source to J25. Note that this is a 50 Ω
identical except for the installed IC.
impedance point set by R13. The input signal is ac-coupled and
To assist in proper placement of the pin header shorting then biased to the center-switching threshold of the
jumpers, the instructions refer to direction (left, right, top, MC100LVEL16D. To engage the differential clocking mode of the
bottom) as well as header pins to be shorted. Pin 1 for each AD9854, Pin 2 and Pin 3 (the bottom two pins) of W3 must be
3-pin header is marked on the PCB corresponding with the connected with a shorting jumper.
schematic diagram. When following these instructions, position
The signal arriving at the AD9854 is called the reference clock.
the PCB so that the PCB text can be read from left to right. The
When engaging the on-chip PLL clock multiplier, this signal is
board is shipped with the pin headers configuring the board as
the reference clock for the PLL and the multiplied PLL output
follows:
becomes the system clock. If the PLL clock multiplier is to be
• REFCLK for the AD9852 or AD9854 is configured as bypassed, the reference clock supplied by the user directly
differential. The differential clock signals are provided by operates the AD9854 and is therefore the system clock.
the MC100LVEL16D differential receiver.
Three-State Control
• The input clock for the MC100LVEL16D is single ended
via J25. This signal may be 3.3 V CMOS or a 2 V p-p sine The W9, W11, W12, W13, W14, and W15 switch headers must
wave capable of driving 50 Ω (R13). be shorted to allow the provided software to control the AD9854
• Both DAC outputs from the AD9852 or AD9854 are evaluation board via the printer port connector, J11.
routed through the two 120 MHz elliptical LP filters, and Programming
their outputs are connected to J7 (Q, or control DAC) and
If programming of the AD9854 is not to be provided by the
J6 (I, or cosine DAC).
user’s PC and Analog Devices software, the W9, W11, W12,
• The board is set up for software control via the printer port
W13, W14, and W15 headers should be opened (shorting
connector.
jumpers removed). This effectively detaches the PC interface
• The output currents of the DAC are configured for 10 mA.
and allows J10 (the 40-pin header) and J1 to assume control
GENERAL OPERATING INSTRUCTIONS without bus contention. Input signals on J10 and J1 going to the
AD9854 should be 3.3 V CMOS logic levels.
Load the CD software onto your PC’s hard disk. The current
software (Version 1.72) supports Windows® 95, Windows 98, Low-Pass Filter Testing
Windows 2000, Windows NT®, and Windows XP. The purpose of the 2-pin W7 and W10 headers (associated with
J4 and J5) is to allow the two 50 Ω, 120 MHz filters to be tested
Connect a printer cable from the PC to the AD9854 evaluation
during PCB assembly without interference from other circuitry
board printer port connector labeled J11.
attached to the filter inputs. Typically, a shorting jumper is
Rev. E | Page 42 of 52
 AD9854
attached to each header to allow the DAC signals to be routed The resulting I and Q signals appear as nearly pure sine waves
to the filters. If the user wishes to test the filters, the shorting and 90° out of phase with each other. These filters are designed
jumpers at W7 and W10 should be removed and 50 Ω test with the assumption that the system clock speed is at or near its
signals should be applied at the J4 and J5 inputs to the 50 Ω maximum speed (300 MHz). If the system clock speed is much
elliptic filters. Users should refer to the schematic provided and to less than 300 MHz, for example 200 MHz, it is possible, or
the following sections to properly position the remaining inevitable, that unwanted DAC products other than the
shorting jumpers. fundamental signal will be passed by the low-pass filters.

Observing the Unfiltered IOUT1 and the Unfiltered If the AD9852 evaluation board is used, any reference to the Q
IOUT2 DAC Signals signal should be interpreted as meaning the control DAC.
The unfiltered DAC outputs can be observed at J5 (the I, or
Observing the Filtered IOUT1 and the Filtered IOUT1
cosine DAC, signal) and J4 (the Q, or control DAC, signal). Use
the following procedure to route the two 50 Ω terminated The filtered I DAC outputs can be observed at J6 (the true signal)
analog DAC outputs to the SMB connectors and to disconnect and J7 (the complementary signal). Use the following procedure to
any other circuitry: route the 120 MHz low-pass filters in the true and complementary
output paths of the I DAC to remove images, aliased harmonics,
1. Install shorting jumpers at W7 and W10. and other spurious signals that are greater than approximately
2. Remove the shorting jumper at W16. 120 MHz:
3. Remove the shorting jumper from the 3-pin W1 header.
4. Install a shorting jumper on Pin 1 and Pin 2 (bottom two 1. Install shorting jumpers at W7 and W10.
pins) of the 3-pin W4 header. 2. Install a shorting jumper at W16.
3. Install a shorting jumper on Pin 2 and Pin 3 (top two pins)
The raw DAC outputs may appear as a series of quantized of the 3-pin W1 header.
(stepped) output levels that may not resemble a sine wave until 4. Install a shorting jumper on Pin 2 and Pin 3 (top two pins)
they are filtered. The default 10 mA output current develops a of the 3-pin W4 header.
0.5 V p-p signal across the on-board 50 Ω termination. If the 5. Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins)
observation equipment offers 50 Ω inputs, the DAC develops of the 3-pin W2 and W8 headers.
only 0.25 V p-p due to the double termination.
The resulting signals appear as nearly pure sine waves and 180°
If using the AD9852 evaluation board, the user can control out of phase with each other. If the system clock speed is much
IOUT2 (the control DAC output) by using the serial or parallel less than 300 MHz, for example 200 MHz, it is possible, or
ports. The 12-bit, twos complement value(s) is/are written to inevitable, that unwanted DAC products other than the
the control DAC register that sets the IOUT2 output to a static fundamental signal will be passed by the low-pass filters.
dc level. Allowable hexadecimal values are 7FF (maximum) to
800 (minimum), with all 0s being midscale. Rapidly changing Connecting the High Speed Comparator
the contents of the control DAC register (up to 100 MSPS) To connect the high speed comparator to the DAC output
allows IOUT2 to assume any waveform that can be signals use either the quadrature filtered output configuration
programmed. (for AD9854 only) or the complementary filtered output
configuration outlined in the previous section (for both the
Observing the Filtered IOUT1 and the Filtered IOUT2
AD9854 and the AD9852). Follow Step 1 through Step 4 in
The filtered I (cosine DAC) and Q (control DAC) outputs can either the Observing the Filtered IOUT1 and the Filtered
be observed at J6 (for the I signal) and J7 (for the Q signal). Use IOUT2 section or the Observing the Filtered IOUT1 and the
the following procedure to route the 50 Ω (input and output Z) Filtered IOUT1 section. Then install a shorting jumper on Pin 1
low-pass filters into the pathways of the I and Q signals to and Pin 2 (top two pins) of the 3-pin W2 and W8 headers. This
remove images, aliased harmonics, and other spurious signals reroutes the filtered signals away from the output connectors
that are greater than approximately 120 MHz: (J6 and J7) and to the 100 Ω configured comparator inputs.
This sets up the comparator for differential input without
1. Install shorting jumpers at W7 and W10.
affecting the comparator output duty cycle, which should be
2. Install a shorting jumper at W16.
approximately 50% in this configuration.
3. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins)
of the 3-pin W1 header. The user can change the value of RSET Resistor R2 from 3.9 kΩ
4. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins) to 1.95 kΩ to receive more robust signals at the comparator
of the 3-pin W4 header. inputs. This decreases jitter and extends the operating range of
5. Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins) the comparator. To implement this change install a shorting
of the 3-pin W2 and W8 headers. jumper at W6, which provides a second 3.9 kΩ chip resistor
(R20) in parallel with that provided by R2. This boosts the DAC
Rev. E | Page 43 of 52
AD9854
output current from 10 mA to 20 mA and doubles the peak-to- Several numerical entries, such as frequency and phase infor-
peak output voltage developed across the loads, thus resulting mation, require pressing Enter to register the information. For
in more robust signals at the comparator inputs. example, if a new frequency is input but does not take effect
when Load is clicked, the user probably neglected to press Enter
Single-Ended Configuration after typing the new frequency information.
To connect the high speed comparator in a single-ended
configuration so that the duty cycle or pulse width can be Normal operation of the AD9852/AD9854 evaluation board
controlled, a dc threshold voltage must be present at one of the begins with a master reset. After this reset, many of the default
comparator inputs. The user can supply this voltage using the register values are depicted in the software control panel. The reset
control DAC. A 12-bit, twos complement value is written to the command sets the DDS output amplitude to minimum and 0 Hz,
control DAC register that sets the IOUT2 output to a static dc zero phase offset, as well as other states that are listed in the
level. Allowable hexadecimal values are 7FF (maximum) to 800 Register Layout table (Table 8 for AD9854).
(minimum), with all 0s being midscale. The IOUT1 channel
The next programming block should be the reference clock and
continues to output a filtered sine wave programmed by the
multiplier because this information is used to determine the
user. These two signals are routed to the comparator by using
proper 48-bit frequency tuning words that are entered and later
the 3-pin W2 and W8 header switches. Use of the configuration
calculated.
described in the Observing the Filtered IOUT1 and the Filtered
IOUT2 section is required. Follow Step 1 through Step 4 in this The output amplitude defaults to the 12-bit, straight binary
section, and then install a shorting jumper on Pin 1 and Pin 2 multiplier values of the I (cosine DAC) multiplier register of
(top two pins) of the 3-pin W2 and W8 headers. 000 hex; no output (dc) should be seen from the DAC. Set the
multiplier amplitude in the Output Amplitude dialog box to a
The user can change the value of RSET Resistor R2 from 3.9 kΩ
substantial value, such as FFF hex. The digital multiplier can be
to 1.95 kΩ to receive more robust signals at the comparator
bypassed by selecting Output Amplitude is always Full Scale, but
inputs. This decreases jitter and extends the operating range of
this usually does not result in the best spurious-free dynamic range
the comparator. To implement this change install a shorting
(SFDR). The best SFDR, achieving improvements of up to 11 dB, is
jumper at W6, which provides a second 3.9 kΩ chip resistor
obtained by routing the signal through the digital multiplier and
(R20) in parallel with that provided by R2.
then reducing the multiplier amplitude. For instance, FC0 hex
USING THE PROVIDED SOFTWARE produces less spurious signal amplitude than FFF hex. If SFDR
must be maximized, this exploitable and repeatable phenomenon
The evaluation software is provided on a CD, along with a brief
should be investigated in the given application. This phenomenon
set of instructions. Use the instructions in conjunction with the
is more readily observed at higher output frequencies, where
AD9852 or AD9854 data sheet and the AD9852 or AD9854
good SFDR becomes more difficult to achieve.
evaluation board schematic.
Refer to this data sheet and the evaluation board schematic to
The CD contains the following:
understand the available functions of the AD9854 and how the
• The AD9852/AD9854 evaluation software software responds to programming commands.
• AD9854 evaluation board instructions
SUPPORT
• AD9854 data sheet
• AD9854 evaluation board schematics Applications assistance is available for the AD9854, the AD9854
• AD9854 PCB layout PCB evaluation board, and all other Analog Devices products.
Call 1-800-ANALOGD or visit www.analog.com/dds.

Rev. E | Page 44 of 52
 AD9854

Table 12. AD9854 Customer Evaluation Board (AD9854 PCB > U1 = AD9854ASVZ)
Reference Min
Item Qty Designator Device Package Value Tol Manufacturer Manufacturer Part No.
1 3 C1, C2, C45 Capacitor 0805 805 0.01 μF, 10% Kemet Corp. C0805C103K5RACTU
50 V, X7R
2 21 C7, C8, C9, C10, Capacitor 0603 603 0.1 μF, 10% Murata GRM188R71H104KA93D
C11, C12, C13, 50 V, X7R Manufacturing
C14, C16, C17, Co., Ltd.
C18, C19, C20,
C22, C23, C24,
C26, C27, C28,
C29, C44
3 2 C4, C37 Capacitor 1206 1206 27 pF, 5% Yageo Corporation CC1206JRNPO9BN270
50 V, NPO
4 2 C5, C38 Capacitor 1206 1206 47 pF, 5% Yageo Corporation CC1206JRNPO9BN470
50 V, NPO
5 3 C6, C21, C25 Capacitor TAJC TAJC 10 μF, 10% AVX TAJC106K016R
16 V, TAJ
6 2 C30, C39 Capacitor 1206 1206 39 pF, 5% Yageo Corporation CC1206JRNPO9BN390
50 V, NPO
7 2 C31, C40 Capacitor 1206 1206 22 pF, 5% Yageo Corporation CC1206JRNPO9BN220
50 V, NPO
8 2 C32, C41 Capacitor 1206 1206 2.2 pF, 0.25 Yageo Corporation CC1206CRNPO9BN2R2
50 V, NPO pF
9 2 C33, C42 Capacitor 1206 1206 12 pF, 5% Yageo Corporation 1206CG120J9B200
50 V, NPO
10 2 C34, C43 Capacitor 1206 1206 8.2 pF, 0.5 Yageo Corporation CC1206DRNPO9BN8R2
50 V, NPO pF
11 9 J1, J2, J3, J4, J5, SMB STR-PC MNT N/A N/A Emerson/Johnson 131-3701-261
J6, J7, J25, J26
12 1 J10 40-pin header Header 40 N/A N/A Samtec, Inc. TSW-120-23-L-D
13 4 L1, L2, L3, L5 Inductor coil 1008CS 68 nH 2% Coilcraft, Inc. 1008CS-680XGLB
14 2 L4, L6 Inductor coil 1008CS 82 nH 2% Coilcraft, Inc. 1008CS-820XGLB
15 2 R1, R5 RES_SM 1206 49.9 Ω, 1% Panasonic-ECG ERJ-8ENF49R9V
¼W
16 2 R2, R20 RES_SM 1206 3.92 kΩ, 1% Panasonic-ECG ERJ-8ENF3921V
¼W
17 2 R3, R7 RES_SM 1206 24.9 Ω, 1% Panasonic-ECG ERJ-8ENF24R9
¼W
18 1 R4 RES_SM 1206 1.3 kΩ, 1% Panasonic-ECG ERJ-8ENF1301V
¼W
19 4 R6, R11, RES_SM 1206 49.9 Ω, 1% Panasonic-ECG ERJ-8ENF49R9V
R12, R13 ¼W
20 1 R8 RES_SM 1206 2 kΩ, 1% Panasonic-ECG ERJ-8ENF2001V
¼W
21 2 R9, R10 RES_SM 1206 100 Ω, 1% Panasonic-ECG ERJ-8ENF1000V
¼W
22 4 R15, R16, RES_SM 1206 10 kΩ, 1% Panasonic-ECG ERJ-8ENF1002V
R17, R18 ¼W
23 1 RP1 Resistor SIP-10P 10 kΩ 2% Bourns 4610X-101-103LF
network
24 1 TB1 TB4 4-position N/A N/A Wieland Electric, Inc. Plug: 25.602.2453.0;
terminal terminal strip: Z5.530.3425.0
25 1 U1 AD9854 SV-80 N/A N/A Analog Devices, Inc. AD9854ASVZ
26 1 U2 74HC125D 14 SOIC N/A N/A Texas Instruments SN74HC125DR
Incorporated

Rev. E | Page 45 of 52
AD9854
Reference Min
Item Qty Designator Device Package Value Tol Manufacturer Manufacturer Part No.
27 1 U3 Primary 8 SOIC N/A N/A ON Semiconductor Primary: MC10EP16DGOS
Secondary 8 SOIC N/A N/A ON Semiconductor Secondary:
MC100LVEL16DGOS
28 4 U4, U5, U6, U7 74HC14 14 SOIC N/A N/A Texas Instruments SN74HC14DR
Incorporated
29 3 U8, U9, U10 74HC574 20 SOIC N/A N/A Texas Instruments SN74HC574DWR
Incorporated
30 1 J11 C36CRPX 36CRP N/A N/A Tyco Electronics 5552742-1
Corporation
31 6 W1, W2, W3, W4, 3-pin header SIP-3P N/A N/A Samtec, Inc. TSW-103-07-S-S
W8, W17
32 10 W6, W7, W9, 2-pin header SIP-2P N/A N/A Samtec, Inc. TSW-102-07-S-S
W10, W11, W12,
W13, W14, W15,
W16
33 6 W1, W2, W3, W4, Jumpers N/A Black N/A Samtec, Inc. SNT-100-BK-G
W8, W17
34 10 W6, W7, W9, Jumpers N/A Black N/A Samtec, Inc. SNT-100-BK-G
W10, W11, W12,
W13, W14, W15,
W16
35 2 N/A Self-tapping 4–40, Phillips N/A N/A 90410A107
screw pan head
36 4 N/A Adhesive feet N/A Black N/A 3M SJ-5518
37 1 AD9852/54 PCB N/A N/A N/A N/A GS02669 REV. E
38 2 R14, R19 RES_SM 1206 0 Ω, 5% Panasonic-ECG ERJ-8GEY0R00V
¼W
39 4 N/A Pin socket Tyco Electronics 5-5330808-6
(open end) Corporation
40 1 Y1 XTAL COSC N/A N/A Optional Optional

Rev. E | Page 46 of 52
 GND
GND DVDD J15

DVDD
DVDD
RESET
PMODE
CLK
CLK8
AVDD
W3
J16 J8
1 GND J17 J6 GND
GND GND
AVDD J18 J11
GND
R4 C1 J19 J12
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1.3kΩ 0.01µF J20 J13
J22 J14

NC5
J24 J21

GND4
GND3
J23

DVDD9
DVDD8
DVDD7
DVDD6

DGND9
DGND8
DGND7
DGND6
PLLFLT

REFCLK
REFCLK

MRESET
CLKVDD

OPTGND
CLKGND
D7 1 D7 PLLVDD 60 AVDD

SPSELECT
120MHz LOW-PASS FILTER

DIFFCLKEN
D6 2 D6 PLLGND 59 R20
GND C32 C33 C34 J6
D5 3 D5 NC4 58 3.92kΩ 2.2pF 12pF 8.2pF
D4 4 D4 NC3 57 R2 R1 W2 GND
W6
3.92kΩ 49.9Ω GND 1
D3 5 D3 RSET 56 L4 L5 L2
GND J4 82nH 68nH 68nH
D2 6 D2 DACBYPASS 55 AVDD
D1 7 D1 AVDD2 54 AVDD C45 C4 C5 C30 C31
U1 0.01µF W7 GND 27pF 47pF 39pF 22pF
D0 8 D0 AGND2 53
AD9854 GND 1
DVDD 9 DVDD1 IOUT2 52 W1
TOP VIEW GND GND GND GND
DVDD 10 DVDD2 (Not to Scale) IOUT2 51
R3 GND 120MHz LOW-PASS FILTER
11 DGND1 AVDD 50 AVDD 24.9Ω
GND C41 C42 C43 J7
12 DGND2 IOUT1 49 W4
GND 1 2.2pF 12pF 8.2pF
13 NC IOUT1 48 J5
R7 R6 W8
A5 14 ADDR5 AGND 47 1 GND
GND 24.9Ω 49.9Ω L6 L3 L1
GND
A4 15 ADDR4 GND2 46 82nH 68nH 68nH
GND W10 W16
A3 16 ADDR3 COMPGND 45 GND GND
GND C37 C38 C39 C40
A2/IO RESET 17 ADDR2 COMPVDD 44 AVDD 27pF 47pF 39pF 22pF
R5
A1/SDO 18 ADDR1 VINN 43 49.9Ω
GND GND GND GND
A0/SDIO 19 ADDR0 VINP 42

Rev. E | Page 47 of 52
GND
I/O UD CLK 20 UPDCLK GND 41
GND R9
J25 Y1

COUTGND2

WR
RD
DVDD3
DVDD4
DVDD5
DGND3
DGND4
DGND5
FSK/BPSK/HOLD
OSK
DACDVDD
DACDVDD2
DACDGND
DACDGND2
NC2
VOUT
COUTVDD
COUTVDD2
COUTGND
100Ω 8 7
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND OUT GND

Figure 64. Evaluation Board Schematic

NC = NO CONNECT 14 1
GND 1 DVDD 3.3V NC GND
R10 W17
100Ω U3 CLKB J3
2

OSK
7

GND

GND
GND
GND
GND
GND
GND
D Q

AVDD
AVDD
AVDD
AVDD

DVDD
DVDD
DVDD

RD/CS
GND
R13 C2 3 6 R19
R8 D Q

WR/SCLK
J1 J26 GND 49.9Ω 0.01µF 0Ω GND
2kΩ MC100LVEL16DGOS
FDATA GND GND R14 J2
VCC

VEE
VBB

DVDD 0Ω
C25 C24 C23 C22 C27 C8 C44 5 4 8
0.1µF CLK
10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF R11

D7
D6
D5
D4
D3
D2
D1
D0
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
UDCLK
WR
RD
PMODE
OSK
RESET
GND DVDD R12 GND
49.9Ω
GND 49.9Ω
VCC

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
J10 TB1 C21 C20 C19 C18 C17 C16 C14 C26 C28
0.1µF GND

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
AVDD
2 GND
DVDD
3 AVDD
GND VCC
C6 C7 C29 C9 C10 C11 C12 C13
4 0.1µF
10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
GND
GND
00636-068
AD9854
 VCC
AD9854
R18
10kΩ

W15
VCC RP1
10kΩ
1 2 3 4 5 6 7 8 9 10 U8 U9
1 GND
EN VCC: 20
1 EN VCC: 20
11 11
1 C1 GND: 10 C1 GND: 10
C0 U5 74HC574 74HC574
2 2 9 12 9 12
A0
1 1A 1Y 8D D0 8D ADDR5
3 8 13 8 13
A1
3 2A
2Y 4 D1 ADDR4
4 5 6 7 14 7 14
A2 3A 3Y D2 ADDR3
5 9 8 6 15 6 15 ADDR2
A3 4A 4Y D3
6 11 10 5 16 5 16 U10
A4 5A 5Y D4 1
7 4 17 4 EN VCC: 20
13 6Y 12 17
A5 6A D5 11 C1 GND: 10
3 18 3 18
8 74HC14 D6 74HC574
A6 2 19 2 19 9 12
VCC GND 1D D7 1D 8D WR
A7 9 8 13
14 7 RD
7 14 RESET
VCC
J11 6 15
VCC GND UDCLK
36PINCONN 16 W12
5
GND:[19:30] PMODE
4 17
U6 ORAMP
W13
1 3 18
10 1A 1Y 2 FDATA
B6 19 W9
3 2A 4 2 1D
11 2Y
B7 VCC 5 6
12 3A 3Y
B5 9 8
13 4A 4Y
B4 11 10
5A 5Y

Rev. E | Page 48 of 52
13 6Y 12
6A
U2
74HC14
14 1 1G
VCC GND VCC 14 VCC
C1 U4

Figure 65. Evaluation Board Schematic

2 1A
14 7 4G 13
1 1A 1Y 2 3 1Y
R15 VCC 4A 12
GND 3 4 ADDR1
10kΩ 2A 2Y W11 4 2G
4Y 11
5 3A 6 5 2A
VCC 3Y 3G 10
8 6 2Y 9
9 4A 4Y 3A
10 ADDR0 W14 7 GND 8
11 5A 5Y 3Y
VCC
U7 13 6A 6Y 12 74HC125D
GND
R16 1 1A 1Y 2 74HC14
10kΩ
3 2A 2Y 4 VCC GND
31 VCC
5 3A 6 14 7
C2 3Y
9 4A 4Y 8 VCC GND
VCC
32 10
B3 VCC
11 5A 5Y
13 6A 6Y 12
74HC14
VCC
VCC GND
14 7
R17 VCC GND
10kΩ
36
C3
00636-069
 AD9854

00636-070
Figure 66. Assembly Drawing

00636-071

Figure 67. Top Routing Layer, Layer 1

Rev. E | Page 49 of 52
AD9854

00636-072
Figure 68. Power Plane Layer, Layer 3

00636-073

Figure 69. Ground Plane Layer, Layer 2

Rev. E | Page 50 of 52
 AD9854

00636-074
Figure 70. Bottom Routing Layer, Layer 4

Rev. E | Page 51 of 52
AD9854

OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80 14.20
0.75 1.20 14.00 SQ
MAX 13.80
0.60
0.45 80 61 61 80
1 60 60 1
PIN 1

TOP VIEW EXPOSED 9.50 SQ

(PINS DOWN) PAD

1.05 0° MIN
0.20 BOTTOM VIEW
1.00 0.09 (PINS UP)
20 41 41 20
0.95 7° 21 40 40 21
3.5°
0.15 SEATING 0° VIEW A
0.65 BSC 0.27
0.05 PLANE 0.08 MAX LEAD PITCH 0.22
COPLANARITY
0.17

VIEW A
ROTATED 90° CCW

091506-A
COMPLIANT TO JEDEC STANDARDS MS-026-AEC-HD

Figure 71. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-80-4)
Dimensions shown in millimeters

16.20
0.75 16.00 SQ
1.60 15.80
0.60 MAX
0.45 80 61
1 60

PIN 1

14.20
TOP VIEW
(PINS DOWN) 14.00 SQ
13.80
1.45
0.20
1.40
0.09
1.35
7°
3.5°
0.15 0° 20 41
0.05 SEATING 0.10 21 40
PLANE COPLANARITY
VIEW A 0.65 0.38
BSC 0.32
VIEW A LEAD PITCH
ROTATED 90° CCW 0.22
051706-A

COMPLIANT TO JEDEC STANDARDS MS-026-BEC

Figure 72. 80-Lead Low Profile Quad Flat Package [LQFP]

(ST-80-2)
Dimensions shown in millimeters

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9854ASVZ 1 −40°C to +85°C 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-4
AD9854AST −40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9854ASTZ1 −40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-2
AD9854/PCB Evaluation Board
1
Z = RoHS Compliant Part.

©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C00636-0-7/07(E)

Rev. E | Page 52 of 52