1 GSPS, 14-Bit, 3.

3 V CMOS
Direct Digital Synthesizer
Data Sheet AD9910
FEATURES APPLICATIONS
1 GSPS internal clock speed (up to 400 MHz analog output) Agile local oscillator (LO) frequency synthesis
Integrated 1 GSPS, 14-bit DAC Programmable clock generators
0.23 Hz or better frequency resolution FM chirp source for radar and scanning systems
Phase noise ≤ −125 dBc/Hz @ 1 kHz offset (400 MHz carrier) Test and measurement equipment
Excellent dynamic performance with Acousto-optic device drivers
>80 dB narrow-band SFDR Polar modulators
Serial input/output (I/O) control Fast frequency hopping
Automatic linear or arbitrary frequency, phase, and
amplitude sweep capability
8 frequency and phase offset profiles
Sin(x)/(x) correction (inverse sinc filter)
1.8 V and 3.3 V power supplies
Software and hardware controlled power-down
100-lead TQFP_EP package
Integrated 1024 word × 32-bit RAM
PLL REFCLK multiplier
Parallel datapath interface
Internal oscillator can be driven by a single crystal
Phase modulation capability
Amplitude modulation capability
Multichip synchronization

FUNCTIONAL BLOCK DIAGRAM

AD9910 HIGH SPEED PARALLEL

DATA INTERFACE

LINEAR
RAMP
GENERATOR

1GSPS DDS CORE 14-BIT DAC

1024-
ELEMENT
RAM

REFCLK
MULTIPLIER TIMING AND CONTROL

SERIAL CONTROL
DATA PORT
06479-001

Figure 1.

Rev. E Document Feedback

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AD9910 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Output Shift Keying (OSK) ....................................................... 26

Applications ....................................................................................... 1 Digital Ramp Generator (DRG) ............................................... 27

Functional Block Diagram .............................................................. 1 RAM Control .............................................................................. 32

Revision History ............................................................................... 3 Additional Features ........................................................................ 41

General Description ......................................................................... 4 Profiles ......................................................................................... 41

Specifications..................................................................................... 5 I/O_UPDATE, SYNC_CLK, and System Clock Relationships

....................................................................................................... 41
Electrical Specifications ............................................................... 5
Automatic I/O Update ............................................................... 42
Absolute Maximum Ratings ............................................................ 8
Power-Down Control ................................................................ 42
Equivalent Circuits ....................................................................... 8
Synchronization of Multiple Devices ........................................... 43
ESD Caution .................................................................................. 8
Power Supply Partitioning............................................................. 46
Pin Configuration and Function Descriptions ............................. 9
3.3 V Supplies.............................................................................. 46
Typical Performance Characteristics ........................................... 12
1.8 V Supplies.............................................................................. 46
Application Circuits ....................................................................... 15
Serial Programming ....................................................................... 47
Theory of Operation ...................................................................... 16
Control Interface—Serial I/O ................................................... 47
Single Tone Mode ....................................................................... 16
General Serial I/O Operation ................................................... 47
RAM Modulation Mode ............................................................ 17
Instruction Byte .......................................................................... 47
Digital Ramp Modulation Mode .............................................. 18
Serial I/O Port Pin Descriptions .............................................. 47
Parallel Data Port Modulation Mode....................................... 19
Serial I/O Timing Diagrams ..................................................... 48
Mode Priority .............................................................................. 21
MSB/LSB Transfers .................................................................... 48
Functional Block Detail ................................................................. 22
Register Map and Bit Descriptions .............................................. 49
DDS Core..................................................................................... 22
Register Bit Descriptions ........................................................... 54
14-Bit DAC Output .................................................................... 22
Outline Dimensions ....................................................................... 61
Inverse Sinc Filter ....................................................................... 23
Ordering Guide .......................................................................... 61
Clock Input (REF_CLK/REF_CLK) ........................................ 23

PLL Lock Indication ................................................................... 26

Rev. E | Page 2 of 64
Data Sheet AD9910
REVISION HISTORY
10/2016—Rev. D to Rev. E Changes to Figure 48 ...................................................................... 41
Change to Figure 33 ........................................................................25 Deleted I/O_UPDATE Pin Section .............................................. 41
Changes to Profiles Section ........................................................... 42
5/2012—Rev. C to Rev. D Added I/O_UPDATE, SYNC_CLK, and System Clock
Changes to Table 1 ............................................................................ 8 Relationships Section ...................................................................... 42
Changes to Table 3 ..........................................................................12 Added Figure 49; Renumbered Sequentially ............................... 42
Changes to Figure 39 ......................................................................31 Changes to Synchronization of Multiple Devices Section ......... 44
Changes to Synchronization of Multiple Devices Section .........45 Changes to DVDD (1.8V) (Pin 17, Pin 23, Pin 30, Pin 47,
Changes to Table 18 ........................................................................55 Pin 57, and Pin 64) Section and AVDD (1.8V) (Pin 89 and
Changes to Table 20 ........................................................................58 Pin 92) Section................................................................................. 47
Changes to Table 26 ........................................................................60 Changes to Control Interface—Serial I/O Section ..................... 48
Changes to Table 17 ........................................................................ 50
8/2010—Rev. B to Rev. C Changes to Table 19 ........................................................................ 57
Changes to XTAL_SEL Input Parameter in Table 1 ..................... 8 Changes to Table 20 and Table 21 ................................................. 58
Changes to Table 2 ............................................................................ 9
Changes to Transmit Enable (TxENABLE) Section ...................21 2/2008—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
12/2008—Rev. A to Rev. B Changes to REFCLK Multiplier Specification in Table 1 ............ 5
Changes to Figure 2........................................................................... 5 Changes to Minimum Setup Time to SYNC_CLK....................... 6
Changes to I/O_UPDATE Pulse Width Parameter and Changes to I/O Update/Profile[2:0] Timing Characteristics ...... 6
Minimum Profile Toggle Period Parameter in Table 1 ................ 7 Changes to TxENABLE/Data Setup Time (to PDCLK) and
Added XTAL_SEL Input Parameter in Table 1 ............................. 8 TxENABLE/Data Hold Time (to PDCLK) .................................... 6
Changes to Table 3 ..........................................................................11 Changes to Miscellaneous Timing Characteristics....................... 6
Changes to Figure 20 ......................................................................16 Changes to Table 3 .......................................................................... 10
Changes to Figure 22 ......................................................................17 Changes to Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,
Changes to Figure 23 ......................................................................18 and Figure 14 ................................................................................... 12
Changes to Figure 24 ......................................................................19 Changes to Figure 30 and Table 7 ................................................. 24
Changes to Figure 25 ......................................................................20 Changes to Automatic I/O Update Section ................................. 41
Changes to REF_CLK/REF_CLK Overview Section .................24 Added Table 16, Renumbered Sequentially ................................. 41
Changes to Crystal Driven REF_CLK/REF_CLK Section ........25 Changes to Figure 49 to Figure 53 ................................................ 43
Changes to PLL Lock Indication Section and Output Shift Added Power Supply Partitioning Section .................................. 46
Keying (OSK) Section .....................................................................27 Changes to General Serial I/O Operation Section ..................... 47
Changes to DRG Slope Control Section and Normal Ramp Changes to Table 17 ........................................................................ 49
Generation Section..........................................................................30 Changes to Table 19 ........................................................................ 56
Changes to Drover Pin Section .....................................................32 Changes to Table 20 ........................................................................ 57
Changes to Figure 43 ......................................................................35 Added Table 32 ................................................................................ 60
Changes to Figure 45 and Internal Profile Control Continuous
Waveform Timing Diagram Section .............................................38 5/2007—Revision 0: Initial Version
Changes to Figure 47 ......................................................................40

Rev. E | Page 3 of 64
AD9910 Data Sheet

GENERAL DESCRIPTION
The AD9910 is a direct digital synthesizer (DDS) featuring The AD9910 is controlled by programming its internal control
an integrated 14-bit DAC and supporting sample rates up to registers via a serial I/O port. The AD9910 includes an integrated
1 GSPS. The AD9910 employs an advanced, proprietary DDS static RAM to support various combinations of frequency, phase,
technology that provides a significant reduction in power con- and/or amplitude modulation. The AD9910 also supports a user
sumption without sacrificing performance. The DDS/DAC defined, digitally controlled, digital ramp mode of operation. In
combination forms a digitally programmable, high frequency, this mode, the frequency, phase, or amplitude can be varied
analog output synthesizer capable of generating a frequency linearly over time. For more advanced modulation functions, a
agile sinusoidal waveform at frequencies up to 400 MHz. high speed parallel data input port is included to enable direct
frequency, phase, amplitude, or polar modulation.
The user has access to the three signal control parameters that
control the DDS: frequency, phase, and amplitude. The DDS The AD9910 is specified to operate over the extended industrial
provides fast frequency hopping and frequency tuning resolu- temperature range (see the Absolute Maximum Ratings section
tion with its 32-bit accumulator. With a 1 GSPS sample rate, the for details).
tuning resolution is ~0.23 Hz. The DDS also enables fast phase
and amplitude switching capability.

RAM_SWP_OVR

AD9910
SERIAL I/O PORT

2
SDIO
SCLK
RAM 8 AUX
I/O_RESET DAC FSC DAC
8-BIT
CS DDS DAC_RSET
OUTPUT
SHIFT AMPLITUDE (A)
OSK
KEYING A Acos (ωt + θ) IOUT
DAC
PHASE (θ) 14-BIT
DRCTL 2 DATA θ INVERSE IOUT
DIGITAL ROUTE FREQUENCY (ω) SINC
DRHOLD RAMP AND ω Asin (ωt + θ)
GENERATOR FILTER
PARTITION
DROVER CONTROL
3 CLOCK REFCLK_OUT
PROFILE[2:0] PROGRAMMING

CLOCK MODE
REGISTERS SYSCLK ÷2
I/O_UPDATE
8
DAC FSC REF_CLK
16 INTERNAL CLOCK TIMING
AND CONTROL PLL REF_CLK
PARALLEL
INPUT 2

XTAL_SEL
TxENABLE PARALLEL DATA POWER- MULTICHIP
TIMING AND DOWN SYNCHRONIZATION
PDCLK CONTROL CONTROL
2
2
EXT_PWR_DWN

PLL_LOCK

PLL_LOOP_FILTER
SYNC_IN

MASTER_RESET
SYNC_CLK

SYNC_OUT
SYNC_SMP_ERR

06479-002

Figure 2. Detailed Block Diagram

Rev. E | Page 4 of 64
Data Sheet AD9910

SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) = 3.3 V ± 5%, DVDD_I/O (3.3 V) = 3.3 V ± 5%, T = 25°C, RSET = 10 kΩ,
IOUT = 20 mA, external reference clock frequency = 1000 MHz with reference clock (REFCLK) multiplier disabled, unless otherwise noted.

Table 1.
Parameter Conditions/Comments Min Typ Max Unit
REFCLK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled 60 1000 MHz
Enabled 3.2 60 MHz
Maximum REFCLK Input Divider Frequency Full temperature range 1500 1900 MHz
Minimum REFCLK Input Divider Frequency Full temperature range 25 35 MHz
External Crystal 25 MHz
Input Capacitance 3 pF
Input Impedance Differential 2.8 kΩ
Single-ended 1.4 kΩ
Duty Cycle REFCLK multiplier disabled 45 55 %
REFCLK multiplier enabled 40 60 %
REFCLK Input Level Single-ended 50 1000 mV p-p
Differential 100 2000 mV p-p
REFCLK MULTIPLIER VCO CHARACTERISTICS
VCO Gain (KV) @ Center Frequency VCO range Setting 0 429 MHz/V
VCO range Setting 1 500 MHz/V
VCO range Setting 2 555 MHz/V
VCO range Setting 3 750 MHz/V
VCO range Setting 4 789 MHz/V
VCO range Setting 51 850 MHz/V
REFCLK_OUT CHARACTERISTICS
Maximum Capacitive Load 20 pF
Maximum Frequency 25 MHz
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current 8.6 20 31.6 mA
Gain Error −10 +10 % FS
Output Offset 2.3 µA
Differential Nonlinearity 0.8 LSB
Integral Nonlinearity 1.5 LSB
Output Capacitance 5 pF
Residual Phase Noise @ 1 kHz offset, 20 MHz AOUT
REFCLK Multiplier Disabled −152 dBc/Hz
Enabled @ 20× −140 dBc/Hz
Enabled @ 100× −140 dBc/Hz
Voltage Compliance Range −0.5 +0.5 V
Wideband SFDR See the Typical Performance
Characteristics section
Narrow-Band SFDR
50.1 MHz Analog Output ±500 kHz –87 dBc
±125 kHz –87 dBc
±12.5 kHz –96 dBc
101.3 MHz Analog Output ±500 kHz –87 dBc
±125 kHz –87 dBc
±12.5 kHz –95 dBc

Rev. E | Page 5 of 64
AD9910 Data Sheet
Parameter Conditions/Comments Min Typ Max Unit
201.1 MHz Analog Output ±500 kHz –87 dBc
±125 kHz –87 dBc
±12.5 kHz –91 dBc
301.1 MHz Analog Output ±500 kHz –86 dBc
±125 kHz –86 dBc
±12.5 kHz –88 dBc
401.3 MHz Analog Output ±500 kHz –84 dBc
±125 kHz –84 dBc
±12.5 kHz –85 dBc
SERIAL PORT TIMING CHARACTERISTICS
Maximum SCLK Frequency 70 Mbps
Minimum SCLK Clock Pulse Width Low 4 ns
High 4 ns
Maximum SCLK Rise/Fall Time 2 ns
Minimum Data Setup Time to SCLK 5 ns
Minimum Data Hold Time to SCLK 0 ns
Maximum Data Valid Time in Read Mode 11 ns
I/O_UPDATE/PROFILE[2:0] TIMING
CHARACTERISTICS
Minimum Setup Time to SYNC_CLK 1.75 ns
Minimum Hold Time to SYNC_CLK 0 ns
I/O_UPDATE Pulse Width High >1 SYNC_CLK cycle
Minimum Profile Toggle Period 2 SYNC_CLK cycles
TxENABLE and 16-BIT PARALLEL (DATA) BUS TIMING
Maximum PDCLK Frequency 250 MHz
TxENABLE/Data Setup Time (to PDCLK) 1.75 ns
TxENABLE/Data Hold Time (to PDCLK) 0 ns
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time2
Fast Recovery 8 SYSCLK cycles3
Full Sleep Mode REFCLK multiplier enabled 1 ms
REFCLK multiplier disabled 150 μs
Minimum Reset Pulse Width High 5 SYSCLK cycles3
DATA LATENCY (PIPELINE DELAY)
Data Latency, Single Tone or Using Profiles
Frequency, Phase, Amplitude-to-DAC Output Matched latency enabled and OSK 91 SYSCLK cycles3
enabled
Frequency, Phase-to-DAC Output Matched latency enabled and OSK 79 SYSCLK cycles3
disabled
Matched latency disabled 79 SYSCLK cycles3
Amplitude-to-DAC Output Matched latency disabled 47 SYSCLK cycles3
Data Latency Using RAM Mode
Frequency, Phase-to-DAC Output Matched latency enabled/disabled 94 SYSCLK cycles3
Amplitude-to-DAC Output Matched latency enabled 106 SYSCLK cycles3
Matched latency disabled 58 SYSCLK cycles3
Data Latency, Sweep Mode
Frequency, Phase-to-DAC Output Matched latency enabled/disabled 91 SYSCLK cycles3
Amplitude-to-DAC Output Matched latency enabled 91 SYSCLK cycles3
Matched latency disabled 47 SYSCLK cycles3
Data Latency, 16-Bit Input Modulation Mode
Frequency, Phase-to-DAC Output Matched latency enabled 103 SYSCLK cycles3
Matched latency disabled 91 SYSCLK cycles3

Rev. E | Page 6 of 64
Data Sheet AD9910
Parameter Conditions/Comments Min Typ Max Unit
CMOS LOGIC INPUTS
Logic 1 Voltage 2.0 V
Logic 0 Voltage 0.8 V
Logic 1 Current 90 150 µA
Logic 0 Current 90 150 µA
Input Capacitance 2 pF
XTAL_SEL INPUT
Logic 1 Voltage 1.25 V
Logic 0 Voltage 0.6 V
Input Capacitance 2 pF
CMOS LOGIC OUTPUTS 1 mA load
Logic 1 Voltage 2.8 V
Logic 0 Voltage 0.4 V
POWER SUPPLY CURRENT
IAVDD (1.8 V) 110 mA
IAVDD (3.3 V) 29 mA
IDVDD (1.8 V) 222 mA
IDVDD (3.3 V) 11 mA
TOTAL POWER CONSUMPTION
Single Tone Mode 715 950 mW
Rapid Power-Down Mode 330 450 mW
Full Sleep Mode 19 40 mW
1
The gain value for VCO range Setting 5 is measured at 1000 MHz.
2
Wake-up time refers to the recovery time from a power-down state. The longest time required is for the reference clock multiplier PLL to relock to the reference. The
wake-up time assumes that the recommended PLL loop filter values are used.
3
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.

Rev. E | Page 7 of 64
AD9910 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. EQUIVALENT CIRCUITS
DAC OUTPUTS
Parameter Rating AVDD
AVDD (1.8V), DVDD (1.8V) Supplies 2V
AVDD (3.3V), DVDD_I/O (3.3V) Supplies 4V
Digital Input Voltage −0.7 V to +4 V
XTAL_SEL −0.7 V TO +2.2 V
Digital Output Current 5 mA
Storage Temperature Range −65°C to +150°C IOUT IOUT
Operating Temperature Range −40°C to +85°C
θJA 22°C/W MUST TERMINATE OUTPUTS TO AGND
FOR CURRENT FLOW. DO NOT EXCEED

06479-003
θJC 2.8°C/W THE OUTPUT VOLTAGE COMPLIANCE
RATING.
Maximum Junction Temperature 150°C
Figure 3. Equivalent Input Circuit
Lead Temperature (10 sec Soldering) 300°C
Stresses at or above those listed under Absolute Maximum DIGITAL INPUTS
DVDD_I/O
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond INPUT
the maximum operating conditions for extended periods may
affect product reliability.

AVOID OVERDRIVING DIGITAL INPUTS.

06479-055
FORWARD BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE ONTO POWER
PINS.

Figure 4. Equivalent Output Circuit

ESD CAUTION

Rev. E | Page 8 of 64
Data Sheet AD9910

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

94 REFCLK_OUT

92 AVDD (1.8V)

89 AVDD (1.8V)

83 AVDD (3.3V)

77 AVDD (3.3V)
76 AVDD (3.3V)
84 DAC_RSET
95 XTAL_SEL

91 REF_CLK
90 REF_CLK
96 AGND

88 AGND

85 AGND

82 AGND

79 AGND
78 AGND
81 IOUT
80 IOUT
100 NC
99 NC
98 NC
97 NC

93 NC

87 NC
86 NC
NC 1 75 AVDD (3.3V)
PIN 1
PLL_LOOP_FILTER 2 INDICATOR 74 AVDD (3.3V)
AVDD (1.8V) 3 73 AGND
AGND 4 72 NC
AGND 5 71 I/O_RESET
AVDD (1.8V) 6 70 CS
SYNC_IN+ 7 69 SCLK
SYNC_IN– 8 68 SDO
SYNC_OUT+ 9 67 SDIO
SYNC_OUT– 10 66 DVDD_I/O (3.3V)
DVDD_I/O (3.3V) 11 65 DGND
AD9910
SYNC_SMP_ERR 12 64 DVDD (1.8V)
TQFP-100 (E_PAD)
DGND 13 TOP VIEW 63 DRHOLD
MASTER_RESET 14 (Not to Scale) 62 DRCTL
DVDD_I/O (3.3V) 15 61 DROVER
DGND 16 60 OSK
DVDD (1.8V) 17 59 I/O_UPDATE
EXT_PWR_DWN 18 58 DGND
PLL_LOCK 19 57 DVDD (1.8V)
NC 20 56 DVDD_I/O (3.3V)
DVDD_I/O (3.3V) 21 55 SYNC_CLK
DGND 22 54 PROFILE0
DVDD (1.8V) 23 53 PROFILE1
RAM_SWP_OVR 24 52 PROFILE2
D15 25 51 DGND
DGND 29
D14 26
D13 27
DVDD_I/O (3.3V) 28

DVDD (1.8V) 30
D12 31

D10 33

D6 37

D4 39

F0 50
D11 32

D9 34

D7 36

D5 38

TxENABLE 41

D2 43
D1 44

DGND 46

D0 48
F1 49
D8 35

PDCLK 40

DVDD_I/O (3.3V) 45
D3 42

DVDD (1.8V) 47

06479-004
NOTES:
1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.
2. NC = NO CONNECT.

Figure 5. Pin Configuration

Rev. E | Page 9 of 64
AD9910 Data Sheet

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O1 Description
1, 20, 72, 86, 87, NC Not Connected. Allow device pins to float.
93, 97 to 100
2 PLL_LOOP_FILTER I PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for
details.
3, 6, 89, 92 AVDD (1.8V) I Analog Core VDD, 1.8 V Analog Supplies.
74 to 77, 83 AVDD (3.3V) I Analog DAC VDD, 3.3 V Analog Supplies.
17, 23, 30, 47, DVDD (1.8V) I Digital Core VDD, 1.8 V Digital Supplies.
57, 64
11, 15, 21, 28, 45, DVDD_I/O (3.3V) I Digital Input/Output VDD, 3.3 V Digital Supplies.
56, 66
4, 5, 73, 78, 79, 82, AGND I Analog Ground.
85, 88, 96
13, 16, 22, 29, 46, DGND I Digital Ground.
51, 58, 65
7 SYNC_IN+ I Synchronization Signal (LVDS), Digital Input (Rising Edge Active). The synchronization
signal from the external master to synchronize internal subclocks. See the Synchronization
of Multiple Devices section for details.
8 SYNC_IN− I Synchronization Signal (LVDS), Digital Input. The synchronization signal from the external
master to synchronize internal subclocks. See the Synchronization of Multiple Devices
section for details.
9 SYNC_OUT+ O Synchronization Signal (LVDS), Digital Output (Rising Edge Active). The synchronization
signal from the internal device subclocks to synchronize external slave devices. See the
Synchronization of Multiple Devices section for details.
10 SYNC_OUT− O Synchronization Signal (LVDS), Digital Output. The synchronization signal from the internal
device subclocks to synchronize external slave devices. See the Synchronization of Multiple
Devices section for details.
12 SYNC_SMP_ERR O Synchronization Sample Error, Digital Output (Active High). Sync sample error: a high on
this pin indicates that the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−.
14 MASTER_RESET I Master Reset, Digital Input (Active High). Master reset: clears all memory elements and sets
registers to default values.
18 EXT_PWR_DWN I External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down Control section for
further details. If unused, connect to ground.
19 PLL_LOCK O Clock Multiplier PLL Lock, Digital Output (Active High). A high on this pin indicates that the
Clock Multiplier PLL has acquired lock to the reference clock input.
24 RAM_SWP_OVR O RAM Sweep Over, Digital Output (Active High). A high on this pin indicates that the RAM
sweep profile has completed.
25 to 27, 31 to 39, D[15:0] I Parallel Input Bus (Active High).
42 to 44, 48
49, 50 F[1:0] I Modulation Format Pins. Digital input to determine the modulation format.
40 PDCLK O Parallel Data Clock. This is the digital output (clock). The parallel data clock provides a
timing signal for aligning data at the parallel inputs.
41 TxENABLE I Transmit Enable. Digital input (active high). In burst mode communications, a high on this
pin indicates new data for transmission. In continuous mode, this pin remains high.
52 to 54 PROFILE[2:0] I Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all I/O buffers to the corresponding registers. State changes should be
set up on the SYNC_CLK pin.
55 SYNC_CLK O Output Clock Divided-By-Four. A digital output (clock). Many of the digital inputs on the
chip, such as I/O_UPDATE and PROFILE[2:0], need to be set up on the rising edge of this signal.

Rev. E | Page 10 of 64
Data Sheet AD9910
Pin No. Mnemonic I/O1 Description
59 I/O_UPDATE I/O Input/Output Update. Digital input (active high). A high on this pin transfers the contents
of the I/O buffers to the corresponding internal registers.
60 OSK I Output Shift Keying. Digital input (active high). When the OSK features are placed in either
manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles
the multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero, a high sweeps the amplitude
up to the amplitude scale factor.
61 DROVER O Digital Ramp Over. Digital output (active high). This pin switches to Logic 1 whenever the
digital ramp generator reaches its programmed upper or lower limit.
62 DRCTL I Digital Ramp Control. Digital input (active high). This pin controls the slope polarity of the
digital ramp generator. See the Digital Ramp Generator (DRG) section for more details. If
not using the digital ramp generator, connect this pin to Logic 0.
63 DRHOLD I Digital Ramp Hold. Digital input (active high). This pin stalls the digital ramp generator in
its present state. See the Digital Ramp Generator (DRG) section for more details. If not
using a digital ramp generator, connect this pin to Logic 0.
67 SDIO I/O Serial Data Input/Output. Digital input/output (active high). This pin can be either unidirec-
tional or bidirectional (default), depending on the configuration settings. In bidirectional serial
port mode, this pin acts as the serial data input and output. In unidirectional mode, it is an
input only.
68 SDO O Serial Data Output. Digital output (active high). This pin is only active in unidirectional
serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is
not operational and should be left floating.
69 SCLK I Serial Data Clock. Digital clock (rising edge on write, falling edge on read). This pin provides
the serial data clock for the control data path. Write operations to the AD9910 use the
rising edge. Readback operations from the AD9910 use the falling edge.
70 CS I Chip Select. Digital input (active low). This pin allows the AD9910 to operate on a common
serial bus for the control data path. Bringing this pin low enables the AD9910 to detect
serial clock rising/falling edges. Bringing this pin high causes the AD9910 to ignore input
on the serial data pins.
71 I/O_RESET I Input/Output Reset. Digital input (active high). This pin can be used when a serial I/O
communication cycle fails (see the I/O_RESET—Input/Output Reset section for details).
When not used, connect this pin to ground.
80 IOUT O Open-Drain DAC Complementary Output Source. Analog output (current mode). Connect
through a 50 Ω resistor to AGND.
81 IOUT O Open-Drain DAC Output Source. Analog output (current mode). Connect through a 50 Ω
resistor to AGND.
84 DAC_RSET O Analog Reference Pin. This pin programs the DAC output full-scale reference current.
Attach a 10 kΩ resistor to AGND.
90 REF_CLK I Reference Clock Input. Analog input. When the internal oscillator is engaged, this pin can
be driven by either an external oscillator or connected to a crystal. See the REF_CLK/ Overview
section for more details.
91 REF_CLK I Reference Clock Input. Analog input. See the REF_CLK/ Overview section for more details.
94 REFCLK_OUT O Crystal Output. Analog output. See the REF_CLK/ Overview section for more details.
95 XTAL_SEL I Crystal Select (1.8 V Logic). Analog input (active high). Driving the XTAL_SEL pin high,
the AVDD (1.8V) pin enables the internal oscillator to be used with a crystal resonator.
If unused, connect it to AGND.
EPAD Exposed Paddle The EPAD should be soldered to ground.
(EPAD)
1
I = input, O = output.

Rev. E | Page 11 of 64
AD9910 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

–50 0

–10

–55 –20
SFDR WITHOUT PLL
–30
SFDR (dBc)

–60 –40

SFDR (dBc)
–50
SFDR WITH PLL
–65 –60
1
–70

–70 –80

06479-034

06479-035
–90

–75 –100
0 50 100 150 200 250 300 350 400 START 0Hz 50MHz/DIV STOP 500MHz
OUTPUT FREQUENCY (MHz)

Figure 6. Wideband SFDR vs. Output Frequency Figure 9. Wideband SFDR at 10 MHz, REFCLK = 1 GHz
(PLL with Reference Clock = 15.625 MHz × 64)
–45
0
LOW SUPPLY
–10
–50
HIGH SUPPLY –20

–55 –30
SFDR (dBc)

–40
SFDR (dBc)

–60
–50
1
–60
–65
–70

–70 –80
06479-046

06479-036
–90
–75
0 50 100 150 200 250 300 350 400 450 –100
START 0Hz 50MHz/DIV STOP 500MHz
OUTPUT FREQUENCY (MHz)

Figure 7. Wideband SFDR vs. Output Frequency and Supply (±5%), Figure 10. Wideband SFDR at 204 MHz, REFCLK = 1 GHz
REFCLK = 1 GHz

–50 0

–40°C –10

–55 +85°C –20

–30

–40
SFDR (dBc)

–60
SFDR (dBc)

–50 1

–65 –60

–70

–70 –80
06479-037
06479-047

–90

–75 –100
0 50 100 150 200 250 300 350 400 450 START 0Hz 50MHz/DIV STOP 500MHz
OUTPUT FREQUENCY (MHz)

Figure 8. Wideband SFDR vs. Output Frequency and Temperature, Figure 11. Wideband SFDR at 403 MHz, REFCLK = 1 GHz
REFCLK = 1 GHz

Rev. E | Page 12 of 64
Data Sheet AD9910
0 0

–12 –12

–24 –24

–36 –36

–48

SFDR (dBc)
–48
SFDR (dBc)

–60 –60

–72 –72

–84 –84
1 1
–96 –96

06479-040
–108

06479-038
–108

–120 –120
CENTER 10.32MHz 2.5kHz/DIV SPAN 25kHz CENTER 403.78MHz 2.5kHz/DIV SPAN 25kHz

Figure 12. Narrow-Band SFDR at 10.32 MHz, REFCLK = 1 GHz Figure 14. Narrow-Band SFDR at 403.78 MHz, REFCLK = 1 GHz

–90
0
fOUT = 397.8MHz
–12 –100

–24 –110
fOUT = 201.1MHz

MAGNITUDE (dBc/Hz)
–36
–120 fOUT = 98.6MHz
–48
SFDR (dBc)

–130
–60

–72 –140

–84 –150
1
–96
–160 fOUT = 20.1MHz

06479-042
06479-039

–108
–170
–120 10 100 1k 10k 100k 1M 10M 100M
CENTER 204.36MHz 2.5kHz/DIV SPAN 25kHz FREQUENCY OFFSET (Hz)

Figure 13. Narrow-Band SFDR at 204.36 MHz, REFCLK = 1 GHz Figure 15. Residual Phase Noise Plot, 1 GHz Operation with PLL Disabled

Rev. E | Page 13 of 64
AD9910 Data Sheet
–90 450
fOUT = 397.8MHz
400 DVDD 1.8V
–100
350

POWER DISSIPATION (mW)

fOUT = 201.1MHz
MAGNITUDE (dBc/ Hz)

–110
300

–120 250

200 AVDD 1.8V

–130

150
–140
100 AVDD 3.3V
fOUT = 20.1MHz
–150

06479-043

06479-045
50 DVDD 3.3V
fOUT = 98.6MHz
–160 0
10 100 1k 10k 100k 1M 10M 100M 400 500 600 700 800 900 1000
FREQUENCY OFFSET (Hz) SYSTEM CLOCK FREQUENCY (MHz)

Figure 16. Residual Phase Noise, Figure 18. Power Dissipation vs. System Clock Frequency (PLL Enabled)
1 GHz Operation Using a 50 MHz Reference Clock with 20× PLL Multiplier
450

400 DVDD 1.8V

350
POWER DISSIPATION (mW)

300

250

200
AVDD 1.8V
150

100 AVDD 3.3V

06479-044

50 DVDD 3.3V

0
100 200 300 400 500 600 700 800 900 1000
SYSTEM CLOCK FREQUENCY (MHz)

Figure 17. Power Dissipation vs. System Clock Frequency (PLL Disabled)

Rev. E | Page 14 of 64
Data Sheet AD9910

APPLICATION CIRCUITS
AD9510, AD9511, ADF4106

÷
PHASE CHARGE LOOP
PUMP VCO
REFERENCE COMPARATOR FILTER
÷

06479-056
REF_CLK
AD9910
LPF

Figure 19. DDS in PLL Feedback Locking to Reference, Offering Fine Frequency and Delay Adjust Tuning

AD9510
CLOCK DISTRIBUTOR
CLOCK WITH
SOURCE DELAY EQUALIZATION

REF_CLK
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
SYNC_OUT

C1
DATA S1
FPGA AD9910 A1
(MASTER)
SYNC_CLK

C2
DATA S2
FPGA AD9910 A2
(SLAVE 1)
SYNC_CLK

CENTRAL C3
CONTROL DATA S3
FPGA AD9910 A3
(SLAVE 2)
SYNC_CLK

C4
DATA S4
FPGA AD9910 A4
06479-058

(SLAVE 3)
SYNC_CLK
A_END

Figure 20. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and Synchronization Clock

PROGRAMMABLE 1 TO 32
DIVIDER AND DELAY ADJUST
CLOCK OUTPUT
SELECTION(S)

AD9515 LVPECL
CH 2 AD9514
AD9910 AD9513 n
LVDS
LPF CMOS
REFCLK AD9512
06479-057

n = DEPENDENT ON PRODUCT SELECTION.

Figure 21. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips

Rev. E | Page 15 of 64
AD9910 Data Sheet

THEORY OF OPERATION
• The AD9910 has four modes of operation. A separate output shift keying (OSK) function is also available.
• Single tone This function employs a separate digital linear ramp generator
• RAM modulation that only affects the amplitude parameter of the DDS. The OSK
• Digital ramp modulation function has priority over the other data sources that can drive
• Parallel data port modulation the DDS amplitude parameter. As such, no other data source
can drive the DDS amplitude when the OSK function is enabled.
The modes relate to the data source used to supply the DDS
Although the various modes (including the OSK function) are
with its signal control parameters: frequency, phase, or ampli-
described independently, they can be enabled simultaneously.
tude. The partitioning of the data into different combinations
This provides an unprecedented level of flexibility for generating
of frequency, phase, and amplitude is handled automatically
complex modulation schemes. However, to avoid multiple data
based on the mode and/or specific control bits.
sources from driving the same DDS signal control parameter,
In single tone mode, the DDS signal control parameters come the device has a built-in priority protocol (see Table 5 in the
directly from the programming registers associated with the Mode Priority section).
serial I/O port. In RAM modulation mode, the DDS signal
SINGLE TONE MODE
control parameters are stored in the internal RAM and played
back upon command. In digital ramp modulation mode, the In single tone mode, the DDS signal control parameters are
DDS signal control parameters are delivered by a digital ramp supplied directly from the programming registers. A profile is
generator. In parallel data port modulation mode, the DDS an independent register that contains the DDS signal control
signal control parameters are driven directly into the parallel port. parameters. Eight profile registers are available.

The various modulation modes generally operate on only one of Each profile is independently accessible. Use the three external
the DDS signal control parameters (two in the case of the polar profile pins (PROFILE[2:0]) to select the desired profile. A
modulation format). The unmodulated DDS signal control change in the state of the profile pins with the next rising edge
parameters are stored in their appropriate programming on SYNC_CLK updates the DDS with the parameters specified
registers and automatically route to the DDS based on the by the selected profile.
selected mode.
RAM_SWP_OVR

AD9910
SERIAL I/O PORT

2
SDIO
SCLK
RAM 8 AUX
I/O_RESET DAC FSC DAC
8-BIT
CS DDS DAC_RSET
OUTPUT
SHIFT AMPLITUDE (A)
OSK
KEYING A Acos (ωt + θ) IOUT
DAC
PHASE (θ) 14-BIT
DRCTL 2 DATA θ INVERSE IOUT
DIGITAL ROUTE FREQUENCY (ω) SINC
DRHOLD RAMP AND ω Asin (ωt + θ)
GENERATOR FILTER
DROVER PARTITION
CONTROL
3 CLOCK REFCLK_OUT
PROFILE[2:0] PROGRAMMING
CLOCK MODE

REGISTERS SYSCLK ÷2
I/O_UPDATE
8
DAC FSC REF_CLK
16 INTERNAL CLOCK TIMING
AND CONTROL PLL REF_CLK
PARALLEL
INPUT 2

XTAL_SEL
TxENABLE PARALLEL DATA POWER- MULTICHIP
TIMING AND DOWN SYNCHRONIZATION
PDCLK CONTROL CONTROL
2
2
EXT_PWR_DWN

PLL_LOCK

PLL_LOOP_FILTER
SYNC_IN

MASTER_RESET
SYNC_CLK

SYNC_OUT
SYNC_SMP_ERR

06479-005

Figure 22. Single Tone Mode

Rev. E | Page 16 of 64
Data Sheet AD9910
RAM MODULATION MODE The selection of the specific DDS signal control parameters that
serve as the destination for the RAM samples is also programmable
The RAM modulation mode (see Figure 23) is activated via the through eight independent RAM profile registers. Select a par-
RAM enable bit and assertion of the I/O_UPDATE pin (or a ticular profile using the three external profile pins (PROFILE[2:0]).
profile change). In this mode, the modulated DDS signal control A change in the state of the profile pins with the next rising
parameters are supplied directly from RAM. edge on SYNC_CLK activates the selected RAM profile.
The RAM consists of 32-bit words and is 1024 words deep. In RAM modulation mode, the ability to generate a time depen-
Coupled with a sophisticated internal state machine, the RAM dent amplitude, phase, or frequency signal enables modulation
provides a very flexible method for generating arbitrary, time of any one of the parameters controlling the DDS carrier signal.
dependent waveforms. A programmable timer controls the rate Furthermore, a polar modulation format is available that partitions
at which words are extracted from the RAM for delivery to the each RAM sample into a magnitude and phase component; 16 bits
DDS. Thus, the programmable timer establishes a sample rate at are allocated to phase and 14 bits are allocated to magnitude.
which 32-bit samples are supplied to the DDS.

RAM_SWP_OVR

AD9910
SERIAL I/O PORT

2
SDIO
SCLK
RAM 8 AUX
I/O_RESET DAC FSC DAC
8-BIT
CS DDS DAC_RSET
OUTPUT
SHIFT AMPLITUDE (A)
OSK
KEYING A Acos (ωt + θ) IOUT
DAC
PHASE (θ) 14-BIT
DRCTL 2 DATA θ INVERSE IOUT
DIGITAL ROUTE FREQUENCY (ω) SINC
DRHOLD RAMP ω
AND Asin (ωt + θ) FILTER
GENERATOR PARTITION
DROVER CONTROL
3 CLOCK REFCLK_OUT
PROFILE[2:0] PROGRAMMING

CLOCK MODE
REGISTERS SYSCLK ÷2
I/O_UPDATE
8
DAC FSC REF_CLK
16 INTERNAL CLOCK TIMING
AND CONTROL PLL REF_CLK
PARALLEL
INPUT 2

XTAL_SEL
TxENABLE PARALLEL DATA POWER- MULTICHIP
TIMING AND DOWN SYNCHRONIZATION
PDCLK CONTROL CONTROL
2
2
EXT_PWR_DWN

PLL_LOCK

PLL_LOOP_FILTER
SYNC_IN
SYNC_CLK

MASTER_RESET
SYNC_OUT
SYNC_SMP_ERR

06479-006

Figure 23. RAM Modulation Mode

Rev. E | Page 17 of 64
AD9910 Data Sheet
DIGITAL RAMP MODULATION MODE The ramp is digitally generated with 32-bit output resolution.
The 32-bit output of the DRG can be programmed to represent
In digital ramp modulation mode (see Figure 24), the modulated frequency, phase, or amplitude. When programmed to represent
DDS signal control parameter is supplied directly from the frequency, all 32 bits are used. However, when programmed to
digital ramp generator (DRG). The ramp generation parameters represent phase or amplitude, only the 16 MSBs or 14 MSBs,
are controlled through the serial I/O port. respectively, are used.
The ramp generation parameters allow the user to control both The ramp direction (rising or falling) is externally controlled by
the rising and falling slopes of the ramp. The upper and lower the DRCTL pin. An additional pin (DRHOLD) allows the user
boundaries of the ramp, the step size and step rate of the rising to suspend the ramp generator in its present state.
portion of the ramp, and the step size and step rate of the falling
portion of the ramp are all programmable.
RAM_SWP_OVR

AD9910
SERIAL I/O PORT

2
SDIO
SCLK
RAM 8 AUX
I/O_RESET DAC FSC DAC
8-BIT
CS DDS DAC_RSET
OUTPUT
SHIFT AMPLITUDE (A)
OSK Acos (ωt + θ)
KEYING A DAC IOUT
PHASE (θ) 14-BIT
DRCTL 2 DATA θ INVERSE IOUT
DIGITAL ROUTE FREQUENCY (ω) SINC
DRHOLD RAMP ω
AND Asin (ωt + θ) FILTER
GENERATOR PARTITION
DROVER CONTROL
3 CLOCK REFCLK_OUT
PROFILE[2:0] PROGRAMMING

CLOCK MODE
REGISTERS SYSCLK ÷2
I/O_UPDATE
8
DAC FSC REF_CLK
16 INTERNAL CLOCK TIMING
AND CONTROL PLL REF_CLK
PARALLEL
INPUT 2

XTAL_SEL
TxENABLE PARALLEL DATA POWER- MULTICHIP
TIMING AND DOWN SYNCHRONIZATION
PDCLK CONTROL CONTROL
2
2
EXT_PWR_DWN

PLL_LOCK

PLL_LOOP_FILTER
SYNC_IN

MASTER_RESET
SYNC_CLK

SYNC_OUT
SYNC_SMP_ERR

06479-007

Figure 24. Digital Ramp Modulation Mode

Rev. E | Page 18 of 64
Data Sheet AD9910
PARALLEL DATA PORT MODULATION MODE apply a weighting factor to the 16-bit data-word. In the default
state (0), the 16-bit data-word and the 32-bit word in the FTW
In parallel data port modulation mode (see Figure 25), the register are LSB aligned. Each increment in the value of the FM
modulated DDS signal control parameter(s) are supplied gain word shifts the 16-bit data-word to the left relative to the
directly from the 18-bit parallel data port. 32-bit word in the FTW register, increasing the influence of the
The data port is partitioned into two sections. The 16 MSBs make 16-bit data-word on the frequency defined by the FTW register
up a 16-bit data-word (D[15:0] pins) and the two LSBs make up by a factor of two. The FM gain word effectively controls the
a 2-bit destination word (F[1:0] pins). The destination word frequency range spanned by the data-word.
defines how the 16-bit data-word is applied to the DDS signal Parallel Data Clock (PDCLK)
control parameters. Table 4 defines the relationship between the
The AD9910 generates a clock signal on the PDCLK pin that
destination bits, the partitioning of the 16-bit data-word, and
runs at ¼ of the DAC sample rate (the sample rate of the par-
the destination of the data (in terms of the DDS signal control
allel data port). PDCLK serves as a data clock for the parallel
parameters). Formatting of the 16-bit data-word is unsigned
port. By default, each rising edge of PDCLK is used to latch the
binary, regardless of the destination.
18 bits of user-supplied data into the data port. The edge polarity
When the destination bits indicate that the data-word is destined can be changed through the PDCLK invert bit. Furthermore,
as a DDS frequency parameter, the 16-bit data-word serves as the PDCLK output signal can be switched off using the PDCLK
an offset to the 32-bit frequency tuning word in the FTW regis- enable bit. However, even though the output signal is switched
ter. This means that the 16-bit data-word must somehow be off, it continues to operate internally using the internal PDCLK
properly aligned with the 32-bit word in the FTW register. This timing to capture the data at the parallel port. Note that PDCLK
is accomplished by means of the 4-bit FM gain word in the is Logic 0 when disabled.
programming registers. The FM gain word allows the user to
RAM_SWP_OVR

AD9910
SERIAL I/O PORT

2
SDIO
SCLK
RAM 8 AUX
I/O_RESET DAC FSC DAC
8-BIT
CS DDS DAC_RSET
OUTPUT
SHIFT AMPLITUDE (A)
OSK A Acos (ωt + θ)
KEYING DAC IOUT
PHASE (θ) 14-BIT
DRCTL 2 DATA θ IOUT
DIGITAL INVERSE
ROUTE FREQUENCY (ω) SINC
DRHOLD RAMP AND ω Asin (ωt + θ) FILTER
GENERATOR PARTITION
DROVER CONTROL
3 CLOCK REFCLK_OUT
PROFILE[2:0] PROGRAMMING
REGISTERS ÷2
CLOCK MODE

I/O_UPDATE SYSCLK
8
DAC FSC REF_CLK
16 INTERNAL CLOCK TIMING
AND CONTROL PLL REF_CLK
PARALLEL
INPUT 2

XTAL_SEL
TxENABLE PARALLEL DATA POWER- MULTICHIP
TIMING AND DOWN SYNCHRONIZATION
PDCLK CONTROL CONTROL
2
2
EXT_PWR_DWN

PLL_LOCK

PLL_LOOP_FILTER
SYNC_IN
SYNC_CLK

SYNC_OUT

MASTER_RESET
SYNC_SMP_ERR

06479-008

Figure 25. Parallel Data Port Modulation Mode

Rev. E | Page 19 of 64
AD9910 Data Sheet

Table 4. Parallel Port Destination Bits

F[1:0] D[15:0] Parameter(s) Comments
00 D[15:2] 14-bit amplitude Amplitude scales from 0 to 1 − 2−14. D[1:0] are not used.
parameter (unsigned
integer)
01 D[15:0] 16-bit phase parameter Phase offset ranges from 0 to 2(1 − 2−16) radians.
(unsigned integer)
10 D[15:0] 32-bit frequency The alignment of the 16-bit data-word with the 32-bit frequency parameter is controlled
parameter (unsigned by a 4-bit FM gain word in the programming registers.
integer)
11 D[15:8] 8-bit amplitude The MSB of the data-word amplitude aligns with the MSB of the DDS 14-bit amplitude
(unsigned integer) parameter. The six LSBs of the DDS amplitude parameter are assigned from Bits[5:0] of the
ASF register. The resulting 14-bit word scales the amplitude from 0 to 1 − 2−14.
D[7:0] 8-bit phase (unsigned The MSB of the data-word phase aligns with the MSB of the 16-bit phase parameter of
integer) the DDS. The eight LSBs of the DDS phase parameter are assigned from Bits[7:0] of the
POW register. The resulting 16-bit word offsets the phase from 0 to 2(1 − 2−16) radians.

Transmit Enable (TxENABLE) Alternatively, instead of operating the TxENABLE pin as a gate,
The AD9910 also accepts a user-generated signal applied to the the user can drive the TxENABLE pin with a clock signal
TxENABLE pin that acts as a gate for the user-supplied data. By operating at the parallel port data rate. When driven by a clock
default, TxENABLE is considered true for Logic 1 and false for signal, the transition from the false to true state must meet the
Logic 0. However, the logical behavior of this pin can be reversed required setup and hold time on each cycle to ensure proper
using the TxENABLE invert bit. When TxENABLE is true, the operation. The TxENABLE and PDCLK timing is shown in
device latches data into the device on the expected edge of PDCLK Figure 26.
(based on the PDCLK invert bit). When TxENABLE is false,
TRUE
even though the PDCLK may continue to operate, the device TxENABLE
(BURST) FALSE
ignores the data supplied to the port. Furthermore, when the
TxENABLE pin is held false, the device internally clears the TxENABLE
(CLOCK)
16-bit data-words, or it retains the last value present on the data tDS tDH
port prior to TxENABLE switching to the false state (based on
PDCLK
the setting of the data assembler hold last value bit). tDH
tDS

06479-009
PARALLEL WORD1 WORD2 WORD3 WORD4 WORDN – 4 WORDN
DATA PORT

Figure 26. PDCLK and TxENABLE Timing Diagram

Rev. E | Page 20 of 64
Data Sheet AD9910
MODE PRIORITY drive the same DDS signal control parameter. To avoid contention,
The three different modulation modes generate frequency, the AD9910 has a built-in priority system. Table 5 summarizes
phase, and/or amplitude data destined for the DDS signal the priority for each of the DDS signal control parameters. The
control parameters. In addition, the OSK function generates rows of Table 5 list data sources for a particular DDS signal con-
amplitude data destined for the DDS. Each of these functions is trol parameter in descending order of precedence. For example,
independently invoked using the appropriate control bit via the if both the RAM and the parallel port are enabled and both are
serial I/O port. programmed for frequency as the destination, then the DDS
frequency parameter is driven by the RAM and not the parallel
The ability to activate each of these functions independently data port.
makes it possible to have multiple data sources attempting to

Table 5. Data Source Priority

DDS Signal Control Parameters
Frequency Phase Amplitude
Priority Data Source Conditions Data Source Conditions Data Source Conditions
Highest RAM RAM enabled and RAM RAM enabled and OSK generator OSK enabled (auto
Priority data destination is data destination is mode)
frequency phase or polar
DRG DRG enabled and DRG DRG enabled and ASF register OSK enabled
data destination is data destination is (manual mode)
frequency phase
Parallel data Parallel data port Parallel data port Parallel data port RAM RAM enabled and
port and FTW enabled and data enabled and data data destination is
register destination is destination is amplitude or polar
frequency phase
FTW register RAM enabled and Parallel data port Parallel data port DRG DRG enabled and
data destination is concatenated with enabled and data data destination is
phase, amplitude, the POW register destination is polar amplitude
or polar LSBs
FTW in active DRG enabled and POW register RAM enabled and Parallel data port Parallel data port
single tone data destination is destination is enabled and data
profile register phase or amplitude frequency or destination is
amplitude amplitude
FTW in active Parallel data port POW in active DRG enabled and Parallel data port Parallel data port
single tone enabled and data single tone profile data destination is concatenated with enabled and data
profile register destination is register frequency or the ASF register destination is
phase, amplitude, amplitude LSBs polar
or polar
FTW in active None POW in active Parallel data port ASF in active single Enable amplitude
single tone single tone profile enabled and data tone profile scale from single
profile register register destination is register tone profiles bit
frequency or (CFR2[24]) set
amplitude
Lowest POW in active None No amplitude None
Priority single tone profile scaling
register

Rev. E | Page 21 of 64
AD9910 Data Sheet

FUNCTIONAL BLOCK DETAIL

POW
DDS CORE 2π  16 
The direct digital synthesizer (DDS) block generates a reference  2 
Δθ =
POW
signal (sine or cosine based on CFR1[16], the select DDS sine 360 16 
output bit). The parameters of the reference signal (frequency,  2 
phase, and amplitude) are applied to the DDS at its frequency,
phase offset, and amplitude control inputs, as shown in Figure 27. where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the POW
DDS SIGNAL CONTROL PARAMETERS
value necessary to develop an arbitrary Δθ, solve the previous
AMPLITUDE 14 equation for POW and round the result (in a manner similar
CONTROL
PHASE
to that described previously for finding an arbitrary FTW).
16
OFFSET
CONTROL MSB ALIGNED The relative amplitude of the DDS signal can be digitally scaled
32-BIT
ACCUMULATOR 16 14 (relative to full scale) by means of a 14-bit amplitude scale
32
ANGLE-TO-
factor (ASF). The amplitude scale value is applied at the output
FREQUENCY 32 32
DQ
32 19 19 AMPLITUDE 14
CONVERSION
14 of the angle-to-amplitude conversion block internal to the DDS
CONTROL
R (MSBs)
(SINE OR
COSINE) TO DAC
core. The amplitude scale is given by
ASF
06479-010

DDS_CLK ACCUMULATOR
RESET 214
Amplitude Scale = (3)
ASF
Figure 27. DDS Block Diagram 20 log  14 
 2 
The output frequency (fOUT) of the AD9910 is controlled by the
frequency tuning word (FTW) at the frequency control input to where the upper quantity is amplitude expressed as a fraction of
the DDS. The relationship among fOUT, FTW, and fSYSCLK is given by full scale and the lower quantity is expressed in decibels relative
to full scale. To find the ASF value necessary for a particular
FTW
f OUT =  32  f SYSCLK (1) scale factor, solve Equation 3 for ASF and round the result (in
 2  a manner similar to that described previously for finding an
where FTW is a 32-bit integer ranging in value from 0 to arbitrary FTW).
2,147,483,647 (231 − 1), which represents the lower half of the When the AD9910 is programmed to modulate any of the DDS
full 32-bit range. This range constitutes frequencies from dc to signal control parameters, the maximum modulation sample
Nyquist (that is, ½ fSYSCLK). rate is ¼ fSYSCLK. This means that the modulation signal exhibits
The FTW required to generate a desired value of fOUT is found images at multiples of ¼ fSYSCLK. The impact of these images
by solving Equation 1 for FTW, as given in Equation 2. must be considered when using the device as a modulator.

  f  14-BIT DAC OUTPUT

FTW = round  2 32  OUT 
 (2)
 The AD9910 incorporates an integrated 14-bit, current output
  f SYSCLK 
DAC. The output current is delivered as a balanced signal using
where the round(x) function rounds the argument (the value of two outputs. The use of balanced outputs reduces the potential
x) to the nearest integer. This is required because the FTW is amount of common-mode noise present at the DAC output,
constrained to be an integer value. For example, for fOUT = offering the advantage of an increased signal-to-noise ratio. An
41 MHz and fSYSCLK = 122.88 MHz, then FTW = 1,433,053,867 external resistor (RSET) connected between the DAC_RSET pin
(0x556AAAAB). and AGND establishes the reference current. The full-scale
output current of the DAC (IOUT) is produced as a scaled version
Programming an FTW greater than 231 produces an aliased of the reference current (see the Auxiliary DAC section). The
image that appears at a frequency given by recommended value of RSET is 10 kΩ.
FTW
f OUT = 1 − 32  f SYSCLK (for FTW ≥ 231) Attention should be paid to the load termination to keep the
 2  output voltage within the specified compliance range; voltages
The relative phase of the DDS signal can be digitally controlled developed beyond this range cause excessive distortion and can
damage the DAC output circuitry.
by means of a 16-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by

Rev. E | Page 22 of 64
Data Sheet AD9910
Auxiliary DAC 1

An 8-bit auxiliary DAC controls the full-scale output current of SINC

the main DAC (IOUT). An 8-bit code word stored in the appropriate 0

register map location sets IOUT according to the following equation:

86.4  CODE  –1
IOUT = 1 + 

(dB)
RSET  96 
–2
where RSET is the value of the RSET resistor (in ohms) and CODE INVERSE
is the 8-bit value supplied to the auxiliary DAC (default is 127). –3
SINC

For example, with RSET = 10,000 Ω and CODE = 127, then IOUT =

06479-011
20.07 mA.
–4
0 0.1 0.2 0.3 0.4 0.5
INVERSE SINC FILTER FREQUENCY RELATIVE TO DAC SAMPLE RATE

The sampled carrier data stream is the input to the digital-to- Figure 28. Sinc and Inverse Sinc Responses
analog converter (DAC) integrated into the AD9910. The
–2.8
DAC output spectrum is shaped by the characteristic sin(x)/x
(or sinc) envelope, due to the intrinsic zero-order hold effect
associated with DAC generated signals. The sinc envelope
can be compensated for because its shape is well known. This –2.9
envelope restoration function is provided by the inverse sinc
filter preceding the DAC. The inverse sinc filter is implemented COMPENSATED RESPONSE

as a digital FIR filter. It has a response characteristic that very (dB)

nearly matches the inverse of the sinc envelope. The response –3.0
of the inverse sinc filter is shown in Figure 28 (with the sinc
envelope for comparison).

06479-012
The inverse sinc filter is enabled using CFR1[22]. The filter tap
–3.1
coefficients are given in Table 6. The filter operates by distorting 0 0.1 0.2 0.3 0.4 0.5

the data prior to its arrival at the DAC in such a way as to FREQUENCY RELATIVE TO DAC SAMPLE RATE

compensate for the sinc envelope that otherwise distorts the Figure 29. DAC Response with Inverse Sinc Compensation
spectrum.
CLOCK INPUT (REF_CLK/REF_CLK)
When the inverse sinc filter is enabled, it introduces a ~3.0 dB REF_CLK/REF_CLK Overview
insertion loss. The inverse sinc compensation is effective for output
The AD9910 supports a number of options for producing the
frequencies up to approximately 40% of the DAC sample rate.
internal SYSCLK signal (that is, the DAC sample clock) via the
Table 6. Inverse Sinc Filter Tap Coefficients REF_CLK/REF_CLK input pins. The REF_CLK input can be
Tap No. Tap Value driven directly from a differential or single-ended source, or it
1, 7 −35 can accept a crystal connected across the two input pins. There
2, 6 +134 is also an internal phase-locked loop (PLL) multiplier that can
3, 5 −562 be independently enabled. A block diagram of the REF_CLK
4 +6729 functionality is shown in Figure 30. The various input configu-
rations are controlled by the XTAL_SEL pin and the control bits
In Figure 28, the sinc envelope introduces a frequency dependent in the CFR3 register. Figure 30 also shows how the CFR3 control
attenuation that can be as much as 4 dB at the Nyquist frequency bits are associated with specific functional blocks.
(½ of the DAC sample rate). Without the inverse sinc filter, the
DAC output suffers from the frequency dependent droop of
the sinc envelope. The inverse sinc filter effectively flattens the
droop to within ±0.05 dB, as shown in Figure 29, which shows
the corrected sinc response with the inverse sinc filter enabled.

Rev. E | Page 23 of 64
AD9910 Data Sheet
XTAL_SEL PLL_LOOP_FILTER
95 2
DRV0 90 REF_CLK
CFR3
[29:28]
2 XTAL
REFCLK_OUT 94 PLL ENABLE
CFR3 91 REF_CLK
REFCLK [8]
INPUT 39pF 39pF

06479-014
SELECT
LOGIC

ENABLE PLL_LOOP_FILTER
1
IN OUT 1
Figure 31. Crystal Connection Diagram
0 PLL
0
REF_CLK 90
CHARGE VCO SYSCLK Direct Driven REF_CLK/REF_CLK
PUMP DIVIDE SELECT

2 7 3 When driving the REF_CLK/REF_CLK inputs directly from a

REF_CLK 91
ICP N VCO SEL signal source, either single-ended or differential signals can be
CFR3 CFR3 CFR3
1
[21:19] [7:1] [26:24] used. With a differential signal source, the REF_CLK/REF_CLK
÷2 0 pins are driven with complementary signals and ac-coupled with
0.1 µF capacitors. With a single-ended signal source, either a
REFCLK REFCLK 06479-013 single-ended-to-differential conversion can be employed or the
INPUT DIVIDER
RESETB
INPUT DIVIDER BYPASS
CFR3[15] REF_CLK input can be driven single-ended directly. In either
CFR3[14]
case, 0.1 µF capacitors are used to ac couple both REF_CLK/
Figure 30. REF_CLK Block Diagram REF_CLK pins to avoid disturbing the internal dc bias voltage
The PLL enable bit is used to choose between the PLL path or of ~1.35 V. See Figure 32 for more details.
the direct input path. When the direct input path is selected, The REF_CLK/REF_CLK input resistance is ~2.5 kΩ differential
the REF_CLK/REF_CLK pins must be driven by an external (~1.2 kΩ single-ended). Most signal sources have relatively low
signal source (single-ended or differential). Input frequencies output impedances. The REF_CLK/REF_CLK input resistance
up to 2 GHz are supported. For input frequencies greater than is relatively high; therefore, its effect on the termination impedance
1 GHz, the input divider must be enabled for proper operation is negligible and can usually be chosen to be the same as the
of the device. output impedance of the signal source. The bottom two examples
When the PLL is enabled, a buffered clock signal is available at in Figure 32 assume a signal source with a 50 Ω output
the REFCLK_OUT pin. This clock signal is the same frequency impedance.
as the REF_CLK input. This is especially useful when a crystal 0.1µF

is connected because it gives the user a replica of the crystal PECL, 90 REF_CLK
DIFFERENTIAL SOURCE, LVPECL,
clock for driving other external devices. The REFCLK_OUT has DIFFERENTIAL INPUT OR
LVDS
TERMINATION
programmable drive capability. This is controlled by two bits, as DRIVER
91 REF_CLK
listed in Table 7. 0.1µF

Table 7. REFCLK_OUT Buffer Control BALUN 0.1µF

DRV0 Bits (CFR3[29:28]) REFCLK_OUT Buffer (1:1) 90 REF_CLK

00 Disabled (tristate) SINGLE-ENDED SOURCE,

50Ω
DIFFERENTIAL INPUT
01 Low output current
91 REF_CLK
10 Medium output current 0.1µF
11 High output current
0.1µF

Crystal Driven REF_CLK/REF_CLK 90 REF_CLK

SINGLE-ENDED SOURCE,
50Ω
When using a crystal at the REF_CLK/REF_CLK input, the SINGLE-ENDED INPUT

resonant frequency should be approximately 25 MHz. Figure 31 91 REF_CLK

06479-015

0.1µF
shows the recommended circuit configuration. The internal
oscillator works with fundamental mode crystals only. Crystal
operation is enabled by a Logic 1 (1.8 V logic required) on the Figure 32. Direct Connection Diagram
XTAL_SEL pin. Phase-Locked Loop (PLL) Multiplier
An internal phase-locked loop (PLL) provides the option to use
a reference clock frequency that is significantly lower than the
system clock frequency. The PLL supports a wide range of
programmable frequency multiplication factors (12× to 127×)
Rev. E | Page 24 of 64
Data Sheet AD9910
as well as a programmable charge pump current and external
fLOW = 820
loop filter components (connected via the PLL_LOOP_FILTER VCO5 fHIGH = 1150
pin). These features add an extra layer of flexibility to the PLL,
fLOW = 700
allowing optimization of phase noise performance and VCO4 fHIGH = 950
flexibility in frequency plan development. The PLL is also
fLOW = 600
equipped with a PLL_LOCK pin. VCO3 fHIGH = 880

The PLL output frequency range (fSYSCLK) is constrained to the VCO2

fLOW = 500
fHIGH = 700
range of 420 MHz ≤ fSYSCLK ≤ 1 GHz by the internal VCO. In
fLOW = 420
addition, the user must program the VCO to one of six operating VCO1 fHIGH = 590
ranges such that fSYSCLK falls within the specified range. Figure 33
fLOW = 370

06479-060
and Figure 34 summarize these VCO ranges. VCO0 fHIGH = 510

Figure 33 shows the boundaries of the VCO frequency ranges 335 435 535 635 735 835 935 1035 1135
(MHz)
over the full range of temperature and supply voltage variation
Figure 34. Typical VCO Ranges
for all devices from the available population. The implication is
that multiple devices chosen at random from the population and
Table 8. VCO Range Bit Settings
operated under widely varying conditions may require different
values to be programmed into CFR3[26:24] to operate at the VCO SEL Bits (CFR3[26:24]) VCO Range
same frequency. For example, Part A chosen randomly from the 000 VCO0
population, operating at an ambient temperature of −10°C with 001 VCO1
a system clock frequency of 900 MHz may require CFR3[26:24] to 010 VCO2
be set to 100b, whereas Part B chosen randomly from the 011 VCO3
population, operating at an ambient temperature of 90°C with a 100 VCO4
system clock frequency of 900 MHz may require CFR3[26:24] 101 VCO5
to be set to 101b. If a frequency plan is chosen such that the 110 PLL bypassed
system clock frequency operates within one set of boundaries 111 PLL bypassed
(as shown in Figure 33), the required value in CFR3[26:24] is
PLL Charge Pump
consistent from part to part.
The charge pump current (ICP) is programmable to provide the
Figure 34 shows the boundaries of the VCO frequency ranges user with additional flexibility to optimize the PLL performance.
over the full range of temperature and supply voltage variation Table 9 lists the bit settings vs. the nominal charge pump current.
for an individual device selected from the population. Figure 34
shows that the VCO frequency ranges for a single device always Table 9. PLL Charge Pump Current
overlap when operated over the full range of conditions. ICP Bits (CFR3[21:19]) Charge Pump Current, ICP (μA)
000 212
If a user wants to retain a single default value for CFR3[26:24],
001 237
a frequency that falls into one of the ranges found in Figure 33
010 262
should be selected. Additionally, for any given individual device,
011 287
the VCO frequency ranges overlap, meaning that any given
100 312
device exhibits no gaps in its frequency coverage across VCO
101 337
ranges over the full range of conditions.
110 363
VCO5 fLOW = 920 111 387
fHIGH = 1030

VCO4 fLOW = 760

fHIGH = 875

VCO3 fLOW = 650

fHIGH = 790

VCO2
fLOW = 530
fHIGH = 615

VCO1 fLOW = 455

fHIGH = 530
06479-059

VCO0 fLOW = 400

fHIGH = 460
395 495 595 695 795 895 995
(MHz)

Figure 33. VCO Ranges Including Atypical Wafer Process Skew

Rev. E | Page 25 of 64
AD9910 Data Sheet
External PLL Loop Filter Components PLL LOCK INDICATION
The PLL_LOOP_FILTER pin provides a connection interface to When the PLL is in use, the PLL_LOCK pin provides an active
attach the external loop filter components. The ability to use high indication that the PLL has locked to the REFCLK input
custom loop filter components gives the user more flexibility to signal. Note that the PLL_LOCK pin is a latched output. When the
optimize the PLL performance. The PLL and external loop filter PLL is bypassed, the pin may remain at Logic 1. The PLL_LOCK
components are shown in Figure 35. pin can be cleared by setting the PFD reset bit. The PFD reset
AVDD bit must be cleared for normal operation.

C1
OUTPUT SHIFT KEYING (OSK)
The OSK function (see Figure 36) allows the user to control the
C2
R1
output signal amplitude of the DDS. Both a manual and an
automatic mode are available under program control. The
PLL_LOOP_FILTER amplitude data generated by the OSK block has priority over
2
any other functional block that is programmed to deliver
REFCLK PLL amplitude data to the DDS. Therefore, the OSK data source,
PLL IN when enabled, overrides all other amplitude data sources.
PFD CP VCO PLL OUT OSK
60
06479-016

÷N

OSK ENABLE
Figure 35. REFCLK PLL External Loop Filter
AUTO OSK ENABLE
In the prevailing literature, this configuration yields a third- MANUAL OSK EXTERNAL
order, Type II PLL. To calculate the loop filter component LOAD ARR AT I/O_UPDATE
values, begin with the feedback divider value (N), the gain of 16 OSK
14 TO DDS
AMPLITUDE
AMPLITUDE RAMP RATE CONTROLLER
the phase detector (KD), and the gain of the VCO (KV) based on (ASF[31:16]) CONTROL
PARAMETER
the programmed VCO SEL bit settings (see Table 1 for KV). The AMPLITUDE SCALE FACTOR 14
loop filter component values depend on the desired open-loop (ASF[15:2])

bandwidth (fOL) and phase margin (φ), as follows: AMPLITUDE STEP SIZE
2
(ASF[1:0])
πNfOL  1 
R1 = 1 +  (4)
 sin(φ ) 

06479-017
K D KV   DDS CLOCK
K K tan(φ ) Figure 36. OSK Block Diagram
C1 = D V (5)
2N (πfOL ) 2
The operation of the OSK function is governed by two CFR1
K D K V  1 − sin(φ )  register bits (OSK enable and select auto OSK), the external
C2 =   (6)
N (2πfOL )2  cos(φ )  OSK pin, and the entire 32 bits of the ASF register. The primary
control for the OSK block is the OSK Enable bit. When the OSK
where: function is disabled, the OSK input controls are ignored and the
KD is equal to the programmed value of ICP. internal clocks shut down.
KV is taken from Table 1.
When the OSK function is enabled, automatic or manual
Ensure that proper units are used for the variables in Equation 4 operation is selected using the select auto OSK bit. A Logic 0
through Equation 6. ICP must be in amps, not microamps (μA) indicates manual mode (default).
as appears in Table 9; KV must be in hertz per volts (Hz/V), not
megahertz per volts (MHz/V) as listed in Table 1; the loop Manual OSK
bandwidth (fOL) must be in hertz (Hz); the phase margin (φ) In manual mode, output amplitude is varied by successive write
must be in radians. operations to the amplitude scale factor portion of the ASF
register. The rate at which amplitude changes can be applied to
For example, suppose the PLL is programmed such that ICP = the output signal is limited by the speed of the serial I/O port.
287 μA, KV = 625 MHz/V, and N = 25. If the desired loop In manual mode, the OSK pin functionality depends on the
bandwidth and phase margin are 50 kHz and 45°, respectively, state of the manual OSK external control bit. When the OSK
then the loop filter component values are R1 = 52.85 Ω, C1 = pin is Logic 0, the output amplitude is forced to 0; otherwise,
145.4 nF, and C2 = 30.11 nF. the output amplitude is set by the amplitude scale factor value.

Rev. E | Page 26 of 64
Data Sheet AD9910
Automatic OSK Table 10. OSK Amplitude Step Size
In automatic mode, the OSK function automatically generates a Amplitude Step Size Bits (ASF[1:0]) Amplitude Step Size
linear amplitude vs. time profile (or amplitude ramp). The ampli- 00 1
tude ramp is controlled via three parameters: the maximum 01 2
amplitude scale factor, the amplitude step size, and the time 10 4
interval between steps. The amplitude ramp parameters reside 11 8
in the 32-bit ASF register and are programmed via the serial
As mentioned previously, a 16-bit programmable timer controls
I/O port. The time interval between amplitude steps is set via
the step interval. Normally, this timer is loaded with the pro-
the 16-bit amplitude ramp rate portion of the ASF register
grammed timing value whenever the timer expires, initiating a
(Bits[31:16]). The maximum amplitude scale factor is set via the
new timing cycle. However, there are three events that can cause
14-bit amplitude scale factor in the ASF register (Bits[15:2]). The
reloading of the timer to have its timing value reloaded prior to
amplitude step size is set via the 2-bit amplitude step size
the timer expiring. One such event occurs when the select auto
portion of the ASF register (Bits[1:0]). Additionally, the
OSK bit transitions from cleared to set, followed by an I/O update.
direction of the ramp (positive or negative slope) is controlled
A second such event is a change of state in the OSK pin. The
by the external OSK pin.
third is dependent on the status of the load ARR @ I/O update
The step interval is controlled by a 16-bit programmable timer bit. If this bit is cleared, then no action occurs; otherwise, when
that is clocked at a rate of ¼ fSYSCLK. The period of the timer sets the I/O_UPDATE pin is asserted (or a profile change occurs),
the time interval between amplitude steps. The step time interval the timer is reset to its initial starting point.
(Δt) is given by
DIGITAL RAMP GENERATOR (DRG)
4M
Δt  DRG Overview
f SYSCLK
To sweep phase, frequency, or amplitude from a defined start
where M is the 16-bit number stored in the amplitude ramp rate point to a defined endpoint, a completely digital, digital ramp
(ARR) portion of the ASF register. For example, if fSYSCLK = generator is included in the AD9910. The DRG makes use of
750 MHz and M = 23218 (0x5AB2), then Δt ≈ 123.8293 μs. nine control register bits, three external pins, two 64-bit
registers, and one 32-bit register (see Figure 37).
The output of the OSK function is a 14-bit unsigned data bus

DROVER

DRHOLD
that controls the amplitude parameter of the DDS (as long as

DRCTL
the OSK enable bit is set). When the OSK pin is set, the OSK
output value starts at 0 (zero) and increments by the pro- 62 61 63

grammed amplitude step size until it reaches the programmed

maximum amplitude value. When the OSK pin is cleared, the DIGITAL RAMP ENABLE
2
OSK output starts at its present value and decrements by the DIGITAL RAMP DESTINATION
programmed amplitude step size until it reaches 0 (zero). 2
DIGITAL RAMP NO-DWELL

The OSK output does not necessarily attain the maximum DROVER PIN ACTIVE
LOAD LRR AT I/O_UPDATE
amplitude value if the OSK pin is switched to Logic 0 before the DIGITAL TO DDS
CLEAR DIGITAL 32
RAMP SIGNAL
maximum value is reached. Nor does the OSK output necessarily RAMP ACCUMULATOR
GENERATOR CONTROL
AUTOCLEAR DIGITAL PARAMETER
reach a value of 0 if the OSK pin is switched to Logic 1 before RAMP ACCUMULATOR
64
the 0 value is reached. DIGITAL RAMP LIMIT REGISTER

The OSK output is initialized to 0 (zero) at power-up and reset DIGITAL RAMP STEP REGISTER
64

whenever the OSK enable bit or the select auto OSK bit is cleared.
32
DIGITAL RAMP RATE REGISTER
The amplitude step size of the OSK output is set by the amplitude
06479-018

step size bits in the ASF register according to Table 10. The step
DDS CLOCK
size refers to the LSB weight of the 14-bit OSK output. Regardless
Figure 37. Digital Ramp Block Diagram
of the programmed step size, the OSK output does not exceed
the maximum amplitude value programmed into the ASF
register.

Rev. E | Page 27 of 64
AD9910 Data Sheet
The primary control for the DRG is the digital ramp enable bit. The ramp characteristics of the DRG are fully programmable. This
When disabled, the other DRG input controls are ignored and the includes the upper and lower ramp limits, and independent control
internal clocks are shut down to conserve power. of the step size and step rate for both the positive and negative slope
The output of the DRG is a 32-bit unsigned data bus that can be characteristics of the ramp. A detailed block diagram of the DRG is
routed to any one of the three DDS signal control parameters, as shown in Figure 38.
controlled by the two digital ramp destination bits in Control The direction of the ramping function is controlled by the
Function Register 2 according to Table 11. The 32-bit output DRCTL pin. A Logic 0 on this pin causes the DRG to ramp
bus is MSB-aligned with the 32-bit frequency parameter, the with a negative slope, whereas a Logic 1 causes the DRG to
16-bit phase parameter, or the 14-bit amplitude parameter, as ramp with a positive slope.
defined by the destination bits. When the destination is phase
or amplitude, the unused LSBs are ignored. The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is set to Logic 1, the DRG is stalled at its last
Table 11. Digital Ramp Destination state; otherwise, the DRG operates normally.
Digital Ramp DDS Signal
Destination Bits Control Bits Assigned to The DDS signal control parameters that are not the destination of
(CFR2[21:20]) Parameter DDS Parameter the DRG are taken from the active profile.
00 Frequency 31:0
01 Phase 31:16
1x1 Amplitude 31:18
1
x = Don’t care.

DIGITAL RAMP ACCUMULATOR

32
DECREMENT STEP SIZE 0 32 32
32
INCREMENT STEP SIZE 1
TO DDS
32 32 SIGNAL
D Q LIMIT CONTROL CONTROL
PARAMETER
DRCTL 62
R 32 32

UPPER LOWER
LIMIT LIMIT
16
NEGATIVE SLOPE RATE 0 16
16
POSITIVE SLOPE RATE 1 2
NO-DWELL NO DWELL
ACCUMULATOR CONTROL
RESET
CONTROL CLEAR DIGITAL RAMP ACCUMULATOR
LOGIC
LOAD
PRESET . ACC
AUTOCLEAR DIGITAL RAMP
LOAD LRR AT I/O_UPDATE CONTROL LOAD
LOGIC
Q
DIGITAL
DRHOLD 63
06479-019

RAMP
DDS CLOCK TIMER

Figure 38. Digital Ramp Generator Detail

Rev. E | Page 28 of 64
Data Sheet AD9910
DRG Slope Control As described previously, the step interval is controlled by a
16-bit programmable timer. There are three events that can
The core of the DRG is a 32-bit accumulator clocked by a
cause this timer to be reloaded prior to its expiration.
programmable timer. The time base for the timer is the DDS
clock, which operates at ¼ fSYSCLK. The timer establishes the One event occurs when the digital ramp enable bit transitions
interval between successive updates of the accumulator. The from cleared to set, followed by an I/O update. A second event
positive (+Δt) and negative (−Δt) slope step intervals are is a change of state in the DRCTL pin. The third event is enabled
independently programmable as given by using the load LRR @ I/O update bit (see the Register Map and Bit
4P Descriptions section for details).
+ Δt =
f SYSCLK DRG Limit Control
4N The ramp accumulator is followed by limit control logic that
− Δt =
f SYSCLK enforces an upper and lower boundary on the output of the
ramp generator. Under no circumstances does the output of the
where P and N are the two 16-bit values stored in the 32-bit digital DRG exceed the programmed limit values while the DRG is
ramp rate register and control the step interval. N defines the step enabled. The limits are set through the 64-bit digital ramp limit
interval of the negative slope portion of the ramp. P defines the step register. Note that the upper limit value must be greater than the
interval of the positive slope portion of the ramp. lower limit value to ensure normal operation.

The step size of the positive (STEPP) and negative (STEPN) slope DRG Accumulator Clear
portions of the ramp are 32-bit values programmed into the 64-bit The ramp accumulator can be cleared (that is, reset to 0) under
digital ramp step size register. Program each of the step sizes as an program control. When the ramp accumulator is cleared, it forces
unsigned integer (the hardware automatically interprets STEPN as the DRG output to the lower limit programmed into the digital
a negative value). The relationship between the 32-bit step size ramp limit register.
values and actual units of frequency, phase, or amplitude depend
on the digital ramp destination bits. Calculate the actual frequency, With the limit control block embedded in the feedback path of the
phase, or amplitude step size by substituting STEPN or STEPP accumulator, resetting the accumulator is equivalent to presetting it
for M in the following equations as required: to the lower limit value.
M Normal Ramp Generation
Frequency Step =  32  f SYSCLK
2  Normal ramp generation implies that both no-dwell bits are
πM cleared (see the No-Dwell Ramp Generation section for details).
Phase Step = (radians) In Figure 39, a sample ramp waveform is depicted with the
231
required control signals. The top trace is the DRG output.
45M
Phase Step = (degrees) The next trace down is the status of the DROVER output pin
229 (assuming that the DROVER pin active bit is set). The remaining
M traces are control bits and control pins. The pertinent ramp
Amplitude Step =  32  I FS
2  parameters are also identified (upper and lower limits plus step
size and Δt for the positive and negative slopes). Along the
Note that the frequency units are the same as those used to bottom, circled numbers identify specific events. These events
represent fSYSCLK (MHz, for example). The amplitude units are are referred to by number (Event 1 and so on) in the following
the same as those used to represent IFS, the full-scale output paragraphs.
current of the DAC (mA, for example).
In this particular example, the positive and negative slopes of
The phase and amplitude step size equations yield the average the ramp are different to demonstrate the flexibility of the DRG.
step size. Although the step size accumulates with 32-bit precision, The parameters of both slopes can be programmed to make the
the phase or amplitude destination exhibits only 16 or 14 bits, positive and negative slopes the same.
respectively. Therefore, at the destination, the actual phase or
amplitude step is the accumulated 32-bit value truncated to 16
or 14 bits, respectively.

Rev. E | Page 29 of 64
AD9910 Data Sheet
P DDS CLOCK CYCLES N DDS CLOCK CYCLES 1 DDS CLOCK CYCLE
NEGATIVE
STEP SIZE
POSITIVE
STEP SIZE
+∆t –∆t UPPER LIMIT

DRG OUTPUT

LOWER LIMIT
DROVER

DIGITAL RAMP ENABLE

DRCTL

RELEASE
CLEAR

CLEAR
AUTO
DRHOLD

CLEAR DIGITAL
RAMP ACCUMULATOR

AUTOCLEAR DIGITAL
RAMP ACCUMULATOR

I/O_UPDATE

1 2 3 4 5 6 7 8 9 11 13
10 12

06479-020
Figure 39. Normal Ramp Generation

Event 1—The digital ramp enable bit is set, which has no effect Event 7—DRHOLD transitions to a Logic 0, releasing the ramp
on the DRG output because the bit is not effective until an I/O accumulator and reinstating the previous positive slope profile.
update.
Event 8—The clear digital ramp accumulator bit is set, which
Event 2—An I/O update registers the enable bit. If DRCTL = 1 has no effect on the DRG because the bit is not effective until an
is in effect at this time (the gray portion of the DRCTL trace), I/O update is issued.
then the DRG output immediately begins a positive slope (the
gray portion of the DRG output trace). Otherwise, if DRCTL = Event 9—An I/O update registers that the clear digital ramp
0, the DRG output is initialized to the lower limit. accumulator bit is set, resetting the ramp accumulator and
forcing the DRG output to the programmed lower limit. The
Event 3—DRCTL transitions to a Logic 1 to initiate a positive DRG output remains at the lower limit until the clear condition
slope at the DRG output. In this example, the DRCTL pin is is removed.
held long enough to cause the DRG to reach its programmed
upper limit. The DRG remains at the upper limit until the ramp Event 10—The clear digital ramp accumulator bit is cleared,
accumulator is cleared, DRCTL = 0, or the upper limit is which has no effect on the DRG output because the bit is not
reprogrammed to a higher value. In the last case, the DRG effective until an I/O update is issued.
immediately resumes its previous positive slope profile. Event 11—An I/O update registers that the clear digital ramp
Event 4—DRCTL transitions to a Logic 0 to initiate a negative accumulator bit is cleared, releasing the ramp accumulator, and
slope at the DRG output. In this example, the DRCTL pin is the previous positive slope profile restarts.
held long enough to cause the DRG to reach its programmed Event 12—The autoclear digital ramp accumulator bit is set,
lower limit. The DRG remains at the lower limit until DRCTL = 1, which has no effect on the DRG output because the bit is not
or until the lower limit is reprogrammed to a lower value. In the effective until an I/O update is issued.
latter case, the DRG immediately resumes its previous negative
slope profile. Event 13—An I/O update registers that the autoclear digital
ramp accumulator bit is set, resetting the ramp accumulator.
Event 5—DRCTL transitions to a Logic 1 for the second time, However, with an automatic clear, the ramp accumulator is only
initiating a second positive slope. held reset for a single DDS clock cycle. This forces the DRG
Event 6—The positive slope profile is interrupted by DRHOLD output to the lower limit, but the ramp accumulator is immedi-
transitioning to a Logic 1. This stalls the ramp accumulator and ately made available for normal operation. In this example, the
freezes the DRG output at its last value. DRCTL pin remains a Logic 1; therefore, the DRG output
restarts the previous positive ramp profile.

Rev. E | Page 30 of 64
Data Sheet AD9910
No-Dwell Ramp Generation P DDS CLOCK CYCLES

The two no-dwell bits in Control Function Register 2 add to the

POSITIVE
flexibility of the DRG capabilities. During normal ramp generation, STEP SIZE
+Δt
when the DRG output reaches the programmed upper or lower UPPER LIMIT

limit, it simply remains at the limit until the operating parameters DRG OUTPUT

dictate otherwise. However, during no-dwell operation, the DRG LOWER LIMIT
output does not necessarily remain at the limit. For example, if the DROVER
digital ramp no-dwell high bit is set when the DRG reaches the
upper limit, it automatically (and immediately) snaps to the lower DRCTL

limit (that is, it does not ramp back to the lower limit; it jumps to

06479-021
1 2 3 4 5 6 7 8
the lower limit). Likewise, when the digital ramp no-dwell low bit is
set, and the DRG reaches the lower limit, it automatically (and Figure 40. No-Dwell High Ramp Generation
immediately) snaps to the upper limit.
The circled numbers in Figure 40 indicate specific events, which
During no-dwell operation, the DRCTL pin is monitored for state are explained as follows:
transitions only; that is, the static logic level is immaterial.
Event 1—Indicates the instant that an I/O update registers that the
During no-dwell high operation, a positive transition of the digital ramp enable bit has been set.
DRCTL pin initiates a positive slope ramp, which continues
uninterrupted (regardless of any further activity on the DRCTL Event 2—DRCTL transitions to a Logic 1, initiating a positive
pin) until the upper limit is reached. slope at the DRG output.

During no-dwell low operation, a negative transition of the DRCTL Event 3—DRCTL transition to a Logic 0, which has no effect on
pin initiates a negative slope ramp, which continues uninterrupted the DRG output.
(regardless of any further activity on the DRCTL pin) until the Event 4—Because the digital ramp no-dwell high bit is set,
lower limit is reached. the moment that the DRG output reaches the upper limit, it
Setting both no-dwell bits invokes a continuous ramping mode immediately switches to the lower limit, where it remains
of operation; that is, the DRG output automatically oscillates until the next Logic 0 to Logic 1 transition of DRCTL.
between the two limits using the programmed slope parameters. Event 5—DRCTL transitions from Logic 0 to Logic 1, which
Furthermore, the function of the DRCTL pin is slightly different. restarts a positive slope ramp.
Instead of controlling the initiation of the ramp sequence, it
only serves to change the direction of the ramp; that is, if the Event 6 and Event 7—DRCTL transitions are ignored until the
DRG output is in the midst of a positive slope and the DRCTL DRG output reaches the programmed upper limit.
pin transitions from Logic 1 to Logic 0, then the DRG imme-
diately switches to the negative slope parameters and resumes Event 8—Because the digital ramp no-dwell high bit is set, the
oscillation between the limits. Likewise, if the DRG output is in moment that the DRG output reaches the upper limit, it immedi-
the midst of a negative slope and the DRCTL pin transitions from ately switches to the lower limit, where it remains until the next
Logic 0 to Logic 1, the DRG immediately switches to the positive Logic 0 to Logic 1 transition of DRCTL.
slope parameters and resumes oscillation between the limits. Operation with the digital ramp no-dwell low bit set (instead of the
When both no-dwell bits are set, the DROVER signal produces a digital ramp no-dwell high bit) is similar, except that the DRG
positive pulse (two cycles of the DDS clock) each time the DRG output ramps in the negative direction on a Logic 1 to Logic 0
output reaches either of the programmed limits (assuming that the transition of DRCTL and jumps to the upper limit upon reaching
DROVER pin active bit is set). the lower limit.

A no-dwell high DRG output waveform is shown in Figure 40. DROVER Pin
The waveform diagram assumes that the digital ramp no-dwell The DROVER pin provides an external signal to indicate the status
high bit is set and has been registered by an I/O update. The of the DRG. Specifically, when the DRG output is at either of the
status of the DROVER pin is also shown with the assumption programmed limits, the DROVER pin is Logic 1; otherwise, it is
that the DROVER pin active bit has been set. Logic 0. In the special case of both no-dwell bits set, the DROVER
pin pulses positive for two DDS clock cycles each time the DRG
output reaches either of the programmed limits.

Rev. E | Page 31 of 64
AD9910 Data Sheet
RAM CONTROL 3. Write to (or read from) the RAM (Address 0x16) the
RAM Overview appropriate number of RAM words as specified by the
selected RAM profile control register (see the Serial
The AD9910 makes use of a 1024 × 32-bit RAM. The RAM has
Programming section for details). Figure 41 is a block
two fundamental modes of operation: data load/retrieve mode
diagram showing the functional components used for RAM
and playback mode. Data load/retrieve mode is active when the
data load/retrieve operation.
RAM data is being loaded or read back via the serial I/O port.
Playback mode is active when the RAM enable contents are During RAM load/retrieve operations, the state machine controls
routed to one of the internal data destinations. an up/down counter to step through the required RAM loca-
Depending on the specific playback mode, the user can tions. The counter synchronizes with the serial I/O port so that
the serial/parallel conversion of the 32-bit words is correctly
partition the RAM with up to eight independent time domain
timed with the generation of the appropriate RAM address to
waveforms. These waveforms drive the DDS signal control
properly execute the desired read or write operation.
parameters, allowing for frequency, phase, amplitude, or polar
modulated signals. 10 WAVEFORM START ADDRESS
PROGRAMMING 3
10 WAVEFORM END ADDRESS PROFILE
REGISTERS
RAM operations are enabled by setting the RAM enable bit in
UP/DOWN
Control Function Register 1; an I/O update (or a profile change) COUNTER
2
is necessary to enact any change to the state of this bit. SDIO

ADDRESS
U/D
32

DATA
STATE SERIAL SCLK
Waveforms are generated using eight RAM profile control MACHINE Q RAM I/O
PORT I/O_RESET
registers that are accessed via the three profile pins. Each profile CS
contains the following:

06479-022
ADDRESS CLOCK

 10-bit waveform start address word Figure 41. RAM Data Load/Retrieve Operation
 10-bit waveform end address word
The RAM profiles are completely independent; it is possible
 16-bit address step rate control word
to define overlapping address ranges. Doing so causes data
 3-bit RAM mode control word
that has been written to overlapped address locations to be
 No-dwell high bit
overwritten by the most recent write operation.
 Zero-crossing bit
Multiple waveforms can be loaded into RAM by treating them
The user must ensure that the end address is greater than the as a single waveform, that is, a time-domain concatenation of all
start address. the waveforms. This is done by programming one of the RAM
profiles with a start and end address spanning the entire range
Each profile defines the number of samples and the sample rate
of the concatenated waveforms. Then the single concatenated
for a given waveform. In conjunction with an internal state
waveform is written into RAM via the serial I/O port using the
machine, the RAM contents are delivered to the appropriate
same RAM profile that was programmed with the start and end
DDS signal control parameter(s) at the specified rate. Further-
addresses. The RAM profiles must then be programmed with
more, the state machine can control the order in which samples
the proper start and end addresses associated with each
are extracted from RAM (forward/reverse), facilitating efficient
individual waveform.
generation of time symmetric waveforms.
RAM Playback Operation (Waveform Generation)
Load/Retrieve RAM Operation
When the RAM has been loaded with the desired waveform
It is strongly recommended that RAM enable = 0 when
data, it can then be used for waveform generation during play
performing RAM load/retrieve operations. Loading or
back. RAM playback requires that RAM enable = 1. To play back
retrieving the contents of the RAM requires a three-step
RAM data, select the desired waveform using the PROFILE[2:0]
process.
pins. The selected profile directs the internal state machine by
1. Program the RAM Profile 0 through RAM Profile 7 control defining the RAM address range occupied by the waveform, the
registers with the start and end addresses that are to define rate at which samples are to be extracted from the RAM
the boundaries of each independent waveform. (playback rate), the mode of operation, and whether to use the
2. Drive the appropriate logic levels on the profile pins to no-dwell feature. Figure 42 is a block diagram showing the
select the desired RAM profile. functional components used for RAM playback operation.

Rev. E | Page 32 of 64
Data Sheet AD9910
The RAM playback destination bits affect specific DDS signal
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
control parameters. The parameters that are not affected by the
RAM
ADDRESS RAMP RATE PROFILE RAM playback destination bits are controlled by the FTW, POW,
RAM MODE REGISTERS 3
10 3 NO DWELL PROFILE and/or ASF registers.
10 16 2
UP/DOWN
COUNTER
RAM_SWP_OVR (RAM Sweep Over) Pin
The RAM_SWP_OVR pin provides an active high external

ADDRESS
U/D
10 32 TO DDS

DATA
STATE signal that indicates the end of a playback sequence. The
MACHINE Q RAM SIGNAL
CONTROL
PARAMETER operation of this pin varies with the RAM operating mode
as detailed in the following sections. When RAM enable = 0,

06479-023
DDS CLOCK this pin is forced to a Logic 0.
Figure 42. RAM Playback Operation
Overview of RAM Playback Modes
During playback, the state machine uses an up/down counter to The RAM can operate in any one of five different playback modes.
step through the specified address locations. The clock rate of  Direct switch
this counter defines the playback rate, that is, the sample rate of
 Ramp-up
the generated waveform. The clocking of the counter is controlled
 Bidirectional ramp
by a 16-bit programmable timer that is internal to the state
 Continuous bidirectional ramp
machine. This timer is clocked by the DDS clock, and its time
interval is set by the 16-bit address step rate value stored in the  Continuous recirculate
selected RAM profile register. The mode is selected via the 3-bit RAM mode control word
located in each of the RAM profile registers. Thus, the RAM
The address step rate value determines the playback rate. For operating mode is profile dependent. The RAM profile mode
example, if M is the 16-bit value of the address step rate for a control bits are detailed in Table 13.
specific RAM profile, then the playback rate for that profile is
given by Table 13. RAM Operating Modes
f f RAM Profile
Playback Rate  DDSCLOCK  SYSCLK Mode Control Bits RAM Operating Mode
M 4M
000, 101, 110, 111 Direct switch
The sample interval (Δt) associated with the playback rate is 001 Ramp-up
therefore given by 010 Bidirectional ramp
1 4M 011 Continuous bidirectional ramp
Δt  
Playback Rate f SYSCLK 100 Continuous recirculate

RAM data entry/retrieval via the I/O port takes precedence RAM Direct Switch Mode
over playback operation. An I/O operation targeting the RAM In direct switch mode, the RAM is not used as a waveform genera-
during playback interrupts any waveform in progress. tor. Instead, when a RAM profile is selected via the PROFILE[2:0]
pins, only a single 32-bit word is routed to the DDS to be applied
The 32-bit words output by the RAM during playback route to
to the signal control parameter(s). This 32-bit word is the data
the DDS signal control parameters according to two RAM
stored in the RAM at the location given by the 10-bit waveform
playback destination bits in Control Function Register 1. The
start address of the selected profile.
32-bit words are partitioned based on Table 12.
In direct switch mode, the RAM_SWP_OVR pin is always
Table 12. RAM Playback Destination Logic 0, and the no-dwell high bit is ignored.
RAM Playback DDS Signal
Destination Bits Control Bits Assigned to Direct switch mode enables up to eight-level FSK, PSK, or ASK
CFR1[30:29] Parameter DDS Parameters modulation; the type of modulation is determined by the RAM
00 Frequency 31:0 playback destination bits (frequency for FSK and so on). Each
01 Phase 31:16 RAM profile is associated with a specific value of frequency,
10 Amplitude 31:18 phase, or amplitude. Each unique waveform start address value
11 Polar (phase 31:16 (phase) in each RAM profile allows access of the 32-bit word stored in
and amplitude) 15:2 (amplitude) that particular RAM location. In this way, the profile pins
When the destination is phase, amplitude, or polar, the unused implement the shift-keying function, modulating the DDS
LSBs are ignored. output as desired.

Rev. E | Page 33 of 64
AD9910 Data Sheet
Note that two-level modulation can be accomplished by using Ramp-Up Timing Diagram
only one of the three profile pins to toggle between two differ- A graphic representation of the ramp-up mode appears in
ent parameter values. Likewise, four-level modulation can be Figure 43, showing both normal and no-dwell operation.
accomplished by using only two of the three profile pins. There
is no restriction on which profile pins are used. The two upper traces show the progression of the RAM address
from the waveform start address to the waveform end address
RAM Direct Switch Mode with Zero Crossing
for the selected profile. The address value advances by one with
The zero-crossing function (enabled with the zero-crossing bit) each timeout of the timer internal to the state machine. The
is a special feature that is only available in RAM direct switch timer period (Δt) is determined by the address ramp rate value
mode. The zero-crossing function is only valid if the RAM for the selected profile. The two upper traces are differentiated
playback destination bits specify phase as the DDS signal by the state of the no-dwell high bit.
control parameter.
M DDS CLOCK CYCLES
Enabling zero-crossing causes the DDS to delay the application
of a new phase value until such time as the DDS phase accumula-
tor rolls over from full scale to 0 (the point at which the DDS
∆t
phase accumulator represents a phase angle that is at the 360° to WAVEFORM END ADDRESS
0° transition point). This can be a very beneficial feature when
RAM ADDRESS NO-DWELL
the DDS is programmed to generate a sine wave (using the 1 HIGH = 0

select DDS sine output bit) because the zero-crossing point of

WAVEFORM START ADDRESS
phase for a sine wave corresponds with the zero-crossing point WAVEFORM END ADDRESS
of amplitude.
NO-DWELL
RAM ADDRESS HIGH = 1
1
In the case of binary phase shift keying (BPSK), the zero-
crossing feature allows the AD9910 to perform the 180° phase WAVEFORM START ADDRESS

jumps associated with BPSK with only a minimal instantaneous RAM_SWP_OVER

change in amplitude. This avoids the spectral splatter that

frequently accompanies BPSK modulation. I/O_UPDATE

06479-024
1 2 3
Although the intent of the zero-crossing feature is for use with
the DDS sine output enabled, it can be used with a cosine Figure 43. Ramp-Up Timing Diagram
output. In this case, the phase values extracted from RAM are
registered at the DDS when the output amplitude is at its peak The circled numbers in Figure 43 indicate specific events,
positive value. explained as follows:

RAM Ramp-Up Mode Event 1—An I/O update or profile change occurs. This event
initializes the state machine to the waveform start address and
In ramp-up mode, upon assertion of an I/O update or a change
sets the RAM_SWP_OVR pin to Logic 0.
of profile, the RAM begins operating as a waveform generator
using the parameters programmed into the selected RAM Event 2—The state machine reaches the waveform end address
profile register. Data is extracted from RAM over the specified value for the selected profile. The RAM_SWP_OVR pin
address range and at the specified rate contained in the wave- switches to Logic 1. This marks the end of the waveform
form start address, waveform end address, and address ramp generation sequence for normal operation.
rate values of the selected RAM profile. The data is delivered
to the specified DDS signal control parameter(s) based on the Event 3—The state machine switches to the waveform start
RAM playback destination bits. address. This marks the end of the waveform generation
sequence for no-dwell operation.
The internal state machine begins extracting data from the
RAM at the waveform start address and continues to extract Changing profiles resets the RAM_SWP_OVR pin to Logic 0,
data until it reaches the waveform end address. Upon reaching automatically terminates the current waveform, and initiates the
this address, it either remains at the waveform end address or newly selected waveform.
returns to the waveform start address as defined by the no-dwell
high bit. Then the state machine halts, and the RAM_SWP_OVR
pin goes high.

Rev. E | Page 34 of 64
Data Sheet AD9910
RAM Ramp-Up Internal Profile Control Mode
Table 14. RAM Internal Profile Control Modes
Internal Profile Control Bits (CFR1[20:17]) Waveform Type Internal Profile Control Description
0000 Internal profile control disabled.
0001 Burst Execute Profile 0, then Profile 1, then halt.
0010 Burst Execute Profile 0 to Profile 2, then halt.
0011 Burst Execute Profile 0 to Profile 3, then halt.
0100 Burst Execute Profile 0 to Profile 4, then halt.
0101 Burst Execute Profile 0 to Profile 5, then halt.
0110 Burst Execute Profile 0 to Profile 6, then halt.
0111 Burst Execute Profile 0 to Profile 7, then halt.
1000 Continuous Execute Profile 0, then Profile 1, continuously.
1001 Continuous Execute Profile 0 to Profile 2, continuously.
1010 Continuous Execute Profile 0 to Profile 3, continuously.
1011 Continuous Execute Profile 0 to Profile 4, continuously.
1100 Continuous Execute Profile 0 to Profile 5, continuously.
1101 Continuous Execute Profile 0 to Profile 6, continuously.
1110 Continuous Execute Profile 0 to Profile 7, continuously.
1111 Invalid.

Ramp up internal profile control mode is invoked via the four At this point, the next course of action depends on whether the
internal profile control bits (rather than through the RAM waveform type is burst or continuous. For burst waveforms, the
profile mode control bits in the RAM profile registers). state machine halts operation after reaching the waveform end
address of the final profile. For continuous waveforms, the state
If any of the internal profile control bits is set, then the RAM machine automatically jumps to Profile 0 and continues the
profile mode control bits of the RAM profile registers are automatic waveform generation by sequentially advancing
ignored. The no-dwell high bit is ignored in this mode. The through the profiles. This process continues indefinitely until
internal profile control mode is identical to ramp-up mode the internal profile control bits are reprogrammed and an I/O
except that profile switching is done automatically and update is asserted.
internally; the state of the PROFILE[2:0] pins is ignored.
Profiles cycle according to Table 14. A burst waveform timing diagram is exemplified in Figure 44.
The diagram assumes that the internal profile control bits in
There are two types of waveform generation types available Register CFR1 are programmed as 0010, the start address in
under internal profile control: burst waveforms and continuous RAM Profile 1 is greater than the end address in RAM Profile 0,
waveforms. With both types, the state machine begins with the and that the start address in RAM Profile 2 is greater than the
waveform specified by the waveform start address, waveform end address in RAM Profile 1. However, the block of RAM
end address, and address ramp rate in Profile 0. After reaching associated with each profile can be chosen arbitrarily based on
the waveform end address of Profile 0, the state machine automati- the waveform start address and waveform end address for each
cally advances to the next profile and initiates the specified profile. Furthermore, the example shows how different Δt
waveform as defined by the new profile parameters. After the values associated with each profile can be used.
state machine reaches the waveform end address of the new
profile, it advances to the next profile. This action continues
until the state machine reaches the waveform end address of
the last profile, as governed by the internal profile control bits in
Control Function Register 1 (CFR1) per Table 14.

Rev. E | Page 35 of 64
AD9910 Data Sheet
RAM PROFILE 0 1 2

WAVEFORM END ADDRESS 2 Δt2

WAVEFORM START ADDRESS 2 1

WAVEFORM END ADDRESS 1 Δt1

RAM
ADDRESS
WAVEFORM START ADDRESS 1 1

WAVEFORM END ADDRESS 0

Δt0
1

WAVEFORM START ADDRESS 0

RAM_SWP_OVER

I/O_UPDATE

06479-025
1 2 3 4 5 6 7

Figure 44. Internal Profile Control Timing Diagram (Burst)

The gray bar across the top indicates the time interval over Event 4—The state machine reaches the waveform end address
which the designated profile is in effect. The circled numbers of RAM Profile 1, and the RAM_SWP_OVR pin generates a
indicate specific events as follows: positive pulse spanning two DDS clock cycles.

Event 1—An I/O update registers the internal profile control bits Event 5—Having reached the waveform end address of RAM
(in Control Function Register 1) as 0010. The RAM_SWP_OVR Profile 1, the next expiration of the internal timer causes the
pin is set to Logic 0. The state machine is initialized to the state machine to advance to RAM Profile 2. The state machine
waveform start address of RAM Profile 0 and begins increment- initializes to the waveform start address of RAM Profile 2 and
ing through the address range for RAM Profile 0 at intervals of begins incrementing through the address range for RAM
Δt0 (as specified by the address step rate for RAM Profile 0). Profile 2 at intervals of Δt2.

Event 2—The state machine reaches the waveform end address Event 6—The state machine reaches the waveform end address of
of RAM Profile 0, and the RAM_SWP_OVR pin generates a RAM Profile 2, and the RAM_SWP_OVR pin generates a positive
positive pulse spanning two DDS clock cycles. pulse spanning two DDS clock cycles.

Event 3—Having reached the waveform end address of RAM Event 7—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the Profile 2, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine state machine to halt and marks completion of the burst
is initialized to the waveform start address of RAM Profile 1 waveform generation process.
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt1.

Rev. E | Page 36 of 64
Data Sheet AD9910
RAM PROFILE 0 1 0 1 0 1

WAVEFORM END Δt1

ADDRESS 1

WAVEFORM START 1
ADDRESS 1
RAM
ADDRESS WAVEFORM END
ADDRESS 0

Δt0
1

WAVEFORM START
ADDRESS 0
RAM_SWP_OVER

I/O_UPDATE

06479-026
1 2 3 4 5 6 7 8 9 10 11

Figure 45. Internal Profile Control Timing Diagram (Continuous)

Internal Profile Control Continuous Waveform Timing Profile 0 and begins incrementing through the address range for
Diagram RAM Profile 0 at intervals of Δt0.
An example of an internal profile control continuous waveform Event 5 to Event 11—These events repeat indefinitely until the
timing diagram is shown in Figure 45. The diagram assumes that internal profile control bits are reprogrammed and an I/O
the internal profile control bits (in Control Function Register 1) update is asserted.
are programmed as 1000. It also assumes that the start address in
RAM Profile 1 is greater than the end address in RAM Profile 0. RAM Bidirectional Ramp Mode
In bidirectional ramp mode, upon assertion of an I/O update,
The gray bar across the top indicates the time interval over the RAM begins operating as a waveform generator using the
which the designated profile is in effect. The circled numbers parameters programmed only into RAM Profile 0 (unlike ramp
indicate specific events.
up mode, which uses all eight profiles). Data is extracted from
Event 1—An I/O update registers that the internal profile RAM over the specified address range and at the specified rate
control bits (in Control Function Register 1) are programmed contained in the waveform start address, waveform end address,
to 1000. The RAM_SWP_OVR pin is set to Logic 0. The state and address ramp rate values of the selected RAM profile. The
machine is initialized to the waveform start address of RAM data is delivered to the specified DDS signal control parameter(s)
Profile 0 and begins incrementing through the address range for based on the RAM playback destination bits.
RAM Profile 0 at intervals of Δt0 (as specified by the address The PROFILE[2:1] pins are ignored by the internal logic in this
step rate for RAM Profile 0).
mode. When a RAM profile programmed to operate in this
Event 2—The state machine reaches the waveform end address mode is selected, no other RAM profiles can be selected until the
of RAM Profile 0, and the RAM_SWP_OVR pin generates a active RAM profile is reprogrammed with a different RAM
positive pulse spanning two DDS clock cycles. operating mode. The no-dwell high bit is ignored in this mode.

Event 3—Having reached the waveform end address of RAM With the bidirectional ramp mode activated via an I/O update
Profile 0, the next expiration of the internal timer causes the or profile change, the internal state machine readies to extract
state machine to advance to RAM Profile 1. The state machine data from the RAM at the waveform start address. Data extrac-
is initialized to the waveform start address of RAM Profile 1 tion begins when PROFILE0 is Logic 1, which instructs the state
and begins incrementing through the address range for RAM machine to begin incrementing through the address range. As
Profile 1 at intervals of Δt1. long as the PROFILE0 pin remains Logic 1, the state machine
continues to extract data until it reaches the waveform end
Event 4—The state machine reaches the waveform end address address. At this point, the state machine halts until the PROFILE0
of RAM Profile 1, and the RAM_SWP_OVR pin generates a pin is Logic 0, instructing the state machine to begin decrementing
positive pulse spanning two DDS clock cycles. through the address range. As long as the PROFILE0 pin is
Logic 0, the state machine continues to extract data until it
Event 5—Having reached the waveform end address of RAM
reaches the waveform start address. At this point, the state
Profile 1, the next expiration of the internal timer causes the
machine halts until the PROFILE0 pin is Logic 1.
state machine to jump back to RAM Profile 0. The state
machine initializes to the waveform start address of RAM

Rev. E | Page 37 of 64
AD9910 Data Sheet
M DDS CLOCK CYCLES

Δt Δt
WAVEFORM END ADDRESS

RAM ADRESS
1

WAVEFORM START ADDRESS

RAM_SWP_OVER

PROFILE0

I/O_UPDATE

1 2 3 4 5 6 7 8

06479-027
Figure 46. Bidirectional Ramp Timing Diagram

If the PROFILE0 pin changes states before the state machine Event 6—Pin PROFILE0 switches to Logic 0. The state machine
reaches the programmed start or end address, the internal timer resets its internal timer and again reverses the direction of the RAM
is restarted and the direction of the address counter is reversed. address counter. The RAM_SWP_OVR state does not change.

Figure 46 is a graphic representation of the bidirectional ramp Event 7—Pin PROFILE0 remains at Logic 0 long enough for the
mode. It shows the action of the state machine in response to state machine to reach the waveform start address. There is no
the PROFILE0 pin and the response of the RAM_SWP_OVR pin. change in the RAM_SWP_OVR state.

The RAM_SWP_OVR pin switches to Logic 1 when the state Event 8—Pin PROFILE0 switches to Logic 1. The state machine
machine reaches the waveform end address. It remains Logic 1 resets its internal timer and begins incrementing the RAM
until the state machine reaches the waveform start address and address counter. The RAM_SWP_OVR pin switches to Logic 0
the PROFILE0 pin transitions from Logic 0 to Logic 1. because both the waveform start address was reached and the
PROFILE0 pin transitioned from Logic 0 to Logic 1.
The circled numbers in Figure 46 indicate specific events as
follows: RAM Continuous Bidirectional Ramp Mode
In continuous bidirectional ramp mode, upon assertion of an
Event 1—An I/O update or profile change activates the RAM
I/O update or a change of profile, the RAM begins operating
bidirectional ramp mode. The state machine initializes to the
as a waveform generator using the parameters programmed
waveform start address, and the RAM_SWP_OVR pin is set to
into the RAM profile designated by the PROFILEx pins. Data is
Logic 0.
extracted from RAM over the specified address range and at the
Event 2—Pin PROFILE0 switches to Logic 1. The state machine specified rate contained in the waveform start address, waveform
begins incrementing the RAM address counter. end address, and address ramp rate values of the selected RAM
profile. The data is delivered to the specified DDS signal control
Event 3—Pin PROFILE0 remains at Logic 1 long enough for the parameter(s) based on the RAM playback destination bits. The
state machine to reach the waveform end address. The RAM_ no-dwell high bit is ignored in this mode.
SWP_OVR pin switches to Logic 1 accordingly.
With the continuous bidirectional ramp mode activated via an
Event 4—Pin PROFILE0 switches to Logic 0. The state machine I/O update or profile change, the internal state machine begins
begins decrementing the RAM address counter. The RAM_ extracting data from the RAM at the waveform start address and
SWP_OVR pin remains at Logic 1. incrementing the address counter until it reaches the waveform
end address. At this point, the state machine automatically reverses
Event 5—Pin PROFILE0 switches to Logic 1. The state machine
the direction of the address counter and begins decrementing
resets its internal timer and reverses the direction of the RAM
through the address range. Whenever one of the terminal
address counter (that is, it starts to increment). There is no
addresses is reached, the state machine reverses the address
change of the RAM_SWP_OVR state because the waveform
counter; the process continues indefinitely.
start address has not yet been reached.

Rev. E | Page 38 of 64
Data Sheet AD9910
M DDS CLOCK CYCLES

Δt Δt
WAVEFORM END ADDRESS

RAM ADRESS
1

WAVEFORM START ADDRESS

RAM_SWP_OVER

I/O_UPDATE

06479-028
1 2 3

Figure 47. Continuous Bidirectional Ramp Timing Diagram

A change in state of the PROFILE pins aborts the current wave- Event 1—An I/O update or profile change has activated the RAM
form, and the newly selected RAM profile is used to initiate a continuous bidirectional ramp mode. The state machine initializes
new waveform. to the waveform start address. The RAM_SWP_OVR pin resets to
Logic 0. The state machine begins incrementing through the
The RAM_SWP_OVR pin switches to Logic 1 when the state specified address range.
machine reaches the waveform end address, then returns to
Logic 0 at the waveform start address, toggling each time one Event 2—The state machine reaches the waveform end address.
of these addresses is reached. The RAM_SWP_OVR pin toggles to Logic 1.

A graphic representation of the continuous bidirectional ramp Event 3—The state machine reaches the waveform start address.
mode is shown in Figure 47. The circled numbers indicate specific The RAM_SWP_OVR pin toggles to Logic 0.
events as follows:
The continuous bidirectional ramp continues indefinitely until
the mode is changed.

Rev. E | Page 39 of 64
AD9910 Data Sheet
M DDS CLOCK CYCLES

∆t
WAVEFORM END ADDRESS

RAM ADRESS
1

WAVEFORM START ADDRESS

RAM_SWP_OVER

I/O_UPDATE

06479-029
1 2 3 4 5

Figure 48. Continuous Recirculate Timing Diagram

RAM Continuous Recirculate Mode Event 1—An I/O update or profile change occurs. This event
The continuous recirculate mode mimics the ramp-up mode, initializes the state machine to the waveform start address and
except that when the state machine reaches the waveform end sets the RAM_SWP_OVR pin to Logic 0.
address, the next timeout of the internal timer causes the state Event 2—The state machine reaches the waveform end address
machine to jump to the waveform start address. The waveform value for the selected profile. The RAM_SWP_OVR pin toggles
repeats until an I/O update or profile change. to Logic 1 for two DDS clock cycles.
The no-dwell high bit is ignored in this mode. Event 3—The state machine switches to the waveform start
A profile pin state change aborts the current waveform, and the address and continues to increment the address counter.
newly selected RAM profile is used to initiate a new waveform. Event 4—The state machine again reaches the waveform end
The RAM_SWP_OVR pin pulses high for two DDS clock cycles address value for the selected profile, and the RAM_SWP_OVR
when the state machine reaches the waveform end address. pin toggles to Logic 1 for two DDS clock cycles.

Continuous recirculate mode is graphically represented in Event 5—The state machine switches to the waveform start
Figure 48. The circled numbers indicate specific events as address and continues to increment the address counter.
follows:
Event 4 and Event 5—These events repeat until an I/O update is
issued or a change in profile is made.

Rev. E | Page 40 of 64
Data Sheet AD9910

ADDITIONAL FEATURES
PROFILES pin is connected to the serial bit stream. In this way, the logic
The AD9910 supports the use of profiles, which consist of a group state of the PROFILE0 pin causes the appropriate mark and
of eight registers containing pertinent operating parameters for space frequencies to be generated in accordance with the binary
a particular operating mode. Profiles enable rapid switching digits of the bit stream.
between parameter sets. Profile parameters are programmed via The profile pins must meet setup and hold times to the rising
the serial I/O port. Once programmed, a specific profile is edge of SYNC_CLK.
activated by means of three external pins (PROFILE[2:0]). A
particular profile is activated by providing the appropriate logic I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
levels to the profile control pins per Table 15. RELATIONSHIPS
Table 15. Profile Control Pins The I/O_UPDATE pin is used to transfer data from the serial
PROFILE[2:0] Active Profile I/O buffer to the active registers in the device. Data in the buffer
is inactive.
000 0
001 1 SYNC_CLK is a rising edge active signal. It is derived from the
010 2 system clock and a divide-by-4 frequency divider. SYNC_CLK,
011 3 which is externally provided, can be used to synchronize external
100 4 hardware to the AD9910 internal clocks.
101 5
110 6 I/O_UPDATE initiates the start of a buffer transfer. It can be
111 7 sent synchronously or asynchronously relative to the SYNC_CLK.
If the setup time between these signals is met, then constant
There are two different parameter sets that the eight profile latency (pipeline) to the DAC output exists. For example, if
registers can control depending on the operating mode of the repetitive changes to phase offset via the SPI port is desired,
device. When RAM enable = 0, the profile parameters follow the latency of those changes to the DAC output is constant;
the single tone profile format detailed in the Register Map and otherwise, a time uncertainty of one SYNC_CLK period is
Bit Descriptions section. When RAM enable = 1, they follow present.
the RAM profile format.
By default, the I/O_UPDATE pin is an input that serves as a
As an example of the use of profiles, consider an application for strobe signal to allow synchronous update of the device operat-
implementing basic two-tone frequency shift keying (FSK). FSK ing parameters. A rising edge on I/O_UPDATE initiates transfer
uses the binary data in a serial bit stream to select between two of the register contents to the internal workings of the device.
different frequencies: a mark frequency (Logic 1) and a space Alternatively, the transfer of programmed data from the program-
frequency (Logic 0). To accommodate FSK, the device operates ming registers to the internal hardware can be accomplished by
in single tone mode. The Single Tone Profile 0 register is pro- changing the state of the PROFILE[2:0] pins.
grammed with the appropriate frequency tuning word for a
space. The Single Tone Profile 1 register is programmed with The timing diagram shown in Figure 49 depicts when the data
the appropriate frequency tuning word for a mark. Then, with in the buffer is transferred to the active registers.
the PROFILE1 and PROFILE2 pins tied to Logic 0, the PROFILE0

SYSCLK

A B

SYNC_CLK

I/O_UPDATE

DATA IN N–1 N N+1

REGISTERS

DATA IN
I/O BUFFERS N N+1 N+2
06479-061

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

Figure 49. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers

Rev. E | Page 41 of 64
AD9910 Data Sheet
AUTOMATIC I/O UPDATE POWER-DOWN CONTROL
The AD9910 offers an option whereby the I/O update function The AD9910 offers the ability to independently power down
is asserted automatically rather than relying on an external signal four specific sections of the device. Power-down functionality
supplied by the user. This feature is enabled by setting the internal applies to the following:
I/O update active bit in Control Function Register 2 (CFR2).
• Digital core
When this feature is active, the I/O_UPDATE pin becomes an • DAC
output pin. It generates an active high pulse each time an inter- • Auxiliary DAC
nal I/O update occurs. The pulse width is determine by the I/O • Input REFCLK clock circuitry
update rate control bits (CFR2[15:14]). Table 16 approximates the
pulse width setting. A power-down of the digital core disables the ability to update
the serial I/O port. However, the digital power-down bit can
Table 16. Pulse Width Setting still be cleared via the serial port to prevent the possibility of a
I/O Update Rate Control Bits nonrecoverable state.
(CFR2[15:14]) I/O Update Pulse Width
00 12 SYSCLKs Software power-down is controlled via four independent power-
01 24 SYSCLKs down bits in Control Function Register 1 (CFR1). Software
10 48 SYSCLKs control requires that the EXT_PWR_DWN pin be forced to a
11 96 SYSCLKs Logic 0 state. In this case, setting the desired power-down bits
(via the serial I/O port) powers down the associated functional
This I/O update strobe can be used to notify an external
block, whereas clearing the bits restores the function.
controller that the device has generated an I/O update
internally. Alternatively, all four functions can be simultaneously powered
down via external hardware control through the EXT_PWR_DWN
The repetition rate of the internal I/O update is programmed
pin. When this pin is forced to Logic 1, all four circuit blocks are
via the serial I/O port. There are two parameters that control
powered down regardless of the state of the power-down bits;
the repetition rate. The first consists of the two I/O update rate
that is, the independent power-down bits in CFR1 are ignored
control bits in CFR2. The second is the 32-bit word in the I/O
and overridden when EXT_PWR_DWN is Logic 1.
update rate register that sets the range of an internal counter.
The I/O update rate control bits establish a divide-by-1, -2, -4, Based on the state of the external power-down control bit, the
or -8 of a clock signal that runs at ¼ fSYSCLK. The output of the EXT_PWR_DWN pin produces either a full power-down or a
divider clocks the aforementioned 32-bit internal counter. The fast recovery power-down. The fast recovery power-down mode
repetition rate of the I/O update is given by maintains power to the DAC bias circuitry and the PLL, VCO,
f SYSCLK and input clock circuitry. Although the fast recovery power-
f I / O _ UPDATE = down does not conserve as much power as the full power-down,
2 A+2 B
it allows the device to awaken very quickly from the power-
where: down state.
A is the value of the 2-bit word comprising the I/O update rate
control bits.
B is the value of the 32-bit word stored in the I/O update rate
register.

The default value of A is 0, and the value of B is 0xFFFF. If B is

programmed to 0x0003 or less, the I/O_UPDATE pin no longer
pulses but assumes a static Logic 1 state.

Rev. E | Page 42 of 64
Data Sheet AD9910

SYNCHRONIZATION OF MULTIPLE DEVICES

Multiple devices are synchronized when their clock states match The sync generator block is shown in Figure 51. It is activated
and they transition between states simultaneously. Clock via the sync generator enable bit. It allows for one AD9910 in a
synchronization allows the user to asynchronously program group to function as a master timing source with the remaining
multiple devices but synchronously activate the programming by devices slaved to the master.
applying a coincident I/O update to all devices
9 SYNC_OUT+
PROGAMMABLE
The function of the synchronization logic in the AD9910 is to SYSCLK ÷16 D Q
DELAY 10 SYNC_OUT–
10
force the internal clock generator to a predefined state coincident 0 LVDS
5 DRIVER
with an external synchronization signal applied to the SYNC_INx 1 R
SYNC
pins. If all devices are forced to the same clock state in synchro- GENERATOR
DELAY
nization with the same external signal, then the devices are, by SYNC
SYNC
POLARITY
GENERATOR
definition, synchronized. Figure 50 is a block diagram of the

06479-051
ENABLE
synchronization function. The synchronization logic is divided
into two independent blocks: a sync generator and a sync receiver, Figure 51. Sync Generator Diagram
both of which use the local SYSCLK signal for internal timing.
The sync generator produces a clock signal that appears at the
SYNC_OUTx pins. This clock is delivered by an LVDS driver
REF_CLK 90 REF_CLK and exhibits a 50% duty cycle. The clock has a fixed frequency
SYSCLK INPUT
CIRCUITRY 91 REF_CLK given by
GENERATOR

GENERATOR

f SYSCLK
f SYNC _ OUT 
POLARITY
ENABLE

16
DELAY
SYNC

SYNC

SYNC

5
The clock at the SYNC_OUTx pins synchronizes with either the
rising or falling edge of the internal SYSCLK signal, as determined
9 SYNC_OUT+
SYNC
GENERATOR
by the sync generator polarity bit. Because the SYNC_OUTx signal
10 SYNC_OUT–
is synchronized with the internal SYSCLK of the master device,
SYNC SYNC the master device SYSCLK serves as the reference timing source
RECEIVER
RECEIVER
ENABLE DELAY for all slave devices. The user can adjust the output delay of the
5 SYNC_OUTx signal in steps of ~75 ps by programming the 5-bit
SYNC_IN+
output sync generator delay word via the serial I/O port. The
INPUT DELAY 7
programmable output delay facilitates added edge timing
GENERATOR

AND EDGE
DETECTION 8 SYNC_IN–
CLOCK

INTERNAL SYNC flexibility to the overall synchronization mechanism.

CLOCKS RECEIVER

SETUP AND 12 SYNC_SMP_ERR The sync receiver block (shown in Figure 52) is activated via the
HOLD VALIDATION
sync receiver enable bit (0x0A[27]). The sync receiver consists
4 of three subsections: the input delay and edge detection block,
SYNC SYNC the internal clock generator block, and the setup and hold
VALIDATION TIMING
DELAY VALIDATION validation block.
06479-050

DISABLE

The clock generator block remains operational even if the sync

Figure 50. Synchronization Circuit Block Diagram
receiver is not enabled.
The synchronization mechanism relies on the premise that the
REFCLK signal appearing at each device is edge aligned with all
others as a result of the external REFCLK distribution system
(see Figure 53).

Rev. E | Page 43 of 64
AD9910 Data Sheet
CLOCK
STATE
DELAYED SYNC-IN SIGNAL SYNC
RECEIVER
SYNC ENABLE Q0
RECEIVER
DELAY • •
INTERNAL
• • CLOCKS
LVDS 5
RECEIVER
• •
RISING EDGE Qn
SYNC_IN+ 7 DETECTOR
PROGAMMABLE AND RESET
SYNC_IN– 8 DELAY STROBE
GENERATOR
CLOCK
SETUP AND HOLD GENERATOR
SYNC_SMP_ERR 12 VALIDATION
SYSCLK

4
SYNC SYNC SYNC PULSE
TIMING VALIDATION
VALIDATION

06479-052
DELAY
DISABLE

Figure 52. Sync Receiver Diagram

CLOCK DISTRIBUTION
AND CLOCK
DELAY EQUALIZATION SOURCE
EDGE (FOR EXAMPLE AD951x)
ALIGNED
AT REF_CLK
INPUTS

DATA REF_CLK
AD9910
PDCLK

FPGA NUMBER 1 MASTER DEVICE

SYNC SYNC
IN OUT

EDGE
ALIGNED
DATA REF_CLK AT SYNC_IN
AD9910 INPUTS.
PDCLK

FPGA NUMBER 2
SYNC SYNC
IN OUT
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
DATA REF_CLK
AD9910
PDCLK

FPGA NUMBER 3
SYNC SYNC
IN OUT
06479-053

Figure 53. Multichip Synchronization Example

The sync receiver accepts a periodic clock signal at the SYNC_ of the delayed SYNC_INx signal with the rising edge of the
INx pins. This signal is assumed to originate from an LVDS- local SYSCLK. The sync pulse is routed to the internal clock
compatible driver. The user can delay the SYNC_INx signal in generator, which behaves as a presettable counter clocked at the
steps of ~75 ps by programming the 5-bit input sync receiver SYSCLK rate. The sync pulse presets the counter to a predefined
delay word in the multichip sync register. The signal at the state (programmable via the 6-bit sync state preset value word
output of the programmable delay is referred to as the delayed in the multichip sync register). The predefined state is only active
SYNC_INx signal. for a single SYSCLK cycle, after which the clock generator resumes
cycling through its state sequence at the SYSCLK rate. This
Note that an internal 100 Ω LVDS termination resistor exists unique state presetting mechanism gives the user the flexibility
across both SYNC_IN inputs. to synchronize devices with specific relative clock state offsets
(by assigning a different sync state preset value word to each
The edge detection logic generates a sync pulse having a dura- device).
tion of one SYSCLK cycle with a repetition rate equal to the
frequency of the signal applied to the SYNC_INx pins. The Multiple device synchronization is accomplished by providing
sync pulse is generated as a result of sampling the rising edge each AD9910 with a SYNC_INx signal that is edge aligned
Rev. E | Page 44 of 64
Data Sheet AD9910
across all the devices. If the SYNC_INx signal is edge aligned at all assume the same predefined clock state simultaneously; that is,
devices, and all devices have the same sync receiver delay and the internal clocks of all devices become fully synchronized.
sync state preset value, then they all have matching clock states
(that is, they are synchronized). This concept is shown in The synchronization mechanism depends on the reliable gen-
Figure 53, in which three AD9910 devices are synchronized, eration of a sync pulse by the edge detection block in the sync
with one device operating as a master timing unit and the receiver. Generation of a valid sync pulse, however, requires
others as slave units. proper sampling of the rising edge of the delayed SYNC_INx signal
with the rising edge of the local SYSCLK. If the edge timing of
The master device must have its SYNC_INx pins included as part these signals fails to meet the setup or hold time requirements
of the synchronization distribution and delay equalization mecha- of the internal latches in the edge detection circuitry, then the
nism in order for it to be synchronized with the slave units. proper generation of the sync pulse is in jeopardy. The setup
and hold validation block (see Figure 54) gives the user a means
The synchronization mechanism begins with the clock distribu- to validate that proper edge timing exists between the two signals.
tion and delay equalization block, which is used to ensure that
all devices receive an edge-aligned REFCLK signal. However, The setup and hold validation block can be disabled via the
even though the REFCLK signal is edge aligned among all devices, sync timing validation disable bit in Control Function Register 2.
this alone does not guarantee that the clock state of each internal
clock generator is coordinated with the others. This is the role The validation block makes use of a user-specified time window
of the synchronization and delay equalization block. This block (programmable in increments of ~75 ps via the 4-bit sync
accepts the SYNC_OUTx signal generated by the master device validation delay word in the multichip sync register). The setup
and redistributes it to the SYNC_INx input of the slave units (as validation and hold validation circuits use latches identical to
well as feeding it back to the master). The goal of the redistributed those in the rising edge detector and strobe generator. The
SYNC_OUT x signal from the master device is to deliver an programmable time window is used to skew the timing between
edge-aligned SYNC_INx signal to all of the sync receivers. the rising edges of the local SYSCLK signal and the rising edges
of the delayed SYNC_INx signal. If either the hold or setup
Assuming that all devices share the same REFCLK edge (due to validation circuits fail to detect a valid edge sample, the condition
the clock distribution and delay equalization block), and all is indicated externally via the SYNC_SMP_ERR pin (active high).
devices share the same SYNC_INx edge (due to the synchroni-
zation and delay equalization block), then all devices should The user must choose a sync validation delay value that is a
generate an internal sync pulse in unison (assuming that they reasonable fraction of the SYSCLK period. For example, if the
all have the same sync receiver delay value). With the further SYSCLK frequency is 1 GHz (1 ns period), then a reasonable
stipulation that all devices have the same sync state preset value, value is 4 (300 ps). Choosing too large a value can cause the
then the synchronized sync pulses cause all of the devices to SYNC_SMP_ERR pin to generate false error signals. Choosing
too small a value may cause instability.

SYNC RECEIVER

RISING EDGE
FROM DETECTOR
SYNC AND STROBE
RECEIVER GENERATOR
DELAY
LOGIC TO
CLOCK
D Q SYNC GENERATION
PULSE LOGIC

SETUP AND HOLD VALIDATION

SETUP
VALIDATION
DELAY D Q
CHECK LOGIC

44
SYNC VALIDATION 12
12 SYNC_SMP_ERR
4 DELAY

DQ
SYSCLK DELAY HOLD
VALIDATION
06479-054

SYNC TIMING VALIDATION DISABLE

Figure 54. Sync Timing Validation Block

Rev. E | Page 45 of 64
AD9910 Data Sheet

POWER SUPPLY PARTITIONING

The AD9910 features multiple power supplies, and their power 1.8 V SUPPLIES
consumption varies with its configuration. This section covers DVDD (1.8 V) (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, and
which power supplies can be grouped together and how the Pin 64)
power consumption of each block varies with frequency.
These pins can be grouped together. Their current consumption
The values quoted in this section are for comparison only. Refer increases linearly with the system clock frequency. See Figure 17
to Table 1 for exact values. With each group, use 0.1 μF or 0.01 μF and Figure 18 for typical current consumption curves. There is
bypass capacitors in parallel with a 10 μF capacitor. also a slight (~5%) increase as fOUT increases from 50 MHz to
400 MHz.
The recommendations here are for typical applications, for
which there are four groups of power supplies: 3.3 V digital, AVDD (1.8 V) (Pin 3)
3.3 V analog, 1.8 V digital, and 1.8 V analog. This 1.8 V supply powers the REFCLK multiplier (PLL) and
consumes about 7 mA. For applications demanding the highest
Applications demanding the highest performance may require performance with the PLL enabled, this supply should be
additional power supply isolation. isolated from other 1.8 V AVDD supplies with a separate
3.3 V SUPPLIES regulator. For less demanding applications, this supply can be
run off the same regulator as Pin 89 and Pin 92 with a ferrite
DVDD_I/O (3.3 V) (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45,
bead to isolate Pin 3 from Pin 89 and Pin 92.
Pin 56, and Pin 66)
These 3.3 V supplies can be grouped together. The power The loop filter for the PLL should directly connect to Pin 3. If
consumption on these pins varies dynamically with serial port the PLL is bypassed, Pin 3 should still be powered, but isolation
activity. is not critical.

AVDD (3.3 V) (Pin 74 to Pin 77 and Pin 83) AVDD (1.8 V) (Pin 6)
These are 3.3 V DAC power supplies that typically consume This pin can be grouped together with the DVDD 1.8 V supply
about 28 mA. At a minimum, a ferrite bead should be used to pins. For the highest performance, a ferrite bead should be used
isolate these from other 3.3 V supplies, with a separate regulator for isolation, with a separate regulator being ideal.
being ideal. The current consumption of these supplies consist
AVDD (1.8 V) (Pin 89 and Pin 92)
mainly of biasing current and do not vary with frequency.
This 1.8 V supply for the REFCLK input consumes about
15 mA. These pins can run off the supply of Pin 3 with a ferrite
bead to isolate Pin 3 from Pin 89 and Pin 92. At a minimum, a
ferrite bead should be used to isolate these from other 1.8 V
supplies. However, for applications demanding the highest
performance, a separate regulator is recommended.

Rev. E | Page 46 of 64
Data Sheet AD9910

SERIAL PROGRAMMING
CONTROL INTERFACE—SERIAL I/O the serial port buffer, and data is driven out on the falling edge
of SCLK.
The AD9910 serial port is a flexible, synchronous serial commu-
nications port allowing easy interface to many industry-standard Note that to read back any profile register (0x0E to 0x15), the
microcontrollers and microprocessors. The serial I/O is compatible three external profile pins must be used. For example, if the
with most synchronous transfer formats. profile register is Profile 5 (0x13), then the PROFILE[0:2] pins
must equal 101.This is not required to write to profile registers.
The interface allows read/write access to all registers that configure
the AD9910. MSB-first or LSB-first transfer formats are INSTRUCTION BYTE
supported. In addition, the serial interface port can be configured The instruction byte contains the following information as
as a single pin input/output (SDIO) allowing a 2-wire interface, shown in the instruction byte information bit map.
or it can
be configured as two unidirectional pins for input/output Instruction Byte Information Bit Map
(SDIO/SDO) enabling a 3-wire interface. Two optional pins MSB LSB
(I/O_RESET and CS) enable greater flexibility for designing D7 D6 D5 D4 D3 D2 D1 D0
systems with the AD9910. R/W X X A4 A3 A2 A1 A0
GENERAL SERIAL I/O OPERATION R/W—Bit 7 of the instruction byte determines whether a read
There are two phases to a serial communications cycle. The first or write data transfer occurs after the instruction byte write.
is the instruction phase to write the instruction byte into the Logic 1 indicates a read operation. Cleared indicates a write
AD9910. The instruction byte contains the address of the register operation.
to be accessed (see the Register Map and Bit Descriptions
section) and defines whether the upcoming data transfer is a X, X—Bit 6 and Bit 5 of the instruction byte are don’t cares.
write or read operation. A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
For a write cycle, Phase 2 represents the data transfer between instruction byte determine which register is accessed during the
the serial port controller to the serial port buffer. The number data transfer portion of the communications cycle.
of bytes transferred is a function of the register being accessed. SERIAL I/O PORT PIN DESCRIPTIONS
For example, when accessing the Control Function Register 2
SCLK—Serial Clock
(Address 0x01), Phase 2 requires that four bytes be transferred.
Each bit of data is registered on each corresponding rising edge The serial clock pin is used to synchronize data to and from the
of SCLK. The serial port controller expects that all bytes of the AD9910 and to run the internal state machines.
register be accessed; otherwise, the serial port controller is put
CS—Chip Select Bar
out of sequence for the next communication cycle. However,
one way to write fewer bytes than required is to use the I/O_RESET CS is an active low input that allows more than one device on
pin feature. The I/O_RESET pin function can be used to abort the same serial communications line. The SDO and SDIO pins
an I/O operation and reset the pointer of the serial port con- go to a high impedance state when this input is high. If driven
troller. After an I/O reset, the next byte is the instruction byte. high during any communications cycle, that cycle is suspended
Note that every completed byte written prior to an I/O reset is until CS is reactivated low. Chip select (CS) can be tied low in
preserved in the serial port buffer. Partial bytes written are not systems that maintain control of SCLK.
preserved. At the completion of any communication cycle, the
SDIO—Serial Data Input/Output
AD9910 serial port controller expects the next eight rising
SCLK edges to be the instruction byte for the next communi- Data is always written into the AD9910 on this pin. However,
cation cycle. this pin can be used as a bidirectional data line. Bit 1 of CFR1
Register Address 0x00 controls the configuration of this pin.
After a write cycle, the programmed data resides in the serial The default is cleared, which configures the SDIO pin as
port buffer and is inactive. I/O_UPDATE transfers data from bidirectional.
the serial port buffer to active registers. The I/O update can be
sent either after each communication cycle or when all serial SDO—Serial Data Out
operations are complete. In addition, a change in profile pins Data is read from this pin for protocols that use separate lines
can initiate an I/O update. for transmitting and receiving data. When the AD9910 operates
in single bidirectional I/O mode, this pin does not output data
For a read cycle, Phase 2 is the same as the write cycle with the and is set to a high impedance state.
following differences: data is read from the active registers, not

Rev. E | Page 47 of 64
AD9910 Data Sheet
I/O_RESET—Input/Output Reset SERIAL I/O TIMING DIAGRAMS
I/O_RESET synchronizes the I/O port state machines without Figure 55 through Figure 58 provide basic examples of the timing
affecting the contents of the addressable registers. An active relationships between the various control signals of the serial
high input on the I/O_RESET pin causes the current communica- I/O port. Most of the bits in the register map are not transferred
tion cycle to abort. After I/O_RESET returns low (Logic 0), to their internal destinations until assertion of an I/O update,
another communication cycle can begin, starting with the which is not included in the timing diagrams that follow.
instruction byte write.
MSB/LSB TRANSFERS
I/O_UPDATE—Input/Output Update
The AD9910 serial port can support both most significant bit
The I/O_UPDATE initiates the transfer of written data from (MSB) first or least significant bit (LSB) first data formats. This
the I/O port buffer to active registers. I/O_UPDATE is active functionality is controlled by Bit 0 in Control Function Register 1
on the rising edge, and its pulse width must be greater than one (0x00). The default format is MSB first. If LSB first is active, all
SYNC_CLK period. It is either an input or output pin depending data, including the instruction byte, must follow LSB-first conven-
on the programming of the internal I/O update active bit. tion. Note that the highest number found in the bit range column
for each register is the MSB, and the lowest number is the LSB
for that register (see the Register Map and Bit Descriptions
section and Table 17).

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

06479-030
SDIO I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 55. Serial Port Write Timing, Clock Stall Low

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK

SDIO I7 I6 I5 I4 I3 I2 I1 I0 DON'T CARE

06479-031

SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 56. 3-Wire Serial Port Read Timing, Clock Stall Low

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK
06479-032

SDIO I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 57. Serial Port Write Timing, Clock Stall High

INSTRUCTION CYCLE DATA TRANSFER CYCLE

CS

SCLK
06479-033

SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 58. 2-Wire Serial Port Read Timing, Clock Stall High

Rev. E | Page 48 of 64
Data Sheet AD9910

REGISTER MAP AND BIT DESCRIPTIONS

Table 17. Register Map
Register
Name Bit Range Default
(Serial (Internal Bit 7 Value1
Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
CFR1— 31:24 RAM RAM playback Open 0x00
Control enable destination
Function 23:16 Manual Inverse Open Internal profile control Select DDS 0x00
Register 1 OSK sinc filter sine output
(0x00) external enable
control
15:8 Load LRR Autoclear Autoclear Clear Clear Load ARR OSK Select auto 0x00
@ I/O digital phase digital phase @ I/O enable OSK
update ramp accumu- ramp accumu- update
accumu- lator accumu- lator
lator lator
7:0 Digital DAC REFCLK Aux DAC External Open SDIO input LSB first 0x00
power- power- input power- power- only
down down power- down down
down control
CFR2— 31:24 Open Enable 0x00
Control amplitude
Function scale from
Register 2 single tone
(0x01) profiles
23:16 Internal SYNC_CLK Digital ramp destination Digital Digital Digital Read 0x40
I/O enable ramp ramp ramp effective
update enable no-dwell no-dwell FTW
active high low
15:8 I/O update rate control Open PDCLK PDCLK TxEnable Open 0x08
enable invert invert
7:0 Matched Data Sync Parallel FM gain 0x20
latency assembler timing data port
enable hold last validation enable
value disable
CFR3— 31:24 Open DRV0[1:0] Open VCO SEL[2:0] 0x1F
Control 23:16 Open ICP[2:0] Open 0x3F
Function
15:8 REFCLK REFCLK Open PFD reset Open PLL enable 0x40
Register 3
input input
(0x02)
divider divider
bypass ResetB
7:0 N[6:0] Open 0x00
Auxiliary 31:24 Open 0x00
DAC 23:16 Open 0x00
Control
15:8 Open 0x00
(0x03)
7:0 FSC[7:0] 0x7F
I/O Update 31:24 I/O update rate[31:24] 0xFF
Rate (0x04) 23:16 I/O update rate[23:16] 0xFF
15:8 I/O update rate[15:8] 0xFF
7:0 I/O update rate[7:0] 0xFF
FTW— 31:24 Frequency tuning word[31:24] 0x00
Frequency 23:16 Frequency tuning word[23:16] 0x00
Tuning
15:8 Frequency tuning word[15:8] 0x00
Word
(0x07) 7:0 Frequency tuning word[7:0] 0x00

Rev. E | Page 49 of 64
AD9910 Data Sheet
Register
Name Bit Range Default
(Serial (Internal Bit 7 Value1
Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
POW— 15:8 Phase offset word[15:8] 0x00
Phase Offset 7:0 Phase offset word[7:0] 0x00
Word (0x08)
ASF— 31:24 Amplitude ramp rate[15:8] 0x00
Amplitude 23:16 Amplitude ramp rate[7:0] 0x00
Scale
15:8 Amplitude scale factor[13:6] 0x00
Factor
(0x09) 7:0 Amplitude scale factor[5:0] Amplitude step size[1:0] 0x00
Multichip 31:24 Sync validation delay[3:0] Sync Sync Sync Open 0x00
Sync (0x0A) receiver generator generator
enable enable polarity
23:16 Sync state preset value[5:0] Open 0x00
15:8 Output sync generator delay[4:0] Open 0x00
7:0 Input sync receiver delay[4:0] Open 0x00
Digital 63:56 Digital ramp upper limit[31:24] N/A
Ramp Limit 55:48 Digital ramp upper limit[23:16] N/A
(0x0B)
47:40 Digital ramp upper limit[15:8] N/A
39:32 Digital ramp upper limit[7:0] N/A
31:24 Digital ramp lower limit[31:24] N/A
23:16 Digital ramp lower limit[23:16] N/A
15:8 Digital ramp lower limit[15:8] N/A
7:0 Digital ramp lower limit[7:0] N/A
Digital 63:56 Digital ramp decrement step size[31:24] N/A
Ramp Step 55:48 Digital ramp decrement step size[23:16] N/A
Size (0x0C)
47:40 Digital ramp decrement step size[15:8] N/A
39:32 Digital ramp decrement step size[7:0] N/A
31:24 Digital ramp increment step size[31:24] N/A
23:16 Digital ramp increment step size[23:16] N/A
15:8 Digital ramp increment step size[15:8] N/A
7:0 Digital ramp increment step size[7:0] N/A
Digital 31:24 Digital ramp negative slope rate [15:8] N/A
Ramp Rate 23:16 Digital ramp negative slope rate[7:0] N/A
(0x0D)
15:8 Digital ramp positive slope rate[15:8] N/A
7:0 Digital ramp positive slope rate[7:0] N/A
Single Tone 63:56 Open Amplitude Scale Factor 0[13:8] 0x08
Profile 0 55:48 Amplitude Scale Factor 0[7:0] 0xB5
(0x0E)
47:40 Phase Offset Word 0[15:8] 0x00
39:32 Phase Offset Word 0[7:0] 0x00
31:24 Frequency Tuning Word 0[31:24] 0x00
23:16 Frequency Tuning Word 0[23:16] 0x00
15:8 Frequency Tuning Word 0[15:8] 0x00
7:0 Frequency Tuning Word 0[7:0] 0x00

Rev. E | Page 50 of 64
Data Sheet AD9910
Register
Name Bit Range Default
(Serial (Internal Bit 7 Value1
Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
RAM 63:56 Open 0x00
Profile 0 55:48 RAM Profile 0 address step rate[15:8] 0x00
(0x0E)
47:40 RAM Profile 0 address step rate[7:0] 0x00
39:32 RAM Profile 0 waveform end address[9:2] 0x00
31:24 RAM Profile 0 waveform Open 0x00
end address[1:0]
23:16 RAM Profile 0 waveform start address[9:2] 0x00
15:8 RAM Profile 0 waveform Open 0x00
start address[1:0]
7:0 Open No-dwell Open Zero- RAM Profile 0 mode control[2:0] 0x00
high crossing
Single Tone 63:56 Open Amplitude Scale Factor 1[13:8] 0x00
Profile 1 55:48 Amplitude Scale Factor 1[7:0] 0x00
(0x0F)
47:40 Phase Offset Word 1[15:8] 0x00
39:32 Phase Offset Word 1[7:0] 0x00
31:24 Frequency Tuning Word 1[31:24] 0x00
23:16 Frequency Tuning Word 1[23:16] 0x00
15:8 Frequency Tuning Word 1[15:8] 0x00
7:0 Frequency Tuning Word 1[7:0] 0x00
RAM 63:56 Open 0x00
Profile 1 55:48 RAM Profile 1 address step rate[15:8] 0x00
(0x0F)
47:40 RAM Profile 1 address step rate[7:0] 0x00
39:32 RAM Profile 1 waveform end address[9:2] 0x00
31:24 RAM Profile 1 waveform Open 0x00
end address[1:0]
23:16 RAM Profile 1 waveform start address[9:2] 0x00
15:8 RAM Profile 1 waveform Open 0x00
start address[1:0]
7:0 Open No-dwell Open Zero- RAM Profile 1 mode control[2:0] 0x00
high crossing
Single Tone 63:56 Open Amplitude Scale Factor 2[13:8] 0x00
Profile 2 55:48 Amplitude Scale Factor 2[7:0] 0x00
(0x10)
47:40 Phase Offset Word 2[15:8] 0x00
39:32 Phase Offset Word 2[7:0] 0x00
31:24 Frequency Tuning Word 2[31:24] 0x00
23:16 Frequency Tuning Word 2[23:16] 0x00
15:8 Frequency Tuning Word 2[15:8] 0x00
7:0 Frequency Tuning Word 2[7:0] 0x00
RAM 63:56 Open 0x00
Profile 2 55:48 RAM Profile 2 address step rate[15:8] 0x00
(0x10)
47:40 RAM Profile 2 address step rate[7:0] 0x00
39:32 RAM Profile 2 waveform end address[9:2] 0x00
31:24 RAM Profile 2 waveform Open 0x00
end address[1:0]
23:16 RAM Profile 2 waveform start address[9:2] 0x00
15:8 RAM Profile 2 waveform Open 0x00
start address[1:0]
7:0 Open No-dwell Open Zero- RAM Profile 2 mode control[2:0] 0x00
high crossing

Rev. E | Page 51 of 64
AD9910 Data Sheet
Register
Name Bit Range Default
(Serial (Internal Bit 7 Value1
Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
Single Tone 63:56 Open Amplitude Scale Factor 3[13:8] 0x00
Profile 3 55:48 Amplitude Scale Factor 3[7:0] 0x00
(0x11)
47:40 Phase Offset Word 3[15:8] 0x00
39:32 Phase Offset Word 3[7:0] 0x00
31:24 Frequency Tuning Word 3[31:24] 0x00
23:16 Frequency Tuning Word 3[23:16] 0x00
15:8 Frequency Tuning Word 3[15:8] 0x00
7:0 Frequency Tuning Word 3[7:0] 0x00
RAM 63:56 Open 0x00
Profile 3 55:48 RAM Profile 3 address step rate[15:8] 0x00
(0x11)
47:40 RAM Profile 3 address step rate[7:0] 0x00
39:32 RAM Profile 3 waveform end address[9:2] 0x00
RAM Profile 3 waveform Open 0x00
31:24
end address[1:0]
23:16 RAM Profile 3 waveform start address[9:2] 0x00
RAM Profile 3 waveform Open 0x00
15:8
start address[1:0]
Open No-dwell Open Zero- RAM Profile 3 mode control[2:0] 0x00
7:0
high crossing
Single Tone 63:56 Open Amplitude Scale Factor 4[13:8] 0x00
Profile 4 55:48 Amplitude Scale Factor 4[7:0] 0x00
(0x12)
47:40 Phase Offset Word 4[15:8] 0x00
39:32 Phase Offset Word 4[7:0] 0x00
31:24 Frequency Tuning Word 4[31:24] 0x00
23:16 Frequency Tuning Word 4[23:16] 0x00
15:8 Frequency Tuning Word 4[15:8] 0x00
7:0 Frequency Tuning Word 4[7:0] 0x00
RAM 63:56 Open 0x00
Profile 4 55:48 RAM Profile 4 address step rate[15:8] 0x00
(0x12)
47:40 RAM Profile 4 address step rate[7:0] 0x00
39:32 RAM Profile 4 waveform end address[9:2] 0x00
31:24 RAM Profile 4 waveform Open 0x00
end address[1:0]
23:16 RAM Profile 4 waveform start address[9:2] 0x00
15:8 RAM Profile 4 waveform Open 0x00
start address[1:0]
7:0 Open No-dwell Open Zero- RAM Profile 4 mode control[2:0] 0x00
high crossing
Single Tone 63:56 Open Amplitude Scale Factor 5[13:8] 0x00
Profile 5 55:48 Amplitude Scale Factor 5[7:0] 0x00
(0x13)
47:40 Phase Offset Word 5[15:8] 0x00
39:32 Phase Offset Word 5[7:0] 0x00
31:24 Frequency Tuning Word 5[31:24] 0x00
23:16 Frequency Tuning Word 5[23:16] 0x00
15:8 Frequency Tuning Word 5[15:8] 0x00
7:0 Frequency Tuning Word 5[7:0] 0x00

Rev. E | Page 52 of 64
Data Sheet AD9910
Register
Name Bit Range Default
(Serial (Internal Bit 7 Value1
Address) Address) (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) (Hex)
RAM 63:56 Open 0x00
Profile 5 55:48 RAM Profile 5 address step rate[15:8] 0x00
(0x13)
47:40 RAM Profile 5 address step rate[7:0] 0x00
39:32 RAM Profile 5 waveform end address[9:2] 0x00
RAM Profile 5 waveform Open 0x00
31:24
end address[1:0]
23:16 RAM Profile 5 waveform start address[9:2] 0x00
RAM Profile 5 waveform Open 0x00
15:8
start address[1:0]
Open No-dwell Open Zero- RAM Profile 5 mode control[2:0] 0x00
7:0
high crossing
Single Tone 63:56 Open Amplitude Scale Factor 6[13:8] 0x00
Profile 6 55:48 Amplitude Scale Factor 6[7:0] 0x00
(0x14)
47:40 Phase Offset Word 6[15:8] 0x00
39:32 Phase Offset Word 6[7:0] 0x00
31:24 Frequency Tuning Word 6[31:24] 0x00
23:16 Frequency Tuning Word 6[23:16] 0x00
15:8 Frequency Tuning Word 6[15:8] 0x00
7:0 Frequency Tuning Word 6[7:0] 0x00
RAM 63:56 Open 0x00
Profile 6 55:48 RAM Profile 6 address step rate[15:8] 0x00
(0x14)
47:40 RAM Profile 6 address step rate[7:0] 0x00
39:32 RAM Profile 6 waveform end address[9:2] 0x00
31:24 RAM Profile 6 waveform Open 0x00
end address[1:0]
23:16 RAM Profile 6 waveform start address[9:2] 0x00
15:8 AM Profile 6 waveform Open 0x00
start address[1:0]
7:0 Open No-dwell Open Zero- RAM Profile 6 mode control[2:0] 0x00
high crossing
Single Tone 63:56 Open Amplitude Scale Factor 7[13:8] 0x00
Profile 7 55:48 Amplitude Scale Factor 7[7:0] 0x00
(0x15)
47:40 Phase Offset Word 7[15:8] 0x00
39:32 Phase Offset Word 7[7:0] 0x00
31:24 Frequency Tuning Word 7[31:24] 0x00
23:16 Frequency Tuning Word 7[23:16] 0x00
15:8 Frequency Tuning Word 7[15:8] 0x00
7:0 Frequency Tuning Word 7[7:0] 0x00
RAM 63:56 Open 0x00
Profile 7 55:48 RAM Profile 7 address step rate[15:8] 0x00
(0x15)
47:40 RAM Profile 7 address step rate[7:0] 0x00
39:32 RAM Profile 7 waveform end address[9:2] 0x00
RAM Profile 7 waveform Open 0x00
31:24
end address[1:0]
23:16 RAM Profile 7 waveform start address[9:2] 0x00
RAM Profile 7 waveform Open 0x00
15:8
start address[1:0]
Open No-dwell Open Zero- RAM Profile 7 mode control[2:0] 0x00
7:0
high crossing
RAM (0x16) 31:0 RAM word[31:0] 0x00
1
N/A = not applicable.

Rev. E | Page 53 of 64
AD9910 Data Sheet
REGISTER BIT DESCRIPTIONS This section is organized in sequential order of the serial addresses
The serial I/O port registers span an address range of 0 to 23 of the registers. Each subheading includes the register name and
(0x00 to 0x16 in hexadecimal notation). This represents a total optional register mnemonic (in parentheses). Also given is the
of 24 registers. However, two of these registers are unused, serial address in hexadecimal format and the number of bytes
yielding a total of 22 available registers. The unused registers are assigned to the register.
Register 5 and Register 6 (0x05 and 0x06, respectively). Following each subheading is a table containing the individual
The number of bytes assigned to the registers varies. That is, the bit descriptions for that particular register. The location of the
registers are not of uniform depth; each contains the number of bit(s) in the register is indicated by a single number or a pair of
bytes necessary for its particular function. Additionally, the numbers separated by a colon; that is, a pair of numbers (A:B)
registers are assigned names according to their functionality. In indicates a range of bits from the most significant (A) to the
some cases, a register is given a mnemonic descriptor. For least significant (B). For example, 5:2 implies Bit Position 5
example, the register at Serial Address 0x00 is named Control down to Bit Position 2, inclusive, with Bit 0 identifying the LSB
Function Register 1 and is assigned the mnemonic CFR1. of the register.

The following section provides a detailed description of each bit Unless otherwise stated, programmed bits are not transferred to
in the AD9910 register map. For cases in which a group of bits their internal destinations until the assertion of the I/O_UPDATE
serves a specific function, the entire group is considered a pin or a profile change.
binary word and described in aggregate.

Control Function Register 1 (CFR1)—Address 0x00

Four bytes are assigned to this register.

Table 18. Bit Description for CFR1

Bit(s) Mnemonic Description
31 RAM enable 0 = disables RAM functionality (default).
1 = enables RAM functionality (required for both load/retrieve and playback operation).
30:29 RAM playback destination See Table 12 for details; default is 00b.
28:24 Open
23 Manual OSK external Ineffective unless CFR1[9:8] = 10b.
control 0 = OSK pin inoperative (default).
1 = OSK pin enabled for manual OSK control (see Output Shift Keying (OSK) section for
details).
22 Inverse sinc filter enable 0 = inverse sinc filter bypassed (default).
1 = inverse sinc filter active.
21 Open
20:17 Internal profile control Ineffective unless CFR1[31] = 1. These bits are effective without the need for an I/O update.
See Table 14 for details. Default is 0000b.
16 Select DDS sine output 0 = cosine output of the DDS is selected (default).
1 = sine output of the DDS is selected.
15 Load LRR @ I/O update Ineffective unless CFR2[19] = 1.
0 = normal operation of the digital ramp timer (default).
1 = digital ramp timer loaded any time I/O_UPDATE is asserted or a PROFILE[2:0] change
occurs.
14 Autoclear digital ramp 0 = normal operation of the DRG accumulator (default).
accumulator 1 = the ramp accumulator is reset for one cycle of the DDS clock after which the accumula-
tor automatically resumes normal operation. As long as this bit remains set, the ramp
accumulator is momentarily reset each time an I/O_UPDATE is asserted or a PROFILE[2:0]
change occurs. This bit is synchronized with either an I/O _UPDATE or a PROFILE[2:0]
change and the next rising edge of SYNC_CLK.
13 Autoclear phase 0 = normal operation of the DDS phase accumulator (default).
accumulator 1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a
profile change occurs.

Rev. E | Page 54 of 64
Data Sheet AD9910
Bit(s) Mnemonic Description
12 Clear digital ramp 0 = normal operation of the DRG accumulator (default).
accumulator 1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset
as long as this bit remains set. This bit is synchronized with either an I/O_UPDATE or a
PROFILE[2:0] change and the next rising edge of SYNC_CLK.
11 Clear phase accumulator 0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator.
10 Load ARR @ I/O update Ineffective unless CFR1[9:8] = 11b.
0 = normal operation of the OSK amplitude ramp rate timer (default).
1 = OSK amplitude ramp rate timer reloaded anytime I/O_UPDATE is asserted or a
PROFILE[2:0] change occurs.
9 OSK enable The output shift keying enable bit.
0 = OSK disabled (default).
1 = OSK enabled.
8 Select auto OSK Ineffective unless CFR1[9] = 1.
0 = manual OSK enabled (default).
1 = automatic OSK enabled.
7 Digital power-down This bit is effective without the need for an I/O update.
0 = clock signals to the digital core are active (default).
1 = clock signals to the digital core are disabled.
6 DAC power-down 0 = DAC clock signals and bias circuits are active (default).
1 = DAC clock signals and bias circuits are disabled.
5 REFCLK input power-down This bit is effective without the need for an I/O update.
0 = REFCLK input circuits and PLL are active (default).
1 = REFCLK input circuits and PLL are disabled.
4 Auxiliary DAC power-down 0 = auxiliary DAC clock signals and bias circuits are active (default).
1 = auxiliary DAC clock signals and bias circuits are disabled.
3 External power-down 0 = assertion of the EXT_PWR_DWN pin affects full power-down (default).
control 1 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down.
2 Open
1 SDIO input only 0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming
mode (default).
1 = configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial
programming mode.
0 LSB first 0 = configures the serial I/O port for MSB-first format (default).
1 = configures the serial I/O port for LSB-first format.

Rev. E | Page 55 of 64
AD9910 Data Sheet
Control Function Register 2 (CFR2)—Address 0x01
Four bytes are assigned to this register.

Table 19. Bit Descriptions for CFR2

Bit(s) Mnemonic Description
31:25 Open
24 Enable amplitude scale Ineffective if CFR2[19 ] = 1 or CFR1[31] = 1 or CFR1[9] = 1.
from single tone profiles 0 = the amplitude scaler is bypassed and shut down for power conservation (default).
1 = the amplitude is scaled by the ASF from the active profile.
23 Internal I/O update active This bit is effective without the need for an I/O update.
0 = serial I/O programming is synchronized with the external assertion of the
I/O_UPDATE pin, which is configured as an input pin (default).
1 = serial I/O programming is synchronized with an internally generated I/O update
signal (the internally generated signal appears at the I/O_UPDATE pin, which is
configured as an output pin).
22 SYNC_CLK enable 0 = the SYNC_CLK pin is disabled; static Logic 0 output.
1 = the SYNC_CLK pin generates a clock signal at ¼ fSYSCLK; used for synchronization of the
serial I/O port (default).
21:20 Digital ramp destination See Table 11 for details. Default is 00b. See the Digital Ramp Generator (DRG) section for
details.
19 Digital ramp enable 0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
18 Digital ramp no-dwell high See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
17 Digital ramp no-dwell low See the Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
16 Read effective FTW 0 = a serial I/O port read operation of the FTW register reports the contents of the FTW
register (default).
1 = a serial I/O port read operation of the FTW register reports the actual 32-bit word
appearing at the input to the DDS phase accumulator.
15:14 I/O update rate control Ineffective unless CFR2[23] = 1. Sets the prescale ratio of the divider that clocks the auto I/O
update timer as follows:
00 = divide-by-1 (default).
01 = divide-by-2.
10 = divide-by-4.
11 = divide-by-8.
13:12 Open
11 PDCLK enable 0 = the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal
continues to operate and provide timing to the data assembler.
1 = the internal PDCLK signal appears at the PDCLK pin (default).
10 PDCLK invert 0 = normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1 = inverted PDCLK polarity.
9 TxEnable invert 0 = no inversion.
1 = inversion.
8 Open
7 Matched latency enable 0 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output in the order listed (default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output simultaneously.

Rev. E | Page 56 of 64
Data Sheet AD9910
Bit(s) Mnemonic Description
6 Data assembler hold last Ineffective unless CFR2[4] = 1.
value 0 = the data assembler of the parallel data port internally forces zeros on the data path
and ignores the signals on the D[15:0] and F[1:0] pins while the TxENABLE pin is Logic 0
(default). This implies that the destination of the data at the parallel data port is
amplitude when TxENABLE is Logic 0.
1 = the data assembler of the parallel data port internally forces the last value received
on the D[15:0] and F[1:0] pins while the TxENABLE pin is Logic 1.
5 Sync timing validation 0 = enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization
disable pulse sampling error.
1 = the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).
4 Parallel data port enable See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
3:0 FM gain See the Parallel Data Port Modulation Mode section for more details. Default is 0000b.

Control Function Register 3 (CFR3)—Address 0x02

Four bytes are assigned to this register.

Table 20. Bit Descriptions for CFR3

Bit(s) Mnemonic Description
31:30 Open
29:28 DRV0 Controls the REFCLK_OUT pin (see Table 7 for details); default is 01b.
27 Open
26:24 VCO SEL Selects the frequency band of the REFCLK PLL VCO (see Table 8 for details); default is 111b.
23:22 Open
21:19 ICP Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 111b.
18:16 Open
15 REFCLK input divider bypass 0 = input divider is selected (default).
1 = input divider is bypassed.
14 REFCLK input divider ResetB 0 = input divider is reset.
1 = input divider operates normally (default).
13:11 Open
10 PFD reset 0 = normal operation (default).
1 = phase detector disabled.
9 Open
8 PLL enable 0 = REFCLK PLL bypassed (default).
1 = REFCLK PLL enabled.
7:1 N This 7-bit number is the divide modulus of the REFCLK PLL feedback divider; default is
0000000b.
0 Open

Auxiliary DAC Control Register—Address 0x03

Four bytes are assigned to this register.

Table 21. Bit Descriptions for DAC Control Register

Bit(s) Mnemonic Description
31:8 Open
7:0 FSC This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary
DAC section); default is 0x7F.

Rev. E | Page 57 of 64
AD9910 Data Sheet
I/O Update Rate Register—Address 0x04
Four bytes are assigned to this register. This register is effective without the need for an I/O update.

Table 22. Bit Descriptions for I/O Update Rate Register

Bit(s) Mnemonic Description
31:0 I/O update rate Ineffective unless CFR2[23] = 1. This 32-bit number controls the automatic I/O update
rate (see the Automatic I/O Update section for details); default is 0xFFFFFFFF.

Frequency Tuning Word Register (FTW)—Address 0x07

Four bytes are assigned to this register.

Table 23. Bit Descriptions for FTW Register

Bit(s) Mnemonic Description
31:0 Frequency tuning word 32-bit frequency tuning word.

Phase Offset Word Register (POW)—Address 0x08

Two bytes are assigned to this register.

Table 24. Bit Descriptions for POW Register

Bit(s) Mnemonic Description
15:0 Phase offset word 16-bit phase offset word.

Amplitude Scale Factor Register (ASF)—Address 0x09

Four bytes are assigned to this register.

Table 25. Bit Descriptions for ASF Register

Bit(s) Mnemonic Description
31:16 Amplitude ramp rate 16-bit amplitude ramp rate value. Effective only if CFR1[9:8] = 11b; see the Output Shift
Keying (OSK) section for details.
15:2 Amplitude scale factor 14-bit amplitude scale factor.
1:0 Amplitude step size Effective only if CFR1[9:8] = 11b; see the Output Shift Keying (OSK) section for details.

Rev. E | Page 58 of 64
Data Sheet AD9910
Multichip Sync Register—Address 0x0A
Four bytes are assigned to this register.

Table 26. Multichip Sync Register

Bit(s) Mnemonic Description
31:28 Sync validation delay This 4-bit number sets the timing skew (in ~75ps increments) between SYSCLK and the
delayed SYNC_INx signal for the sync validation block in the sync receiver. Default is 0000b.
27 Sync receiver enable 0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
26 Sync generator enable 0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
25 Sync generator polarity 0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
24 Open
23:18 Sync state preset value This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 000000b.
17:16 Open
15:11 Output sync generator This 5-bit number sets the output delay (in ~75 ps increments) of the sync generator.
delay Default is 00000b.
10:8 Open
7:3 Input sync receiver delay This 5-bit number sets the input delay (in ~75 ps increments) of the sync receiver. Default is
00000b.
2:0 Open

Digital Ramp Limit Register—Address 0x0B

Eight bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.

Table 27. Bit Descriptions for Digital Ramp Limit Register

Bit(s) Mnemonic Description
63:32 Digital ramp upper limit 32-bit digital ramp upper limit value.
31:0 Digital ramp lower limit 32-bit digital ramp lower limit value.

Digital Ramp Step Size Register—Address 0x0C

Eight bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.

Table 28. Bit Descriptions for Digital Ramp Step Size Register
Bit(s) Mnemonic Description
63:32 Digital ramp decrement 32-bit digital ramp decrement step size value.
step size
31:0 Digital ramp increment 32-bit digital ramp increment step size value.
step size

Digital Ramp Rate Register—Address 0x0D

Four bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.

Table 29. Bit Descriptions for Digital Ramp Rate Register

Bit(s) Mnemonic Description
31:16 Digital ramp negative slope 16-bit digital ramp negative slope value that defines the time interval between decrement
rate values.
15:0 Digital ramp positive slope 16-bit digital ramp positive slope value that defines the time interval between increment
rate values.
Rev. E | Page 59 of 64
AD9910 Data Sheet
Profile Registers In normal operation, the active profile register is selected using
the external PROFILE[2:0] pins. However, in the specific case
There are eight consecutive serial I/O addresses (Address 0x0E
when CFR1[31] = 1 and CFR1[20:17] ≠ 0000b, the active profile
to Address 0x015) dedicated to device profiles. All eight profile
is selected automatically (see the RAM Ramp-Up Internal
registers are either single tone profiles or RAM profiles. RAM
Profile Control Mode section).
profiles are in effect when CFR1[31] = 1. Single tone profiles are
in effect when CFR1[31] = 0, CFR2[19] = 0, and CFR2[4] = 0.

Profile 0 to Profile 7, Single Tone Registers—Address 0x0E to Address 0x15

Eight bytes are assigned to each register.

Table 30. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register
Bit(s) Mnemonic Description
63:62 Open
61:48 Amplitude scale factor This 14-bit number controls the DDS output amplitude.
47:32 Phase offset word This 16-bit number controls the DDS phase offset.
31:0 Frequency tuning word This 32-bit number controls the DDS frequency.

RAM Profile 0 to RAM Profile 7, Control Registers—Address 0x0E to Address 0x15

Eight bytes are assigned to each register.

Table 31. Bit Descriptions for Profile 0 to Profile 7 RAM Register

Bit(s) Mnemonic Description
63:56 Open
55:40 Address step rate 16-bit address step rate value.
39:30 Waveform end address 10-bit waveform end address.
29:24 Open
23:14 Waveform start address 10-bit waveform start address.
13:6 Open
5 No-dwell high Effective only when the RAM mode is in ramp-up.
0 = when the RAM state machine reaches the end address, it halts.
1 = when the RAM state machines reaches the end address, it jumps to the start address
and halts.
4 Open
3 Zero-crossing Effective only when in RAM mode, direct switch.
0 = zero-crossing function disabled.
1 = zero-crossing function enabled.
2:0 RAM mode control See Table 13 for details.

RAM Register—Address 0x16

Four bytes are assigned to the RAM register.

Table 32. Bit Descriptions for RAM Register

Bit(s) Mnemonic Description
31:0 RAM word The start and end addresses in the RAM Profile 0 to RAM Profile 7 control registers define
the number of 32-bit words (1 minimum, 1024 maximum) to be written to the RAM register.

Rev. E | Page 60 of 64
Data Sheet AD9910

OUTLINE DIMENSIONS
0.75 1.20 16.00 BSC SQ
MAX
0.60 14.00 BSC SQ
0.45 100 76 76 100
1 75 75 1
PIN 1

TOP VIEW EXPOSED 5.00 SQ

(PINS DOWN) PAD

1.05 0° MIN
0.20 BOTTOM VIEW
1.00 0.09 (PINS UP)
25 51 51 25
0.95 7° 26 50 50 26
3.5°
0.15 0° VIEW A 0.50 BSC 0.27
SEATING LEAD PITCH
0.05 PLANE 0.08 MAX 0.22
COPLANARITY 0.17
FOR PROPER CONNECTION OF
VIEW A THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND

042209-A
ROTATED 90° CCW FUNCTION DESCRIPTIONS
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD SECTION OF THIS DATA SHEET.

Figure 59. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-4)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9910BSVZ –40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-4
AD9910BSVZ-REEL –40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-4
AD9910/PCBZ Evaluation Board
1
Z = RoHS Compliant Part.

Rev. E | Page 61 of 64
AD9910 Data Sheet

NOTES

Rev. E | Page 62 of 64
Data Sheet AD9910

NOTES

Rev. E | Page 63 of 64
AD9910 Data Sheet

NOTES

©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06479-0-10/16(E)

Rev. E | Page 64 of 64
Mouser Electronics

Authorized Distributor

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Analog Devices Inc.:

AD9910/PCBZ AD9910BSVZ-REEL AD9910BSVZ