a 16-Bit/18-Bit, 16 3 FS

PCM Audio DACs

AD1851/AD1861
FEATURES FUNCTIONAL BLOCK DIAGRAM
110 dB SNR
Fast Settling Permits 163 Oversampling
–VS 1 +VS
63 V Output LATCH DAC
16

Optional Trim Allows Super-Linear Performance DGND 2 15 TRIM

65 V Operation +VL 3 SERIAL

14 MSB ADJ
INPUT
16-Pin Plastic DIP and SOIC Packages REGISTER
NC 4
Pin-Compatible with AD1856 & AD1860 Audio DACs IOUT 13 IOUT

2s Complement, Serial Input CLK 5 12 AGND

CONTROL
LOGIC
APPLICATIONS LE 6 11 SJ

High-End Compact Disc Players 7 RF

DATA 10
Digital Audio Amplifiers
AD1851/ VOUT
DAT Recorders and Players NC 8
AD1861
9

Synthesizers and Keyboards

NC = NO CONNECT

PRODUCT DESCRIPTION The critical specifications of THD+N and signal-to-noise ratio

The AD1851/AD1861 is a monolithic PCM audio DAC. The are 100% tested for all devices.
AD1851 is a 16-bit device, while the AD1861 is an 18-bit de- The AD1851/AD1861 operates with ± 5 V power supplies, mak-
vice. Each device provides a voltage output amplifier, DAC, ing it suitable for home use markets. The digital supply, VL, can
serial-to-parallel register and voltage reference. The digital por- be separated from the analog supplies, VS and –VS, for reduced
tion of the AD1851/AD1861 is fabricated with CMOS logic digital crosstalk. Separate analog and digital ground pins are
elements that are provided by Analog Devices’ 2 µm ABCMOS also provided. Power dissipation is 100 mW typical.
process. The analog portion of the AD1851/AD1861 is fabri-
cated with bipolar and MOS devices as well as thin-film The AD1851/AD1861 is available in either a 16-pin plastic DIP
resistors. or a 16-pin plastic SOIC package. Both packages incorporate
the industry standard pinout found on the AD1856 and
This combination of circuit elements, as well as careful design AD1860 PCM audio DACs. As a result, the AD1851/AD1861
and layout techniques, results in high performance audio play- is a drop-in replacement for designs where ± 5 V supplies have
back. Laser-trimming of the linearity error affords low total har- been used with the AD1856/AD1860. Operation is guaranteed
monic distortion. An optional linearity trim pin is provided to over the temperature range of –25°C to +70°C and over the
allow residual differential linearity error at midscale to be elimi- voltage supply range of ± 4.75 V to ± 5.25 V.
nated. This feature is particularly valuable for low distortion
reproductions of low amplitude signals. Output glitch is also PRODUCT HIGHLIGHTS
small, contributing to the overall high level of performance. The l. AD1851 16-bit resolution provides 96 dB dynamic range.
output amplifier achieves fast settling and high slew rates, pro- AD1861 18-bit resolution provides 108 dB dynamic range.
viding a full ± 3 V signal at load currents up to 8 mA. When
used in current output mode, the AD1851/AD1861 provides a 2. No external components are required.
± 1 mA output signal. The output amplifier is short circuit 3. Operates with ± 5 V supplies.
protected and can withstand indefinite shorts to ground.
4. Space saving 16-pin SOIC and plastic DIP packages.
The serial input interface consists of the clock, data and latch
5. 100 mW power dissipation.
enable pins. The serial 2s complement data word is clocked into
the DAC, MSB first, by the external clock. The latch enable 6. High input clock data rates and 1.5 µs settling time permits
signal transfers the input word from the internal serial input 23, 43, 83 and 163 oversampling.
register to the parallel DAC input register. The AD1851 input 7. ± 3 V or ± 1 mA output capability.
clock can support a 12.5 MHz data rate, while the AD1861 in-
8. THD + Noise and SNR are 100% tested.
put clock can support a 13.5 MHz data rate. This serial input
port is compatible with second generation digital filter chips 9. Pin-compatible with AD1856 & AD1860 PCM audio DACs.
used in consumer audio products. These filters operate at over-
sampling rates of 23, 43, 83 and 163 sampling frequencies.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD1851/AD1861–SPECIFICATIONS (T @ +258C and 65 V supplies, unless otherwise noted) A

Min Typ Max Units

DIGITAL INPUTS
VIH 2.0 +VL V
VIL 0.8 V
IIH, VIH = VL 1.0 µA
IIL, VIL = 0.4 –10 µA
ACCURACY
Gain Error ±1 %
Midscale Output Voltage ± 10 mV
DRIFT (0°C to +70°C)
Total Drift ± 25 ppm of FSR/°C
Bipolar Zero Drift ±4 ppm of FSR/°C
SETTLING TIME (To ± 0.0015% of FSR)
Voltage Output
6 V Step 1.5 µs
1 LSB Step 1.0 µs
Slew Rate 9 V/µs
Current Output
1 mA Step 10 Ω to 100 Ω Load 350 ns
1 kΩ Load 350 ns
OUTPUT
Voltage Output Configuration
Bipolar Range 62.88 ± 3.0 63.12 V
Output Current ±8 mA
Output Impedance 0.1 Ω
Short Circuit Duration Indefinite to Common
Current Output Configuration
Bipolar Range (± 30%) ± 1.0 mA
Output Impedance (± 30%) 1.7 kΩ
POWER SUPPLY
Voltage
+VL and +VS 4.75 5.25 V
–VS –5.25 –4.75 V
TEMPERATURE RANGE
Specification 0 +25 +70 °C
Operation –25 +70 °C
Storage –60 +100 °C
WARM-UP TIME 1 min
Specifications subject to change without notice.

–VS 1 16-BIT 16-BIT 16 +VS –VS 1 16-BIT 16-BIT 16 +VS

LATCH DAC LATCH DAC

DGND 2 15 TRIM DGND 2 15 TRIM

+VL SERIAL +VL SERIAL

3 INPUT 14 MSB ADJ 3 INPUT 14 MSB ADJ
REGISTER REGISTER
NC 4 IOUT 13 IOUT NC 4 IOUT 13 IOUT

CLK 5 12 AGND CLK 5 12 AGND

CONTROL CONTROL
LOGIC LOGIC
LE 6 11 SJ LE 6 11 SJ

DATA 7 10 RF DATA 7 10 RF

VOUT VOUT
NC 8 AD1851 9 NC 8 AD1851 9

NC = NO CONNECT NC = NO CONNECT

AD1851 Functional Block Diagram AD1861 Functional Block Diagram

–2– REV. A
AD1851 AD1851/AD1861
Min Typ Max Units
RESOLUTION 16 Bits
TOTAL HARMONIC DISTORTION + NOISE
0 dB, 990.5 Hz
AD1851N-J, R-J 0.003 0.004 %
AD1851N, R 0.004 0.008 %
–20 dB, 990.5 Hz
AD1851N-J, R-J 0.009 0.016 %
AD1851N, R 0.009 0.040 %
–60 dB, 990.5 Hz
AD1851N-J, R-J 0.9 1.6 %
AD1851N, R 0.9 4.0 %
D-RANGE* (With A-Weight Filter)
–60 dB, 990.5 Hz AD1851N, R 88 dB
AD1851N-J, R-J 96 dB
SIGNAL-TO-NOISE RATIO 107 110 dB
MAXIMUM CLOCK INPUT FREQUENCY 12.5 MHz
ACCURACY
Differential Linearity Error ± 0.001 % of FSR
MONOTONICITY 14 Bits
POWER SUPPLY
Current
+I 10.0 13.0 mA
–I –10.0 –15.0 mA
Power Dissipation 100 mW

AD1861
Min Typ Max Units
RESOLUTION 18 Bits
TOTAL HARMONIC DISTORTION + NOISE
0 dB, 990.5 Hz
AD1861N-J, R-J 0.003 0.004 %
AD1861N, R 0.004 0.008 %
–20 dB, 990.5 Hz
AD1861N-J, R-J 0.009 0.016 %
AD1861N, R 0.009 0.040 %
–60 dB, 990.5 Hz
AD1861N-J, R-J 0.9 1.6 %
AD1861N, R 0.9 4.0 %
D-RANGE* (With A-Weight Filter)
–60 dB, 990.5 Hz AD1861N, R 88 dB
AD1861N-J, R-J 96 dB
SIGNAL-TO-NOISE RATIO 107 110 dB
MAXIMUM CLOCK INPUT FREQUENCY 13.5 MHz
ACCURACY
Differential Linearity Error ± 0.001 % of FSR
MONOTONICITY 15 Bits
POWER SUPPLY
Current
+I 10.0 13.0 mA
–I –10.0 –15.0 mA
Power Dissipation 100 mW
*Tested in accordance with EIAJ Test Standard CP-307.
Specifications subject to change without notice.

REV. A –3–
AD1851/AD1861
ABSOLUTE MAXIMUM RATINGS* PIN DESCRIPTIONS
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V 1 –VS Analog Negative Power Supply
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –6.50 V to 0 V 2 DGND Logic Ground
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL 3 VL Logic Positive Power Supply
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V 4 NC No Connection
Short Circuit . . . . . . . . . . . . . . . . . Indefinite Short to Ground 5 CLK Clock Input
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec 6 LE Latch Enable Input
Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C 7 DATA Serial Data Input
8 NC No Internal Connection*
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional 9 VOUT Voltage Output
operation of the device at these or any other conditions above those indicated in the 10 RF Feedback Resistor
operational section of this specification is not implied. Exposure to absolute 11 SJ Summing Junction
maximum rating conditions for extended periods may affect device reliability. 12 AGND Analog Ground
13 IOUT Current Output
ORDERING GUIDE 14 MSB ADJ MSB Adjustment Terminal
15 TRIM MSB Trimming Potentiometer Terminal
Package
16 VS Analog Positive Power Supply
Model Resolution THD + N Option*
*Pin 8 has no internal connection; -V L from AD1856 or AD1860 socket can be
AD1851N 16 Bits 0.008% N-16 safely applied.
AD1851N-J 16 Bits 0.004% N-16
AD1851R 16 Bits 0.008% R-16
AD1851R-J 16 Bits 0.004% R-16
AD1861N 18 Bits 0.008% N-16
AD1861N-J 18 Bits 0.004% N-16
AD1861R 18 Bits 0.008% R-16
AD1861R-J 18 Bits 0.004% R-16
*N = Plastic DIP Package; R = Small Outline (SOIC) Package.

CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
WARNING!
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted. ESD SENSITIVE DEVICE

Typical Performance

10

175

150
1

125 –60dB
THD+N – %
PD – mW

100
0.1

75

50 0.01
–20dB
25
0dB
0.001
2 4 6 8 10 12 14 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
CLOCK FREQUENCY – MHz
TEMPERATURE – °C

Power Dissipation vs. Clock Frequency THD vs. Temperature

–4– REV. A
 AD1851/AD1861
TOTAL HARMONIC DISTORTION RF
Total harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val- IOUT DAC
REFERENCE
ues of the first 19 harmonics and noise to the value of the funda-
mental input frequency. It is usually expressed in percent (%). AUDIO
OUTPUT
THD+N is a measure of the magnitude and distribution of lin- INPUT LATCH
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing on the amplitude of the output signal. Therefore, to be most
SERIAL-TO-PARALLEL
useful, THD+N should be specified for both large (0 dB) and CONVERSION
small signal amplitudes (–20 dB and –60 dB). CLOCK LE DATA
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. This specification, therefore, provides a Figure 1. AD1851/AD1861 Functional Block Diagram
direct method to classify and choose an audio DAC for a
desired level of performance. FUNCTIONAL DESCRIPTION
The AD1851/AD1861 is a complete monolithic PCM audio
SETTLING TIME DAC. No additional external components are required for op-
Settling time is the time required for the output of the DAC to eration. As shown in Figure 1 above, each chip contains a volt-
reach and remain within a specified error band about its final age reference, an output amplifier, a DAC, an input latch and a
value, measured from the digital input transition. It is a primary parallel input register.
measure of dynamic performance. The voltage reference consists of a bandgap circuit and buffer
amplifier. This combination of elements produces a reference
MIDSCALE ERROR voltage that is unaffected by changes in temperature and age.
Midscale error, or bipolar zero error, is the deviation of the ac- The DAC output voltage, which is derived from the reference
tual analog output from the ideal output (0 V) when the 2s voltage, is also unaffected by these environmental changes.
complement input code representing half scale is loaded in the
The output amplifier uses both MOS and bipolar devices to
input register.
produce low offset, high slew rate and optimum settling time.
When combined with the on-chip feedback resistor, the output
D-RANGE DISTORTION
op amp converts the output current of the AD1851/AD1861 to
D-range distortion is equal to the value of the total harmonic
a voltage output.
distortion + noise (THD+N) plus 60 dB when a signal level of
–60 dB below full scale is reproduced. D-range is tested with a The DAC uses a combination of segmented decoder and R-2R
1 kHz input sine wave. This is measured with a standard A- architecture to achieve consistent linearity and differential lin-
weight filter as specified by EIAJ Standard CP-307. earity. The resistors which form the ladder structure are fabri-
cated with silicon chromium thin film. Laser-trimming of these
SIGNAL-TO-NOISE RATIO resistors further reduces linearity error, resulting in low output
The signal-to-noise ratio (SNR) is defined as the ratio of the distortion.
amplitude of the output when a full-scale output is present to The input register and serial-to-parallel converter are fabricated
the amplitude of the output with no signal present. This is mea- with CMOS logic gates. These gates allow the achievement of
sured with a standard A-weight filter as specified by EIAJ fast switching speeds and low power consumption. This contrib-
Standard CP-307. utes to the overall low power dissipation of the AD1851/
AD1861.

REV. A –5–
AD1851/AD1861
However, three separate voltage supplies are not necessary for
Analog Circuit Considerations good circuit performance. For example, Figure 3 illustrates a
system where only a single positive and a single negative supply
GROUNDING RECOMMENDATIONS are available.
The AD1851/AD1861 has two ground pins, designated Analog In this example, the positive logic and positive analog supplies
and Digital ground. The analog ground pin is the “high quality” must both be connected to +5 V, while the negative analog sup-
ground reference point for the device. The analog ground pin ply will be connected to –5 V. Performance would benefit from
should be connected to the analog common point in the system. a measure of isolation between the supplies introduced by using
The output load should also be connected to that same point. simple low pass filters in the individual power supply leads.
The digital ground pin returns ground current from the digital
logic portions of the AD1851/AD1861 circuitry. This pin +5V +5V

should be connected to the digital common point in the system.

3 16
As illustrated in Figure 2, the analog and digital grounds should +VL +VS
be connected together at one point in the system.
AD1851/AD1861
+ 5V +5V –VS
DGND AGND
2 1 12
3 16
+VL +VS DIGITAL ANALOG
GROUND GROUND
AD1851/AD1861 –5V

DGND –VS AGND

Figure 3. Alternate Recommended Schematic
2 1 12
As with most linear circuits, changes in the power supplies will
DIGITAL ANALOG affect the output of the DAC. Analog Devices recommends that
GROUND GROUND well regulated power supplies with less than 1% ripple be incor-
– 5V
porated into the design of any system using the AD1851/AD1861.
Figure 2. Recommended Circuit Schematic OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
POWER SUPPLIES AND DECOUPLING linearity error around midscale to be eliminated. This error is
The AD1851/AD1861 has three power supply input pins. The especially important when low amplitude signals are being re-
± VS supplies provide the supply voltages to operate the linear produced. In those cases, as the signal amplitude decreases, the
portions of the DAC including the voltage reference, output am- ratio of the midscale differential linearity error to the signal am-
plifier and control amplifier. The ± VS supplies are designed to plitude increases, thereby increasing THD.
operate at ± 5 V.
Therefore, for best performance at low output levels, the op-
The +VL supply operates the digital portions of the chip includ- tional MSB adjust circuitry shown in Figure 4 may be used to
ing the input shift register and the input latching circuitry. The improve performance. The adjustment should be made with a
+VL supply is designed to operate at +5 V. small signal input (–20 dB or –60 dB).
Decoupling capacitors should be used on all power supply pins.
TRIM –VS
Furthermore, good engineering practice suggests that these ca- 470kΩ 100kΩ 200kΩ

pacitors be placed as close as possible to the package pins as 15 1

well as to the common points. The logic supply, +VL, should be

decoupled to digital common, while the analog supplies, ± VS, 14
should be decoupled to analog common.
MSB
The use of three separate power supplies will reduce feedthrough ADJUST
from the digital portion of the system to the linear portion of the
system, thus contributing to improved performance. Figure 4. Optional THD Adjust Circuit

–6– REV. A
 AD1851/AD1861
AD1851 DIGITAL CIRCUIT CONSIDERATIONS AD1861 DIGITAL CIRCUIT CONSIDERATIONS
AD1851 Input Data AD1861 Input Data
Data is transmitted to the AD1851 in a bit stream composed of Data is transmitted to the AD1861 in a bit stream composed of
16-bit words with a serial, MSB first format. Three signals 18-bit words with a serial, MSB first format. Three signals
must be present to achieve proper operation. They are the must be present to achieve proper operation. They are the
Data, Clock and Latch Enable (LE) signals. Input data bits are Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock clocked into the input register on the rising edge of the Clock
signal. The LSB is clocked in on the 16th clock pulse. When all signal. The LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 5 illustrates the general signal require- the DAC input. Figure 7 illustrates the general signal require-
ments for data transfer to the AD1851. ments for data transfer to the AD1861.

CLOCK
CLOCK

AAAAAAAAA AAAAAAAAA
M L M L
DATA S S S S
B B DATA B B

LATCH LATCH

Figure 5. Signal Requirements for AD1851 Figure 7. Signal Requirements for AD1861
Figure 6 illustrates the specific timing requirements that must Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop- be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1851 are both TTL and 5 V erly. The input pins of the AD1861 are both TTL and 5 V
CMOS compatible. The input requirements illustrated in Fig- CMOS compatible. The input requirements illustrated in Fig-
ures 5 and 6 are compatible with data outputs provided by ures 7 and 8 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems. popular DSP filter chips used in digital audio playback systems.
The AD1851 input clock can run at a 12.5 MHz rate. This The AD1861 input clock can run at a 13.5 MHz rate. This
clock rate will allow data transfer rates for 23, 43 or 83 or clock rate will allow data transfer rates for 23, 43 or 83 or
163 oversampling reconstructions. 163 oversampling reconstructions.
>30ns
>30ns

DATA
DATA

>15ns >15ns
>15ns >15ns
>40ns
>40ns

CLOCK CLOCK

>30ns >30ns >30ns >30ns

>15ns >15ns
>80.0ns
>74.1ns

LATCH LATCH

>40ns >40ns >40ns >40ns

Figure 6. Timing Relationships of AD1851 Input Signals Figure 8. Timing Relationships of AD1861 Input Signals

REV. A –7–
AD1851/AD1861
APPLICATIONS
Figures 9 through 12 show connection diagrams for the
AD1851 and AD1861 and the Yamaha YM3434 and the NPC
SM5813AP/APT digital filter chips.

LEFT
CLK +5V CLK
LOW OUTPUT
LATCH OUT PASS
X1 ST 16/18 DLO FILTER
DATA AD1851
BCO

YM3434 WCO

DRO DATA
LOW
LATCH OUT PASS
FILTER
CLK AD1851 RIGHT
OUTPUT

Figure 9. AD1851 with Yamaha YM3434 Digital Filter

+5V LEFT
CLK CLK
LOW OUTPUT
LATCH OUT PASS
X1 ST 16/18 FILTER
DLO DATA AD1861
BCO

YM3434 WCO

DRO DATA
LOW
LATCH OUT PASS
FILTER
CLK AD1861 RIGHT
OUTPUT

Figure 10. AD1861 with Yamaha YM3434 Digital Filter

–8– REV. A
 AD1851/AD1861
+5V LEFT
CLK CLK
OUTPUT
LOW
LATCH OUT PASS
FILTER
X1 COB OW20
DOL DATA AD1851

BCKO
SM5813AP/APT
WCKO

DOR DATA
OW18
LOW
LATCH OUT PASS
FILTER
CLK
AD1851 RIGHT
+5V OUTPUT

Figure 11. AD1851 with NPC SM5813AP/APT Digital Filter

+5V
LEFT
CLK CLK
OUTPUT
LOW
LATCH OUT PASS
FILTER
X1 COB OW20
DOL DATA
AD1861

BCKO
SM5813AP/APT
WCKO

DOR DATA
OW18
LOW
LATCH OUT PASS
FILTER
AD1861 RIGHT
CLK OUTPUT

Figure 12. AD1861 with NPC SM5813AP/APT Digital Filter

REV. A –9–
AD1851/AD1861
OTHER DIGITAL AUDIO COMPONENTS AVAILABLE
FROM ANALOG DEVICES

–VS 1 16-BIT 16-BIT 16 +VS –VS 1 18-BIT 18-BIT 16 +VS

LATCH DAC LATCH DAC
DGND 2 15 TRIM DGND 2 15 TRIM

+VL SERIAL +VL SERIAL

3 14 MSB ADJ 3 14 MSB ADJ
INPUT INPUT
REGISTER REGISTER
NC 4 IOUT 13 IOUT NC 4 IOUT 13 IOUT

CLK 5 12 AGND CLK 5 12 AGND

CONTROL CONTROL
LOGIC LOGIC
LE 6 11 SJ LE 6 11 SJ

DATA 7 10 RF DATA 7 10 RF

–VL 8 AD1856 9 VOUT –VL 8 AD1860 9 VOUT

NC = NO CONNECT NC = NO CONNECT

AD1856 16-BIT AUDIO DAC AD1860 18-BIT AUDIO DAC

Complete, No External Components Required Complete, No External Components Required
0.0025% THD 0.0025% THD+N
Low Cost 108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package 16-Pin DIP or SOIC Package
Standard Pinout Standard Pinout

–VS 1 AD1864 24 +VS

–VS 1 16 +VS
TRIM 2 23 TRIM
VOLTAGE REFERENCE REFERENCE
–VS 2 15 NR2
REFERENCE MSB 3 22 MSB

14 IOUT
TRIM 3 ADJ 4 21 IOUT

AGND 5 20 AGND
+VL 4 13 NR1
SJ 6 19 SJ

CLK 5 12 AGND
RF 7 18 RF
INPUT
AND 20-BIT – –
LE 6 11 IOUT VOUT 8
+
17 VOUT
DIGITAL DAC +
OFFSET +VL 9 16 –VL
DATA 7 10 RF
DR 10 18-BIT 18-BIT 15 DL
18-BIT 18-BIT
D/A D/A
–VL 8 AD1862 9 DGND LR 11
LATCH LATCH
14 LL

CK 12 13 DGND
NC = NO CONNECT

AD1862 20-BIT AUDIO DAC AD1864 DUAL 18-BIT AUDIO DAC

119 dB Signal-to-Noise Ratio Complete, No External Components
0.0016% THD+N 0.0025% THD+N
102 dB D-Range Performance 108 dB Signal-to-Noise Ratio
± 1 dB Gain Linearity Cophased Outputs
16-Pin DIP 24-Pin Package

–10– REV. A
 AD1851/AD1861
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

N (Plastic DIP) Package

R (SOIC Surface Mount) Package

16 9

0.299
(7.60) 0.419
(10.65)

1 8

PIN
1 0.030
0.050 (1.27)
(0.75)
0.413 (10.50)

0.104
(2.650)

0.019
(0.49) 0.012 0.013 0.042
(0.30) (0.32) (1.07)

REV. A –11–
–12–
PRINTED IN U.S.A. C1458–7–10/90