1 nV/√Hz Low Noise

Instrumentation Amplifier
Data Sheet AD8429
FEATURES PIN CONNECTION DIAGRAM
Low noise AD8429
–IN 1 8 +VS
1 nV/√Hz input noise
RG 2 7 VOUT
45 nV/√Hz output noise
RG 3 6 REF
High accuracy dc performance (AD8429BRZ)
90 dB CMRR minimum (G = 1) +IN 4 5 –VS

09730-001
50 μV maximum input offset voltage TOP VIEW
(Not to Scale)
0.02% maximum gain accuracy (G = 1)
Figure 1.
Excellent ac specifications
80 dB CMRR to 5 kHz (G = 1)
15 MHz bandwidth (G = 1)
1.2 MHz bandwidth (G = 100)
22 V/μs slew rate
THD: −130 dBc (1 kHz, G = 1)
Versatile
±4 V to ±18 V dual supply
Gain set with a single resistor (G = 1 to 10,000)
Temperature range for specified performance
−40°C to +125°C

APPLICATIONS
Medical instrumentation
Precision data acquisition
Microphone preamplification
Vibration analysis

GENERAL DESCRIPTION
The AD8429 is an ultralow noise, instrumentation amplifier be useful to shift the output level when interfacing to a single
designed for measuring extremely small signals over a wide supply signal chain.
temperature range (−40°C to +125°C). The AD8429 performance is specified over the extended industrial
The AD8429 excels at measuring tiny signals. It delivers ultralow temperature range of −40°C to +125°C. It is available in an 8-lead
input noise performance of 1 nV/√Hz. The high CMRR of the plastic SOIC package.
AD8429 prevents unwanted signals from corrupting the acqui- 1000

sition. The CMRR increases as the gain increases, offering high

rejection when it is most needed. The high performance pin
configuration of the AD8429 allows it to reliably maintain high 100
G=1
CMRR at frequencies well beyond those of typical instrumentation
NOISE (nV/√Hz)

amplifiers.
10
The AD8429 reliably amplifies fast changing signals. Its current G = 10
feedback architecture provides high bandwidth at high gain, for
G = 100
example, 1.2 MHz at G = 100. The design includes circuitry to im-
1
prove settling time after large input voltage transients. The AD8429 G = 1k

was designed for excellent distortion performance, allowing use in

demanding applications such as vibration analysis.
0.1
09730-002

1 10 100 1k 10k 100k

Gain is set from 1 to 10,000 with a single resistor. A reference
FREQUENCY (Hz)
pin allows the user to offset the output voltage. This feature can Figure 2. RTI Voltage Noise Spectral Density vs. Frequency

Rev. A Document Feedback

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AD8429 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Architecture ................................................................................ 15
Applications ....................................................................................... 1 Gain Selection ............................................................................. 15
Pin Connection Diagram ................................................................ 1 Reference Terminal .................................................................... 15
General Description ......................................................................... 1 Input Voltage Range ................................................................... 16
Revision History ............................................................................... 2 Layout .......................................................................................... 16
Specifications..................................................................................... 3 Input Bias Current Return Path ............................................... 17
Absolute Maximum Ratings ............................................................ 6 Input Protection ......................................................................... 17
Thermal Resistance ...................................................................... 6 Radio Frequency Interference (RFI) ........................................ 17
ESD Caution .................................................................................. 6 Calculating the Noise of the Input Stage ................................. 18
Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19
Theory of Operation ...................................................................... 15

REVISION HISTORY
2/2017—Rev, 0 to Rev. A
Changes to Figure 2 .......................................................................... 1
Change to Input Current Parameter, Table 1 ................................ 3
Changes to Figure 20 and Figure 21............................................. 10
Changes to Figure 24 through Figure 27 ..................................... 11
Changes to Figure 28 and Figure 30............................................. 12
Change to Large Differential Input Voltage at High Gain
Section .............................................................................................. 17
Changes to Figure 53 ...................................................................... 18

4/2011—Revision 0: Initial Version

Rev. A | Page 2 of 20
Data Sheet AD8429

SPECIFICATIONS
VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.

Table 1.
A Grade B Grade
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
COMMON-MODE REJECTION
RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ VCM = ±10 V
Source Imbalance
G=1 80 90 dB
G = 10 100 110 dB
G = 100 120 130 dB
G = 1000 134 140 dB
CMRR at 5 kHz VCM = ±10 V
G=1 76 80 dB
G = 10 90 90 dB
G = 100 90 90 dB
G = 1000 90 90 dB
VOLTAGE NOISE, RTI VIN+, VIN− = 0 V
Spectral Density 1: 1 kHz
Input Voltage Noise, eni 1.0 1.0 nV/√Hz
Output Voltage Noise, eno 45 45 nV/√Hz
Peak to Peak: 0.1 Hz to 10 Hz
G=1 2 2 µV p-p
G = 1000 100 100 nV p-p
CURRENT NOISE
Spectral Density: 1 kHz 1.5 1.5 pA/√Hz
Peak to Peak: 0.1 Hz to 10 Hz 100 100 pA p-p
VOLTAGE OFFSET 2
Input Offset, VOSI 150 50 µV
Average TC 0.1 1 0.1 0.3 µV/°C
Output Offset, VOSO 1000 500 µV
Average TC 3 10 3 10 µV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G=1 90 100 dB
G = 10 110 120 dB
G = 100 130 130 dB
G = 1000 130 130 dB
INPUT CURRENT VIN+, VIN− = 0 V
Input Bias Current 300 150 nA
Average TC 250 250 pA/°C
Input Offset Current 100 30 nA
Average TC 15 15 pA/°C
DYNAMIC RESPONSE
Small Signal Bandwidth: –3 dB
G=1 15 15 MHz
G = 10 4 4 MHz
G = 100 1.2 1.2 MHz
G = 1000 0.15 0.15 MHz

Rev. A | Page 3 of 20
AD8429 Data Sheet
A Grade B Grade
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
Settling Time 0.01% 10 V step
G=1 0.75 0.75 µs
G = 10 0.65 0.65 µs
G = 100 0.85 0.85 µs
G = 1000 5 5 µs
Settling Time 0.001% 10 V step
G=1 0.9 0.9 µs
G = 10 0.9 0.9 µs
G = 100 1.2 1.2 µs
G = 1000 7 7 µs
Slew Rate
G = 1 to 100 22 22 V/µs
THD First five harmonics, f = 1 kHz,
RL = 2 kΩ, VOUT = 10 V p-p
G=1 −130 −130 dBc
G = 10 −116 −116 dBc
G = 100 −113 −113 dBc
G = 1000 −111 −111 dBc
THD + N f = 1 kHz, RL = 2 kΩ, VOUT =
10 V p-p
G = 100 0.0005 0.0005 %
GAIN 3 G = 1 + (6 kΩ/RG)
Gain Range 1 10000 1 10000 V/V
Gain Error VOUT = ±10 V
G=1 0.05 0.02 %
G>1 0.3 0.15 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 1000 RL = 10 kΩ 2 2 ppm
Gain vs. Temperature
G=1 2 5 2 5 ppm/°C
G>1 −100 −100 ppm/°C
INPUT
Impedance (Pin to Ground) 4 1.5||3 1.5||3 GΩ||pF
Input Operating Voltage VS = ±4 V to ±18 V −VS + 2.8 +VS − 2.5 −VS + 2.8 +VS − 2.5 V
Range 5
OUTPUT
Output Swing RL = 2 kΩ −VS + 1.8 +Vs − 1.2 −VS + 1.8 +Vs − 1.2 V
Over Temperature −VS + 1.9 +Vs − 1.3 −VS + 1.9 +Vs − 1.3 V
Output Swing RL = 10 kΩ −VS + 1.7 +Vs − 1.1 −VS + 1.7 +Vs − 1.1 V
Over Temperature −VS + 1.8 +Vs − 1.2 −VS + 1.8 +Vs − 1.2 V
Short-Circuit Current 35 35 mA
REFERENCE INPUT
RIN 10 10 kΩ
IIN VIN+, VIN− = 0 V 70 70 µA
Voltage Range −VS +VS V
Reference Gain to Output 1 1 V/V
Reference Gain Error 0.01 0.05 0.01 0.05 %

Rev. A | Page 4 of 20
Data Sheet AD8429
A Grade B Grade
Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
POWER SUPPLY
Operating Range ±4 ±18 ±4 ±18 V
Quiescent Current 6.7 7 6.7 7 mA
T = 125°C 9 9 mA
TEMPERATURE RANGE
For Specified Performance −40 +125 −40 +125 °C

1
Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information.
2
Total RTI VOS = (VOSI) + (VOSO/G).
3
These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table.
4
Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
5
Input voltage range of the AD8429 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage.
See the Input Voltage Range section for more details.

Rev. A | Page 5 of 20
AD8429 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. THERMAL RESISTANCE
Parameter Rating θJA is specified for a device in free air using a 4-layer JEDEC
Supply Voltage ±18 V printed circuit board (PCB).
Output Short-Circuit Current Duration Indefinite
Maximum Voltage at –IN, +IN1 ±VS Table 3.
Differential Input Voltage1 Package θJA Unit
Gain ≤ 4 ±VS 8-Lead SOIC 121 °C/W
4 > Gain > 50 ±50 V/gain
Gain ≥ 50 ±1 V
Maximum Voltage at REF ±VS ESD CAUTION
Storage Temperature Range −65°C to +150°C
Specified Temperature Range −40°C to +125°C
Maximum Junction Temperature 140°C
ESD
Human Body Model 3.0 kV
Charge Device Model 1.5 kV
Machine Model 0.2 kV
1
For voltages beyond these limits, use input protection resistors. See the
Theory of Operation section for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 6 of 20
Data Sheet AD8429

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8429
–IN 1 8 +VS

RG 2 7 VOUT

RG 3 6 REF

+IN 4 5 –VS

09730-003
TOP VIEW
(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 −IN Negative Input Terminal.
2, 3 RG Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG).
4 +IN Positive Input Terminal.
5 −VS Negative Power Supply Terminal.
6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output.
7 VOUT Output Terminal.
8 +VS Positive Power Supply Terminal.

Rev. A | Page 7 of 20
AD8429 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = ±15, VREF = 0, RL = 10 kΩ, unless otherwise noted.
15 160
G=1 VS = ±15V GAIN = 1000
GAIN = 100
140 GAIN = 10
10 GAIN = 1
COMMON-MODE VOLTAGE (V)

VS = ±12V 120

POSITIVE PSRR (dB)

5
100

0 VS = ±5V 80

60
–5

40
–10
20

–15 0
09730-010

09730-069
–15 –10 –5 0 5 10 15 1 10 100 1k 10k 100k 1M
OUTPUT VOLTAGE (V) FREQUENCY (Hz)

Figure 4. Input Common-Mode Voltage vs. Output Voltage, Figure 7. Positive PSRR vs. Frequency
Dual Supply, VS = ±5 V, ±12 V, ±15 V (G = 1)
15 160
VS = ±15V GAIN = 1000
G = 100 GAIN = 100
140 GAIN = 10
10 GAIN = 1
COMMON-MODE VOLTAGE (V)

VS = ±12V 120
NEGATIVE PSRR (dB)

5
100

0 VS = ±5V 80

60
–5
40
–10
20

–15 0
09730-011

09730-070
–15 –10 –5 0 5 10 15 1 10 100 1k 10k 100k 1M
OUTPUT VOLTAGE (V) FREQUENCY (Hz)

Figure 5. Input Common-Mode Voltage vs. Output Voltage, Figure 8. Negative PSRR vs. Frequency
Dual Supply, VS = ±5 V, ±12 V, ±15 V (G = 100)
0 70
GAIN = 1000 VS = ±15V
–5 60

–10 50
INPUT BIAS CURRENT (nA)

GAIN = 100
–15 40
–12.28V
–20 30
GAIN (dB)

GAIN = 10
–25 20

–30 +12.60V 10
GAIN = 1
–35 0

–40 –10

–45 –20

–50 –30
09730-068

09730-017

–14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 100 1k 10k 100k 1M 10M 100M

COMMON-MODE VOLTAGE (V) FREQUENCY (Hz)

Figure 6. Input Bias Current vs. Common-Mode Voltage Figure 9. Gain vs. Frequency

Rev. A | Page 8 of 20
Data Sheet AD8429
160 40 3.0
IB+
G = 1k
IB–
140
G = 100 30 IOS 2.5

INPUT OFFSET CURRENT (nA)

G = 10

INPUT BIAS CURRENT (nA)

120

G=1 20 2.0
100
BANDWIDTH
CMRR (dB)

LIMITED
80 10 1.5

60
0 1.0

40
–10 0.5
20

0 –20 0

09730-019
09730-110
1 10 100 1k 10k 100k 1M –45 –30 –15 0 15 30 45 60 75 90 105 120 135
FREQUENCY (Hz) TEMPERATURE (°C)

Figure 10. CMRR vs. Frequency Figure 13. Input Bias Current and Input Offset Current vs. Temperature

140 40
G = 100 GAIN = 1
G = 1k 30
120
G = 10 20

100 10
G=1

CMRR (µV/V)
0
CMRR (dB)

80
BANDWIDTH
LIMITED –10
60 –20

–30
40
–40
20
–50
NORMALIZED AT 25°C
0 –60

09730-114
–40 –25 –10 5 20 35 50 65 80 95 110 125
09730-111

1 10 100 1k 10k 100k 1M

FREQUENCY (Hz) TEMPERATURE (°C)

Figure 11. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 14. CMRR vs. Temperature (G = 1), Normalized at 25°C

12 10.0
CHANGE IN INPUT OFFSET VOLTAGE (µV)

9.5
10
9.0
SUPPLY CURRENT (mA)

8.5
8
8.0

6 7.5

7.0
4
6.5

6.0
2
5.5

0 5.0
09730-022
09730-112

0 100 200 300 400 500 600 700 –50 –30 –10 10 30 50 70 90 110 130
WARM-UP TIME (s) TEMPERATURE (°C)

Figure 12. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time Figure 15. Supply Current vs. Temperature (G = 1)

Rev. A | Page 9 of 20
AD8429 Data Sheet
50 +VS
+125°C
40 ISHORT+ –0.5 +85°C
+25°C

REFERRED TO SUPPLY VOLTAGES

–1.0
–40°C
SHORT-CIRCUIT CURRENT (mA)

30
–1.5
20

INPUT VOLTAGE (V)

–2.0
10 –2.5

0
+2.5
–10
+2.0
–20
ISHORT– +1.5
–30
+1.0
–40 +0.5

–50 –VS

09730-023

09730-026
–40 –25 –10 5 20 35 50 65 80 95 110 125 4 6 8 10 12 14 16 18
TEMPERATURE (°C) SUPPLY VOLTAGE (±VS)

Figure 16. Short-Circuit Current vs. Temperature (G = 1) Figure 19. Input Voltage Limit vs. Supply Voltage

30 +VS

–0.4

REFERRED TO SUPPLY VOLTAGES

25
–0.8
–SR
OUTPUT VOLTAGE (V) –1.2
SLEW RATE (V/µs)

20

+SR
15 +2.0

+1.6
10
+1.2

+0.8 +125°C
5
+85°C
+0.4 +25°C
–40°C
0 –VS
09730-024

09730-027
–40 –25 –10 5 20 35 50 65 80 95 110 125 4 6 8 10 12 14 16 18
TEMPERATURE (°C) SUPPLY VOLTAGE (±VS)

Figure 17. Slew Rate vs. Temperature, VS = ±15 V (G = 1) Figure 20. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ

25 +VS

–0.4
REFERRED TO SUPPLY VOLTAGES

20 –SR
–0.8
OUTPUT VOLTAGE (V)

+SR –1.2
SLEW RATE (V/µs)

15

+2.0

10 +1.6

+1.2

5 +0.8 +125°C
+85°C
+0.4 +25°C
–40°C
0 –VS
09730-025

09730-028

–40 –25 –10 5 20 35 50 65 80 95 110 125 4 6 8 10 12 14 16 18

TEMPERATURE (°C) SUPPLY VOLTAGE (±VS)

Figure 18. Slew Rate vs. Temperature, VS = ±5 V (G = 1) Figure 21. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

Rev. A | Page 10 of 20
Data Sheet AD8429
15 10
VS = ±15V GAIN = 1000
8
10
6
OUTPUT VOLTAGE SWING (V)

NONLINEARITY (ppm)
4
5

+125°C 2
+85°C
0 0
+25°C
–40°C
–2
–5
–4

–6
–10
–8

–15 –10

09730-029

09730-084
100 1k 10k 100k –10 –8 –6 –4 –2 0 2 4 6 8 10
LOAD (Ω) OUTPUT VOLTAGE (V)

Figure 22. Output Voltage Swing vs. Load Resistance Figure 25. Gain Nonlinearity (G = 1000), RL = 10 kΩ

+VS 1000
VS = ±15V
–0.4
REFERRED TO SUPPLY VOLTAGES

–0.8
OUTPUT VOLTAGE SWING (V)

–1.2 100
G=1
–1.6
NOISE (nV/√Hz)
10
+2.0 G = 10

+1.6
G = 100
+1.2
1
+125°C G = 1k
+0.8
+85°C
+0.4 +25°C
–40°C
–VS 0.1
09730-030

09730-126
10µ 100µ 1m 10m 1 10 100 1k 10k 100k
OUTPUT CURRENT (A) FREQUENCY (Hz)

Figure 23. Output Voltage Swing vs. Output Current Figure 26. RTI Voltage Noise Spectral Density vs. Frequency

10
GAIN = 1
8
GAIN = 1000, 100nV/DIV
6
NONLINEARITY (ppm)

2
GAIN = 1, 1μV/DIV
0

–2

–4

–6
09730-086

–8
1s/DIV
–10
09730-083

–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)

Figure 24. Gain Nonlinearity (G = 1), RL = 10 kΩ Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000)

Rev. A | Page 11 of 20
AD8429 Data Sheet
100

5V/DIV
NOISE (pA/√Hz)

750ns TO 0.01%
10 872ns TO 0.001%

0.002%/DIV

2µs/DIV

09730-090
1
TIME (µs)

09730-087
1 10 100 1k 10k 100k
FREQUENCY (Hz)

Figure 28. Current Noise Spectral Density vs. Frequency Figure 31. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step,
VS = ±15 V

5V/DIV

640ns TO 0.01%
896ns TO 0.001%

0.002%/DIV
09730-088

50pA/DIV 1s/DIV 2µs/DIV

09730-091
TIME (µs)

Figure 29. 0.1 Hz to 10 Hz Current Noise Figure 32. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step,
VS = ±15 V
30
G=1

VS = ±15V
25
OUTPUT VOLTAGE (V p-p)

20 5V/DIV

840ns TO 0.01%
15 1152ns TO 0.001%

10
0.002%/DIV

VS = ±5V
5

2µs/DIV
09730-040

0
TIME (µs)
09730-089

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 30. Large Signal Frequency Response Figure 33. Large Signal Pulse Response and Settling Time (G = 100),
10 V Step, VS = ±15 V

Rev. A | Page 12 of 20
Data Sheet AD8429
G = 100

5V/DIV

5.04µs TO 0.01%
6.96µs TO 0.001%

0.002%/DIV

09730-044
10µs/DIV 20mV/DIV 1µs/DIV

09730-041
TIME (µs)

Figure 34. Large Signal Pulse Response and Settling Time (G = 1000), Figure 37. Small Signal Response (G = 100), RL = 10 kΩ, CL = 100 pF
10 V Step, VS = ±15 V

G = 1000
G=1

09730-045
09730-042

50mV/DIV 1µs/DIV 20mV/DIV 10µs/DIV

Figure 35. Small Signal Response (G = 1), RL = 10 kΩ, CL = 100 pF Figure 38. Small Signal Response (G = 1000), RL = 10 kΩ, CL = 100 pF

G = 10 G=1

NO LOAD
09730-043

09730-093

CL = 100pF
20mV/DIV 1µs/DIV 50mV/DIV CL = 147pF 1µs/DIV

Figure 36. Small Signal Response (G = 10), RL = 10 kΩ, CL = 100 pF Figure 39. Small Signal Response with Various Capacitive Loads (G = 1),
RL = Infinity

Rev. A | Page 13 of 20
AD8429 Data Sheet
1400 1
NO LOAD G = 1000, SECOND HARMONIC
2kΩ LOAD VOUT = 10V p-p

AMPLITUDE (Percentage of Fundamental)

600Ω LOAD
1200

0.1
1000
SETTLING TIME (ns)

SETTLED TO 0.001%
800
0.01
SETTLED TO 0.01%
600

400
0.001

200

0 0.0001

09730-092

09730-098
2 4 6 8 10 12 14 16 18 20 10 100 1k 10k 100k
STEP SIZE (V) FREQUENCY (Hz)

Figure 40. Settling Time vs. Step Size (G = 1) Figure 43. Second Harmonic Distortion vs. Frequency (G = 1000)

1 1
NO LOAD G = 1, SECOND HARMONIC NO LOAD G = 1000, THIRD HARMONIC
2kΩ LOAD VOUT = 10V p-p 2kΩ LOAD VOUT = 10V p-p

AMPLITUDE (Percentage of Fundamental)

AMPLITUDE (Percentage of Fundamental)

600Ω LOAD 600Ω LOAD

0.1
0.1

0.01

0.01

0.001

0.001
0.0001

0.00001 0.0001

09730-099
09730-096

10 100 1k 10k 100k 10 100 1k 10k 100k

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 41. Second Harmonic Distortion vs. Frequency (G = 1) Figure 44. Third Harmonic Distortion vs. Frequency (G = 1000)

1 1
NO LOAD G = 1, THIRD HARMONIC VOUT = 10V p-p
2kΩ LOAD VOUT = 10V p-p RL ≥ 2kΩ
AMPLITUDE (Percentage of Fundamental)

600Ω LOAD

0.1 0.1

0.01 0.01
THD (%)

GAIN = 100
0.001 0.001

GAIN = 1000

0.0001 0.0001 GAIN = 10

GAIN = 1

0.00001 0.00001
09730-097

09730-100

10 100 1k 10k 100k 10 100 1k 10k 100k

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 42. Third Harmonic Distortion vs. Frequency (G = 1) Figure 45. THD vs. Frequency

Rev. A | Page 14 of 20
Data Sheet AD8429

THEORY OF OPERATION
I VB I

IB IB
COMPENSATION COMPENSATION
A1 A2 R3
5kΩ
C1 C2 R4 +VS
NODE 1 5kΩ

NODE 2 A3 VOUT

+VS +VS R5 +VS

R1 R2 5kΩ R6 –VS
3kΩ 3kΩ
5kΩ
+VS +VS REF
–IN Q1 Q2 +IN
RG
–VS –VS –VS
RG– RG+

09730-058
–VS –VS

Figure 46. Simplified Schematic

ARCHITECTURE Table 5. Gains Achieved Using 1% Resistors

The AD8429 is based on the classic 3-op-amp topology. This 1% Standard Table Value of RG Calculated Gain
topology has two stages: a preamplifier to provide differential 6.04 kΩ 1.993
amplification followed by a difference amplifier that removes 1.5 kΩ 5.000
the common-mode voltage and provides additional amplifica- 665 Ω 10.02
tion. Figure 46 shows a simplified schematic of the AD8429. 316 Ω 19.99
The first stage works as follows. To keep its two inputs matched, 121 Ω 50.59
Amplifier A1 must keep the collector of Q1 at a constant voltage. 60.4 Ω 100.3
It does this by forcing RG− to be a precise diode drop from –IN. 30.1 Ω 200.3
Similarly, A2 forces RG+ to be a constant diode drop from +IN. 12.1 Ω 496.9
Therefore, a replica of the differential input voltage is placed 6.04 Ω 994.4
across the gain setting resistor, RG. The current that flows through 3.01 Ω 1994
this resistance must also flow through the R1 and R2 resistors,
creating a gained differential signal between the A2 and A1 The AD8429 defaults to G = 1 when no gain resistor is used.
outputs. Add the tolerance and gain drift of the RG resistor to the
specifications of the AD8429 to determine the total gain accu-
The second stage is a G = 1 difference amplifier, composed of
racy of the system. When the gain resistor is not used, gain
Amplifier A3 and the R3 through R6 resistors. This stage removes
error and gain drift are minimal.
the common-mode signal from the amplified differential signal.
RG Power Dissipation
The transfer function of the AD8429 is
The AD8429 duplicates the differential voltage across its inputs
VOUT = G × (VIN+ − VIN−) + VREF
onto the RG resistor. Choose an RG resistor size sufficient to
where: handle the expected power dissipation.
6 kΩ REFERENCE TERMINAL
G = 1+
RG The output voltage of the AD8429 is developed with respect to
the potential on the reference terminal. This is useful when the
GAIN SELECTION
output signal must be offset to a precise midsupply level. For
Placing a resistor across the RG terminals sets the gain of the example, a voltage source can be tied to the REF pin to level
AD8429, which can be calculated by referring to Table 5 or by shift the output, allowing the AD8429 to drive a single-supply
using the following gain equation: ADC. The REF pin is protected with ESD diodes and should
6 kΩ not exceed either +VS or −VS by more than 0.3 V.
RG =
G −1

Rev. A | Page 15 of 20
AD8429 Data Sheet
For best performance, maintain a source impedance to the REF source resistance in the input path (for example, for input
terminal that is well below 1 Ω. As shown in Figure 46, the protection) close to the in-amp inputs, which minimizes their
reference terminal, REF, is at one end of a 5 kΩ resistor. interaction with parasitic capacitance from the PCB traces.
Additional impedance at the REF terminal adds to this 5 kΩ Parasitic capacitance at the gain setting pins can also affect CMRR
resistor and results in amplification of the signal connected to over frequency. If the board design has a component at the gain
the positive input. The amplification from the additional RREF setting pins (for example, a switch or jumper), choose a component
can be calculated as follows: such that the parasitic capacitance is as small as possible.
2(5 kΩ + RREF)/(10 kΩ + RREF) Power Supplies and Grounding
Only the positive signal path is amplified; the negative path Use a stable dc voltage to power the instrumentation amplifier.
is unaffected. This uneven amplification degrades CMRR. Noise on the supply pins can adversely affect performance. See
INCORRECT CORRECT the PSRR performance curves in Figure 9 and Figure 10 for more
information.
Place a 0.1 μF capacitor as close as possible to each supply pin.
AD8429 AD8429
Because the length of the bypass capacitor leads is critical at
REF REF
V
high frequency, surface-mount capacitors are recommended. A
V
parasitic inductance in the bypass ground trace works against
+
the low impedance created by the bypass capacitor. As shown in
OP1177
Figure 49, a 10 μF capacitor can be used farther away from the
09730-059

–
device. For larger value capacitors, intended to be effective at
lower frequencies, the current return path distance is less critical.
Figure 47. Driving the Reference Pin
In most cases, this capacitor can be shared by other precision
INPUT VOLTAGE RANGE integrated circuits.
+VS
Figure 4 and Figure 5 show the allowable common-mode input
voltage ranges for various output voltages and supply voltages.
The 3-op-amp architecture of the AD8429 applies gain in the 0.1µF 10µF

first stage before removing common-mode voltage with the

+IN
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 46) experience a VOUT
RG AD8429
combination of a gained signal, a common-mode signal, and a LOAD
diode drop. This combined signal can be limited by the voltage –IN REF

supplies even when the individual input and output signals are
not limited.
0.1µF 10µF

09730-061
LAYOUT
–VS
To ensure optimum performance of the AD8429 at the PCB
Figure 49. Supply Decoupling, REF, and Output Referred to Local Ground
level, care must be taken in the design of the board layout. The
pins of the AD8429 are arranged in a logical manner to aid in A ground plane layer is helpful to reduce parasitic inductances.
this task. This minimizes voltage drops with changes in current. The area
of the current path is directly proportional to the magnitude of
–IN 1 8 +VS parasitic inductances and, therefore, the impedance of the path
RG 2 7 VOUT at high frequency. Large changes in currents in an inductive
RG 3 6 REF decoupling path or ground return create unwanted effects, due
+IN 4 5 –VS to the coupling of such changes into the amplifier inputs.
AD8429
09730-060

TOP VIEW Because load currents flow from the supplies, the load should
(Not to Scale)
be connected at the same physical location as the bypass capa-
Figure 48. Pinout Diagram
citor grounds.
Common-Mode Rejection Ratio over Frequency
Reference Pin
Poor layout can cause some of the common-mode signals to be
The output voltage of the AD8429 is developed with respect to
converted to differential signals before reaching the in-amp.
the potential on the reference terminal. Ensure that REF is tied
Such conversions occur when one input path has a frequency
to the appropriate local ground.
response that is different from the other. To maintain high
CMRR over frequency, closely match the input source
impedance and capacitance of each path. Place additional
Rev. A | Page 16 of 20
Data Sheet AD8429
INPUT BIAS CURRENT RETURN PATH Noise sensitive applications may require a lower protection resis-
The input bias current of the AD8429 must have a return path to tance. Low leakage diode clamps, such as the BAV199, can be used
ground. When using a floating source without a current return at the inputs to shunt current away from the AD8429 inputs,
path, such as a thermocouple, create a current return path, as thereby allowing smaller protection resistor values. To ensure
shown in Figure 50. current flows primarily through the external protection diodes,
place a small value resistor, such as a 33 Ω, between the diodes and
INCORRECT CORRECT
the AD8429.
+VS +VS
+VS
+VS +VS
RPROTECT RPROTECT 33Ω
+ + I
VIN+ I VIN+
– – –VS
AD8429 AD8429 AD8429 AD8429
+VS
REF REF RPROTECT RPROTECT 33Ω
+ +
VIN– –VS VIN– –VS
– – –VS

09730-066
–VS –VS
SIMPLE METHOD LOW NOISE METHOD
TRANSFORMER TRANSFORMER
Figure 51. Protection for Voltages Beyond the Rails
+VS +VS
Large Differential Input Voltage at High Gain
If large differential voltages at high gain are expected, use an
external resistor in series with each input to limit current during
AD8429 AD8429 overload conditions. The limiting resistor at each input can be
REF REF computed by using the following equation:
10MΩ
1  V DIFF − 1V 
R PROTECT ≥  − RG 
–VS –VS 
2  I MAX 
THERMOCOUPLE THERMOCOUPLE

Noise sensitive applications may require a lower protection resis-
+VS +VS
tance. Low leakage diode clamps, such as the BAV199, can be used
C C across the inputs to shunt current away from the AD8429 inputs
and, therefore, allow smaller protection resistor values.
1 R
AD8429 fHIGH-PASS = 2πRC AD8429 RPROTECT RPROTECT
C C I + I
REF REF +
VDIFF VDIFF
AD8429 AD8429
R – –

RPROTECT RPROTECT
09730-062

–VS –VS

09730-067
CAPACITIVELY COUPLED CAPACITIVELY COUPLED SIMPLE METHOD LOW NOISE METHOD
Figure 50. Creating an Input Bias Current Return Path Figure 52. Protection for Large Differential Voltages
INPUT PROTECTION IMAX
Do not allow the inputs of the AD8429 to exceed the ratings The maximum current into the AD8429 inputs, IMAX, depends
stated in the Absolute Maximum Ratings section of this data on time and temperature. At room temperature, the device can
sheet. If this cannot be done, protection circuitry can be added withstand a current of 10 mA for at least one day. This time is
in front of the AD8429 to limit the current into the inputs to a cumulative over the life of the device.
maximum current, IMAX.
RADIO FREQUENCY INTERFERENCE (RFI)
Input Voltages Beyond the Rails
RF rectification is often a problem when amplifiers are used in
If voltages beyond the rails are expected, use an external resistor applications that have strong RF signals. The disturbance can
in series with each input to limit current during overload condi- appear as a small dc offset voltage. High frequency signals can
tions. The limiting resistor at the input can be computed from be filtered with a low-pass RC network placed at the input of
| VIN − VSUPPLY | the instrumentation amplifier, as shown in Figure 53.
R PROTECT ≥
I MAX

Rev. A | Page 17 of 20
AD8429 Data Sheet
+VS
at the amplifier input. To calculate the noise referred to the
amplifier output (RTO), simply multiply the RTI noise by the
0.1µF 10µF
gain of the instrumentation amplifier.
CC
1nF Source Resistance Noise
L* R +IN
33Ω Any sensor connected to the AD8429 has some output resistance.
CD OUT There may also be resistance placed in series with inputs for pro-
10nF AD8429
L* R REF
tection from either overvoltage or radio frequency interference.
33Ω –IN This combined resistance is labeled R1 and R2 in Figure 54. Any
CC
1nF
resistor, no matter how well made, has an intrinsic level of noise.
This noise is proportional to the square root of the resistor value.
0.1µF 10µF
At room temperature, the value is approximately equal to
4 nV/√Hz × √(resistor value in kΩ).

09730-049
–VS

*CHIP FERRITE BEAD. For example, assuming that the combined sensor and protec-
Figure 53. RFI Suppression tion resistance on the positive input is 4 kΩ, and on the negative
The filter limits the input signal bandwidth, according to the input is 1 kΩ, the total noise from the input resistance is
following relationship:
4  4   4  1 
2 2
 64  16  8.9 nV/√Hz
1
FilterFrequency DIFF 
2πR(2C D  CC ) Voltage Noise of the Instrumentation Amplifier
1 The voltage noise of the instrumentation amplifier is calculated
FilterFrequency CM 
2πRC C using three parameters: the device input noise, output noise,
and the RG resistor noise. It is calculated as follows:
where CD  10 CC.
Total Voltage Noise =
CD affects the difference signal, and CC affects the common-mode
signal. Choose values of R and CC that minimize RFI. A mismatch Output Noise / G 2  Input Noise 2  Noise of RG Resistor 2
between R × CC at the positive input and R × CC at the negative
input degrades the CMRR of the AD8429. By using a value of For example, for a gain of 100, the gain resistor is 60.4 Ω. There-
CD that is one magnitude larger than CC, the effect of the fore, the voltage noise of the in-amp is
mismatch is reduced, and performance is improved.
45 / 100 2  12  4  0.0604  = 1.5 nV/√Hz
2
Resistors add noise; therefore, the choice of resistor and capacitor
values depends on the desired tradeoff between noise, input
impedance at high frequencies, and RFI immunity. The resistors Current Noise of the Instrumentation Amplifier
used for the RFI filter can be the same as those used for input Current noise is calculated by multiplying the source resistance
protection. by the current noise.
CALCULATING THE NOISE OF THE INPUT STAGE For example, if the R1 source resistance in Figure 54 is 4 kΩ,
SENSOR and the R2 source resistance is 1 kΩ, the total effect from the
current noise is calculated as follows:

4  1.52  1  1.52  = 6.2 nV/√Hz

R1 RG AD8429

Total Noise Density Calculation

09730-064

R2 To determine the total noise of the in-amp, referred to input,

Figure 54. Source Resistance from Sensor and Protection Resistors combine the source resistance noise, voltage noise, and current
noise contribution by the sum of squares method.
The total noise of the amplifier front end depends on much
more than the 1 nV/√Hz specification of this data sheet. There For example, if the R1 source resistance in Figure 54 is 4 kΩ, the
are three main contributors: the source resistance, the voltage R2 source resistance is 1 kΩ, and the gain of the in-amps is 100,
noise of the instrumentation amplifier, and the current noise of the total noise, referred to input, is
the instrumentation amplifier. 8.9 2  1.5 2  6.2 2 = 11.0 nV/√Hz
In the following calculations, noise is referred to the input
(RTI). In other words, everything is calculated as if it appeared

Rev. A | Page 18 of 20
Data Sheet AD8429

OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

012407-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8429ARZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8429ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7” Tape and Reel R-8
AD8429BRZ −40°C to +125°C 8-Lead SOIC_N R-8
AD8429BRZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7” Tape and Reel R-8
1
Z = RoHS Compliant Part.

Rev. A | Page 19 of 20
AD8429 Data Sheet

NOTES

©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09730-0-2/17(A)

Rev. A | Page 20 of 20