CS5509

Single-supply, 16-bit A/D Converter

Features Description
 Delta-sigma A/D Converter The CS5509 is a single-supply, 16-bit, serial-output
CMOS A/D converter. The CS5509 uses charge-bal-
- 16-bit, No Missing Codes anced (delta-sigma) techniques to provide low-cost,
- Linearity Error: ±0.0015%FS high-resolution measurements at output word rates up to
200 samples per second.
 Differential Input The on-chip digital filter offers superior line rejection at
- Pin-selectable Unipolar/Bipolar Ranges 50Hz and 60Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
- Common Mode Rejection
105 dB @ dc The CS5509 has on-chip self-calibration circuitry which
120 dB @ 50, 60 Hz can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.
 Either 5V or 3.3V Digital Interface Low power, high resolution, and small package size
make the CS5509 an ideal solution for loop-powered
 On-chip Self-calibration Circuitry transmitters, panel meters, weigh scales, and battery
powered instruments.
 Output Update Rates up to 200/second ORDERING INFORMATION

 Ultra Low Power: 1.7 mW CS5509-ASZ -40 °C to +85 °C 16-pin SOIC Lead Free
I

VREF+ VREF- VA+ GND VD+

9 10 11 12 13
1 CS
Serial 14 SCLK
7 Interface 15
AIN+ Differential Logic SDATA
4th order Digital 16 DRDY
delta-sigma Filter
8 modulator
AIN-
3
CAL
Calibration µC 6 BP/UP
Calibration
SRAM OSC
2 4 5
CONV XIN XOUT

Copyright  Cirrus Logic, Inc. 2009 SEP ‘09

http://www.cirrus.com (All Rights Reserved)
DS125F3
1
 CS5509

ANALOG CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; VREF+ = 2.5V,
VREF- = 0V; fCLK = 32.768 kHz; Bipolar Mode; Rsource = 40 Ω with a 10 nF to GND at AIN; AIN- = 2.5V; unless oth-
erwise specified.) (Notes 1 and 2)

Parameter* Min Typ Max Unit

Accuracy
Linearity Error fCLK = 32.768 kHz - 0.0015 0.003 ± %FS
fCLK = 165 kHz - 0.0015 0.003 ± %FS
fCLK = 247.5 kHz - 0.0015 0.003 ± %FS
fCLK = 330 kHz - 0.005 0.0125 ± %FS
Differential Nonlinearity - ±0.25 ±0.5 LSB
Full-scale Error (Note 3) - ±0.25 ±2 LSB
Full-scale Drift (Note 4) - ±0.5 - LSB
Unipolar Offset (Note 3) - ±0.5 ±2 LSB
Unipolar Offset Drift (Note 4) - ±0.5 - LSB
Bipolar Offset (Note 3) - ±0.25 ±1 LSB
Bipolar Offset Drift (Note 4) - ±0.25 - LSB
Noise (Referred to Output) - 0.16 - LSBrms
Analog Input
Analog Input Range Unipolar - 0 to +2.5 - V
Bipolar (Notes 5 and 6) - ±2.5 - V
Common Mode Rejection dc - 105 - dB
fCLK = 32.768 kHz 50, 60 Hz (Note 2) 120 - - dB
Input Capacitance - 15 - pF
DC Bias Current (Note 1) - 5 - nA
Power Supplies
DC Power Supply Currents ITotal
- 350 450 µA
IAnalog - 300 - µA
IDigital - 60 - µA
Power Dissipation (Note 7) - 1.7 2.25 mW
Power Supply Rejection - 80 - dB
Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5509's source
impedance requirements. Refer to the text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25 °C.
5. The input is differential. Therefore, GND ≤ Signal + Common Mode Voltage ≤ VA+.
6. The CS5509 can accept input voltages up to the VA+ analog supply. In unipolar mode the CS5509 will
output all 1's if the dc input magnitude ((AIN+) - (AIN-)) exceeds ((VREF+) - (VREF-)) and will output all
0's if the input becomes more negative than 0 Volts. In bipolar mode the CS5509 will output all 1's if the
dc input magnitude ((AIN+) - (AIN-)) exceeds ((VREF+) - (VREF-)) and will output all 0's if the input
becomes more negative in magnitude than -((VREF+) - (VREF-)).
7. All outputs unloaded. All inputs CMOS levels.
* Refer to the Specification Definitions immediately following the Pin Description Section.

2 DS125F3
 CS5509

DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Unit
Modulator Sampling Frequency fs fclk/2 Hz
Output Update Rate (CONV = 1) fout fclk/1622 Hz
Filter Corner Frequency f-3dB fclk/1928 Hz
Settling Time to 1/2 LSB (FS Step) ts 1/fout s

5V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%; GND = 0) (Notes 2 and 8)

Parameter Symbol Min Typ Max Unit

High-level Input Voltage XIN 3.5 - - V
All Pins Except XIN VIH 2.0 - - V
Low-level Input Voltage XIN - - 1.5 V
All Pins Except XIN VIL - - 0.8 V
High-level Output Voltage (Note 9) VOH (VD+) -1.0 - - V
Low-level Output Voiltage Iout = 1.6 mA VOL - - 0.4 V
Input Leakage Current Iin - ±1 ±10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF
Notes: 8. All measurements are performed under static conditions.
9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4 V at Iout = -40 µA).

3.3V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; GND = 0)
(Notes 2 and 8)

Parameter Symbol Min Typ Max Unit

High-level Input Voltage XIN 0.7 VD+ - - V
All Pins Except XIN VIH 0.6 VD+ - - V
Low-level Input Voltage XIN - - 0.3 VD+ V
All Pins Except XIN VIL - - 0.16 VD+ V
High-level Output Voltage (Note 9) VOH (VD+) -0.3 - - V
Low-level Output Voltage Iout = 1.6 mA VOL - - 0.3 V
Input Leakage Current Iin - ±1 ±10 µA
3-state Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF

Specifications are subject to change without notice

DS125F3 3
 CS5509

5V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%;

Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2)

Parameter Symbol Min Typ Max Unit

Master Clock Frequency Internal Oscillator XIN 30.0 32.768 53.0 kHz
External Clock fclk 30 - 330 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times Any Digital Input (Note 10) - - 1.0 µs
Any Digital Output trise - 50 - ns
Fall Time Any Digital Input (Note 10) - - 1.0 µs
Any Digital Output tfall - 20 - ns
Start-Up
Power-On Reset Period (Note 11) tres - 10 - ms
Oscillator Start-up Time XTAL = 32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL = 1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk - s
Conversion
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk - - s
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk - s
Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using
an external clock source.
13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on
reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.

4 DS125F3
 CS5509

3.3V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input
Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2)

Parameter Symbol Min Typ Max Unit

Master Clock Frequency Internal Oscillator XIN 30.0 32.768 53.0 kHz
External Clock fclk 30 - 330 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times Any Digital Input (Note 10) - - 1.0 µs
Any Digital Output trise - 50 - ns
Fall Time Any Digital Input (Note 10) - - 1.0 µs
Any Digital Output tfall - 20 - ns
Start-Up
Power-On Reset Period (Note 11) tres - 10 - ms
Oscillator Start-up Time XTAL = 32.768 kHz (Note 12) tosu - 500 - ms
Wake-up Period (Note 13) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL = 1) (Note 14) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration tcal - 3246/fclk - s
Conversion
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk - - s
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 15) tcon - 1624/fclk - s

DS125F3 5
 CS5509

XIN

XIN/2

CAL
t ccw
CONV
t scl t cal
STATE Standby Calibration Standby

Figure 1. Calibration Timing (Not to Scale)

XIN

XIN/2

CONV
t cpw
DRDY

BP/UP
t bus t buh
t scn t con
STATE Standby Conversion Standby

Figure 2. Conversion Timing (Not to Scale)

6 DS125F3
 CS5509

5V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±5%; Input Levels: Logic 0 =
0V, Logic 1 = VD+; CL = 50 pF) (Note 2)

Parameter Symbol Min Typ Max Unit

Serial Clock fsclk 0 - 2.5 MHz
Serial Clock Pulse Width High tph 200 - - ns
Pulse Width Low tpl 200 - - ns
Access Time CS Low to data valid (Note 16) tcsd - 60 200 ns
Maximum Delay Time (Note 17)
SCLK falling to new SDATA bit tdd - 150 310 ns
Output Float Delay CS High to output Hi-Z (Note 18) tfd1 - 60 150 ns
SCLK falling to Hi-Z tfd2 - 160 300 ns
Notes: 16. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To guarantee
proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than
2 fclk + 200 ns after CS goes low.
17. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial
port shifting mechanism before falling edges can be recognized.
18. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.

3.3V SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.3V ±5%; Input
Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) (Note 2)

Parameter Symbol Min Typ Max Unit

Serial Clock fsclk 0 - 1.25 MHz
Serial Clock Pulse Width High tph 200 - - ns
Pulse Width Low tpl 200 - - ns
Access Time CS Low to data valid (Note 16) tcsd - 100 200 ns
Maximum Delay Time (Note 17)
SCLK falling to new SDATA bit tdd - 400 600 ns
Output Float Delay CS High to output Hi-Z (Note 18) tfd1 - 70 150 ns
SCLK falling to Hi-Z tfd2 - 320 500 ns

DS125F3 7
 CS5509

DRDY

CS
t csd t fd1
SDATA(o) Hi-Z MSB MSB-1 MSB-2
t dd
SCLK(i)

DRDY

CS
t csd
SDATA(o) Hi-Z MSB MSB-1 LSB+2 LSB+1 LSB
t dd t ph tfd2

SCLK(i)
t pl

Figure 3. Timing Relationships (Not to Scale)

8 DS125F3
 CS5509

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19)

Parameter Symbol Min Typ Max Unit

DC Power Supplies Positive Digital VD+ 3.15 5.0 5.5 V
Positive Analog VA+ 4.75 5.0 5.5 V
(VREF+) -
Analog Reference Voltage (Note 20) (VREF-) 1.0 2.5 3.6 V
Analog Input Voltage (Note 6)
Unipolar VAIN 0 - (VREF+) - (VREF-) V
Bipolar VAIN -((VREF+) - (VREF-)) - (VREF+) - (VREF-) V
Notes: 19. All voltages with respect to ground.
20. The CS5509 can be operated with a reference voltage as low as 100 mV; but with a corresponding
reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value
as long as +VREF and -VREF remain inside the supply values of VA+ and GND.

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Unit
DC Power Supplies Ground (Note 21) GND -0.3 - (VD+)-0.3 V
Positive Digital (Note 22) VD+ -0.3 - 6.0 V
Positive Analog VA+ -0.3 - 6.0 V
Input Current, Any Pin Except Supplies (Notes 23 and 24) Iin - - ±10 mA
Output Current Iout - - ±25 mA
Power Dissipation (Total) (Note 25) - - 500 mW
Analog Input Voltage AIN and VREF pins VINA -0.3 - (VA+)+0.3 V
Digital Input Voltage VIND -0.3 - (VD+)+0.3 V
Ambient Operating Temperature TA -40 - 85 °C
Storage Temperature Tstg -65 - 150 °C
Notes: 21. No pin should go more positive than (VA+) + 0.3 V.
22. VD+ must always be less than (VA+) + 0.3 V, and can never exceed +6.0 V.
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
24. Transient currents of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
25. Total power dissipation, including all input currents and output currents.
*WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

DS125F3 9
 CS5509

GENERAL DESCRIPTION Calibration

The CS5509 is a low power, 16-bit, monolithic After the initial application of power, the CS5509
CMOS A/D converter designed specifically for must enter the calibration state prior to performing
measurement of dc signals. The CS5509 includes a accurate conversions. During calibration, the chip
delta-sigma charge-balance converter, a voltage executes a two-step process. The device first per-
reference, a calibration microcontroller with forms an offset calibration and then follows this
SRAM, a digital filter and a serial interface. with a gain calibration. The two calibration steps
The CS5509 is optimized to operate from a 32.768 determine the zero reference point and the full scale
kHz crystal but can be driven by an external clock reference point of the converter's transfer function.
whose frequency is between 30kHz and 330kHz. From these points it calibrates the zero point and a
When the digital filter is operated with a 32.768 gain slope to be used to properly scale the output
kHz clock, the filter has zeros precisely at 50 and digital codes when doing conversions.
60 Hz line frequencies and multiples thereof. The calibration state is entered whenever the CAL
The CS5509 uses a "start convert" command to and CONV pins are high at the same time. The state
start a convolution cycle on the digital filter. Once of the CAL and CONV pins at power-on are recog-
the filter cycle is completed, the output port is up- nized as commands, but will not be executed until
dated.When operated with a 32.768kHz clock the the end of the 1800 clock cycle wake-up period.
ADC converts and updates its output port at 20 If CAL and CONV become active (high) during the
samples/sec.The output port operates in a synchro- 1800 clock cycle wake-up time, the converter will
nous externally-clocked interface format. wait until the wake-up period elapses before exe-
cuting the calibration. If the wake-up time has
THEORY OF OPERATION elapsed, the converter will be in the standby mode
Basic Converter Operation waiting for instruction and will enter the calibration
cycle immediately if CAL and CONV become ac-
The CS5509 A/D converter has three operating
tive. The calibration lasts for 3246 clock cycles.
states. These are stand-by, calibration, and conver-
Calibration coefficients are then retained in the
sion. When power is first applied, an internal pow-
SRAM (static RAM) for use during conversion.
er-on reset delay of about 10 ms resets all of the
logic in the device. The oscillator must then begin The state of BP/UP is ignored during calibration
oscillating before the device can be considered but should remain stable throughout the calibration
functional. After the power-on reset is applied, the period to minimize noise.
device enters the wake-up period for 1800 clock When conversions are performed in unipolar mode
cycles after clock is present. This allows the delta- or in bipolar mode, the converter uses the same cal-
sigma modulator and other circuitry (which are op- ibration factors to compute the digital output code.
erating with very low currents) to reach a stable The only difference is that in bipolar mode the on-
bias condition prior to entering into either the cali- chip microcontroller offsets the computed output
bration or conversion states. During the 1800 cycle word by a code value of 8000H. This means that the
wake-up period, the device can accept an input bipolar measurement range is not calibrated from
command. Execution of this command will not oc- full scale positive to full scale negative. Instead it is
cur until the complete wake-up period elapses. If calibrated from the bipolar zero scale point to full
no command is given, the device enters the standby scale positive. The slope factor is then extended be-
state. low bipolar zero to accommodate the negative in-

10 DS125F3
 CS5509

put signals. The converter can be used to convert The BP/UP pin is not a latched input. The BP/UP
both unipolar and bipolar signals by changing the pin controls how the output word from the digital
BP/UP pin. Recalibration is not required when filter is processed. In bipolar mode the output word
switching between unipolar and bipolar modes. computed by the digital filter is offset by 8000H
At the end of the calibration cycle, the on-chip mi- (see Understanding Converter Calibration). BP/UP
crocontroller checks the logic state of the CONV can be changed after a conversion is started as long
signal. If the CONV input is low the device will en- as it is stable for 82 clock cycles of the conversion
ter the standby mode where it waits for further in- period prior to DRDY falling. If one wishes to in-
struction. If the CONV signal is high at the end of termix measurement of bipolar and unipolar signals
the calibration cycle, the converter will enter the on various input signals, it is best to switch the
conversion state and perform a conversion on the BP/UP pin immediately after DRDY falls and
input channel. The CAL signal can be returned low leave BP/UP stable until DRDY falls again.
any time after calibration is initiated. CONV can The digital filter in the CS5509 has a Finite Im-
also be returned low, but it should never be taken pulse Response and is designed to settle to full ac-
low and then taken back high until the calibration curacy in one conversion time.
period has ended and the converter is in the standby If CONV is left high, the CS5509 will perform con-
state. If CONV is taken low and then high again tinuous conversions. The conversion time will be
with CAL high while the converter is calibrating, 1622 clock cycles. If conversion is initiated from
the device will interrupt the current calibration cy- the standby state, there may be up to two XIN clock
cle and start a new one. If CAL is taken low and cycles of uncertainty as to when conversion actual-
CONV is taken low and then high during calibra- ly begins. This is because the internal logic oper-
tion, the calibration cycle will continue as the con- ates at one half the external clock rate and the exact
version command is disregarded. The state of phase of the internal clock may be 180° out of
BP/UP is not important during calibrations. phase relative to the XIN clock. When a new con-
If an "end of calibration" signal is desired, pulse the version is initiated from the standby state, it will
CAL signal high while leaving the CONV signal take up to two XIN clock cycles to begin. Actual
high continuously. Once the calibration is complet- conversion will use 1624 clock cycles before
ed, a conversion will be performed. At the end of DRDY goes low to indicate that the serial port has
the conversion, DRDY will fall to indicate the first been updated. See the Serial Interface Logic sec-
valid conversion after the calibration has been tion of the data sheet for information on reading
completed. data from the serial port.
Conversion In the event the A/D conversion command (CONV
going positive) is issued during the conversion
The conversion state can be entered at the end of
state, the current conversion will be terminated and
the calibration cycle, or whenever the converter is
a new conversion will be initiated.
idle in the standby mode. If CONV is taken high to
initiate a calibration cycle ( CAL also high), and re- Voltage Reference
mains high until the calibration cycle is completed The CS5509 uses a differential voltage reference
(CAL is taken low after CONV transitions high), input. The positive input is VREF+ and the nega-
the converter will begin a conversion upon comple- tive input is VREF-. The voltage between VREF+
tion of the calibration period. and VREF- can range from 1 volt minimum to 3.6
volts maximum. The gain slope will track changes

DS125F3 11
 CS5509

in the reference without recalibration, accommo- Unipolar Input Output Bipolar Input
dating ratiometric applications. Voltage Codes Voltage
> (VREF - 1.5 LSB) FFFF > (VREF - 1.5 LSB)
Analog Input Range VREF - 1.5 LSB FFFF VREF - 1.5 LSB
----------------
FFFE
The analog input range is set by the magnitude of
VREF/2 - 0.5 LSB 8000- -0.5 LSB
the voltage between the VREF+ and VREF- pins. --------------
7FFF
In unipolar mode the input range will equal the +0.5 LSB 0001 -VREF + 0.5 LSB
-------------
magnitude of the voltage reference. In bipolar 0000
mode the input voltage range will equate to plus < (+0.5 LSB) 0000 < (-VREF + 0.5 LSB)
and minus the magnitude of the voltage reference. Note: Table excludes common mode voltage on the
While the voltage reference can be as great as 3.6 signal and reference inputs.
volts, its common mode voltage can be any value as Table 1. Output Coding

long as the reference inputs VREF+ and VREF- offset and gain. The CS5509 device has no missing
stay within the supply voltages VA+ and GND. code performance to 16-bits. Figure4 illustrates the
The differential input voltage can also have any DNL of the CS5509. The converter achieves Com-
common mode value as long as the maximum sig- mon Mode Rejection (CMR) at dc of 105dB typi-
nal magnitude stays within the supply voltages. cal, and CMR at 50 and 60Hz of 120dB typical.
The A/D converter is intended to measure dc or low The CS5509 can experience some drift as tempera-
frequency inputs. It is designed to yield accurate ture changes. The CS5509 uses chopper-stabilized
conversions even with noise exceeding the input techniques to minimize drift. Measurement errors
voltage range as long as the spectral components of due to offset or gain drift can be eliminated at any
this noise will be filtered out by the digital filter. time by recalibrating the converter.
For example, with a 3.0 volt reference in unipolar
mode, the converter will accurately convert an in- Analog Input Impedance Considerations
put dc signal up to 3.0volts with up to 15% over- The analog input of the CS5509 can be modeled as
range for 60Hz noise. A 3.0volt dc signal could illustrated in Figure 5. Capacitors (15 pF each) are
have a 60Hz component which is 0.5volts above used to dynamically sample each of the inputs
the maximum input of 3.0 (3.5 volts peak; 3.0 volts (AIN+ and AIN-). Every half XIN cycle the switch
dc plus 0.5 volts peak noise) and still accurately alternately connects the capacitor to the output of
convert the input signal (XIN = 32.768 kHz). This the buffer and then directly to the AIN pin. When-
assumes that the signal plus noise amplitude stays ever the sample capacitor is switched from the out-
within the supply voltages. put of the buffer to the AIN pin, a small packet of
The CS5509 converters output data in binary for- charge (a dynamic demand of current) is required
mat when converting unipolar signals and in offset from the input source to settle the voltage of the
binary format when converting bipolar signals. Ta- sample capacitor to its final value. The voltage on
ble 1 outlines the output coding for both unipolar the output of the buffer may differ up to 100 mV
and bipolar measurement modes. from the actual input voltage due to the offset volt-
age of the buffer. Timing allows one half of a XIN
Converter Performance clock cycle for the voltage on the sample capacitor
The CS5509 A/D converter has excellent linearity to settle to its final value.
performance. Calibration minimizes the errors in

12 DS125F3
 CS5509

Figure 4. CS5509 Differential Nonlinearity Plot

The VREF+ and VREF- inputs have nearly the

AIN+ same structure as the AIN+ and AIN- inputs.
+ 15 pF Therefore, the discussion on analog input imped-
V os ≤ 100 mV Internal
-
Bias
ance applies to the voltage reference inputs as well.
Voltage
AIN- Digital Filter Characteristics
15 pF
+ The digital filter in the CS5509 is the combination
V os ≤ 100 mV
-
of a comb filter and a low pass filter. The comb fil-
ter has zeros in its transfer function which are opti-
mally placed to reject line interference frequencies
Figure 5. Analog Input Model
(50 and 60 Hz and their multiples) when the
CS5509 is clocked at 32.768 kHz. Figures 6, 7 and
An equation for the maximum acceptable source 8 illustrate the magnitude and phase characteristics
resistance is derived. of the filter. Figure 6 illustrates the filter attenua-
tion from dc to 260 Hz. At exactly 50, 60, 100, and
–1 120 Hz the filter provides over 120 dB of rejection.
Rs max = -------------------------------------------------------------------------------------------------------------------------
Ve Table 2 indicates the filter attenuation for each of
2XIN ( 15pF + C EXT ) ln ---------------------------------------------------
15pF ( 100mV ) the potential line interference frequencies when the
V e + -------------------------------------
15pF + C EXT converter is operating with a 32.768 kHz clock.
This equation assumes that the offset voltage of the The converter yields excellent attenuation of these
buffer is 100 mV, which is the worst case. The val- interference frequencies even if the fundamental
ue of Ve is the maximum error voltage which is ac- line frequency should vary ± 1% from its specified
ceptable. CEXT is the combination of any external frequency. The -3 dB corner frequency of the filter
or stray capacitance. when operating from a 32.768 kHz clock is 17 Hz.
Figure 8 illustrates that the phase characteristics of
For a maximum error voltage (Ve) of 10 µV in the the filter are precisely linear phase.
CS5509 (1/4LSB at 16-bits), the above equation in-
dicates that when operating from a 32.768 kHz If the CS5509 is operated at a clock rate other than
XIN, source resistances up to 110 kΩ are accept- 32.768kHz, the filter characteristics, including the
able in the absence of external capacitance comb filter zeros, will scale with the operating
(CEXT=0). clock frequency. Therefore, optimum rejection of

DS125F3 13
 CS5509

0 180

-20 X1 = 32.768kHz 135

X2 = 330.00kHz
-40 90
Attenuation (dB)

Phase (Degrees)
-60 45

-80 0

-100 -45

-120 -90
XIN = 32.768 kHz
-140 -135
XIN = 32.768 kHz
-160 -180
X1 0 40 80 120 160 200 240 0 5 10 15 20 25 30 35 40 45 50
X2 0 402.83 805.66 1208.5 1611.3 2014.2 2416.9 Frequency (Hz)
Frequency (Hz)
Figure 6. Filter Magnitude Plot to 260 Hz Figure 8. Filter Phase Plot to 50 Hz

Frequency Notch Frequency Minimum

-20 Flatness
Frequency dB (Hz) Depth (Hz) Attenuation
1 -0.010 (dB) (dB)
-40 2 -0.041
50 125.6 50 ±1% 55.5
Attenuation (dB)

3 -0.093

-60 4 -0.166 60 126.7 60 ±1% 58.4

5 -0.259 100 145.7 100 ±1% 62.2
6 -0.374
-80 7 -0.510
120 136.0 120 ±1% 68.4
8 -0.667 150 118.4 150 ±1% 74.9
-100 9 -0.846 180 132.9 180 ±1% 87.9
10 -1.047
XIN = 32.768 kHz 200 102.5 200 ±1% 94.0
17 -3.093
-120 240 108.4 240 ±1% 104.4

-140 Table 2. Filter Notch Attenuation (XIN = 32.768 kHz)

0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz)
Anti-Alias Considerations for Spectral
Figure 7. Filter Magnitude Plot to 50 Hz
Measurement Applications
Input frequencies greater than one half the output
line frequency interference will occur with the word rate (CONV = 1) may be aliased by the con-
CS5509 running at 32.768kHz. verter. To prevent this, input signals should be lim-
ited in frequency to no greater than one half the
output word rate of the converter (when CONV
=1). Frequencies close to the modulator sample rate
(XIN/2) and multiples thereof may also be aliased.
If the signal source includes spectral components
above one half the output word rate (when CONV
= 1) these components should be removed by
means of low-pass filtering prior to the A/D input

14 DS125F3
 CS5509

to prevent aliasing. Spectral components greater Serial Interface Logic

than one half the output word rate on the VREF in- The digital filter in the CS5509 takes 1624 clock
puts (VREF+ and VREF-) may also be aliased. Fil- cycles to compute an output word once a conver-
tering of the reference voltage to remove these sion begins. At the end of the conversion cycle, the
spectral components from the reference voltage is filter will attempt to update the serial port. Two
desirable. clock cycles prior to the update DRDY will go
Crystal Oscillator high. When DRDY goes high just prior to a port up-
date it checks to see if the port is either empty or
The CS5509 is designed to be operated using a
unselected (CS = 1). If the port is empty or unse-
32.768kHz "tuning fork" type crystal. One end of
lected, the digital filter will update the port with a
the crystal should be connected to the XIN input.
new output word. When new data is put into the
The other end should be attached to XOUT. Short
port DRDY will go low.
lead lengths should be used to minimize stray ca-
pacitance. Reading Serial Data
Over the industrial temperature range (-40 to SDATA is the output pin for the serial data. When
+85 °C) the on-chip gate oscillator will oscillate CS goes low after new data becomes available
with other crystals in the range of 30kHz to 53 kHz. (DRDY goes low), the SDATA pin comes out of
The chip will operate with external clock frequen- Hi-Z with the MSB data bit present. SCLK is the
cies from 30kHz to 330kHz over the industrial tem- input pin for the serial clock. If the MSB data bit is
perature range. The 32.768 kHz crystal is normally on the SDATA pin, the first rising edge of SCLK
specified as a time-keeping crystal with tight spec- enables the shifting mechanism. This allows the
ifications for both initial frequency and for drift falling edges of SCLK to shift subsequent data bits
over temperature. To maintain excellent frequency out of the port. Note that if the MSB data bit is out-
stability, these crystals are specified only over lim- put and the SCLK signal is high, the first falling
ited operating temperature ranges (i.e. -10 °C to edge of SCLK will be ignored because the shifting
+60 °C) by the manufacturers. Applications of mechanism has not become activated. After the
these crystals with the CS5509 does not require first rising edge of SCLK, each subsequent falling
tight initial tolerance or low tempco drift. There- edge will shift out the serial data. Once the LSB is
fore, a lower cost crystal with looser initial toler- present, the falling edge of SCLK will cause the
ance and tempco will generally be adequate for use SDATA output to go to Hi-Z and DRDY to return
with the CS5509. Also check with the manufactur- high. The serial port register will be updated with a
er about wide temperature range application of new data word upon the completion of another con-
their standard crystals. Generally, even those crys- version if the serial port has been emptied, or if the
tals specified for limited temperature range will op- CS is inactive (high).
erate over much larger ranges if frequency stability CS can be operated asynchronously to the DRDY
over temperature is not a requirement. The frequen- signal. The DRDY signal need not be monitored as
cy stability can be as bad as ±3000 ppm over the long as the CS signal is taken low for at least two
operating temperature range and still be typically XIN clock cycles plus 200ns prior to SCLK being
better than the line frequency (50 Hz or 60Hz) sta- toggled. This ensures that CS has gained control
bility over cycle-to-cycle during the course of a over the serial port.
day.

DS125F3 15
 CS5509

Power Supplies and Grounding Figure 9a illustrates the System Connection Dia-
The analog and digital supply pins to the CS5509 gram for the CS5509. Note that all supply pins are
are brought out on separate pins to minimize noise bypassed with 0.1 µF capacitors and that the VD+
coupling between the analog and digital sections of digital supply is derived from the VA+ supply. Fig-
the chip. In the digital section of the chip the supply ure 9b illustrates the CS5509 operating from a +5V
current flows into the VD+ pin and out of the GND analog supply and +3.3V digital supply.
pin. As a CMOS device, the CS5509 requires that When using separate supplies for VA+ and VD+,
the supply voltage on the VA+ pin always be more VA+ must be established first. VD+ should never
positive than the voltage on any other pin of the de- become more positive than VA+ under any operat-
vice. If this requirement is not met, the device can ing condition. Remember to investigate transient
latch-up or be damaged. In all circumstances the power-up conditions, when one power supply may
VA+ voltage must remain more positive than the have a faster rise time.
VD+ or GND pins; VD+ must remain more posi-
tive than the GND pin.

16 DS125F3
 CS5509

10Ω

+5V 0.1 µF 0.1 µF

Analog 11 13
Supply
VA+ VD+

Optional
4 14
Clock XIN SCLK Serial
Source
Data
5 15
32.768 kHz XOUT SDATA Interface

CS5509

7
Analog AIN+
Signal 8
AIN-
1
CS
2
CONV
3 Control
CAL
9 6 Logic
+ VREF+
Voltage BP/UP
Reference 10 16
- VREF- DRDY

GND
12

Figure 9a. System Connection Diagram Using a Single Supply

DS125F3 17
 CS5509

Note: VD+ must never be more positive than VA+

+3.3V to +5V
+5V 0.1 µF 0.1 µF Digital
Analog Supply
11 13
Supply
VA+ VD+

Optional
4 14
Clock XIN SCLK Serial
Source
Data
5 15
32.768 kHz XOUT SDATA Interface

CS5509

7
Analog AIN+
Signal 8
AIN-
1
CS
2
CONV
3 Control
CAL
+ 9 6 Logic
VREF+
Voltage BP/UP
Reference 10 16
- VREF- DRDY

GND
12

Figure 9b. System Connection Diagram Using Split Supplies

18 DS125F3
 CS5509

PIN DESCRIPTIONS*

CHIP SELECT CS 1 16 DRDY DATA READY

CONVERT CONV 2 15 SDATA SERIAL DATA OUTPUT
CALIBRATE CAL 3 14 SCLK SERIAL CLOCK INPUT
CRYSTAL IN XIN 4 13 VD+ POSITIVE DIGITAL POWER
CRYSTAL OUT XOUT 5 12 GND GROUND
BIPOLAR / UNIPOLAR BP/UP 6 11 VA+ POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT AIN+ 7 10 VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN- 8 9 VREF+ VOLTAGE REFERENCE INPUT

* Pinout applies to both PDIP and SOIC

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 1.

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 16.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 15.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 14.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.

DS125F3 19
 CS5509

Control Input Pins

CAL - Calibrate, Pin 3.

When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.

CONV - Convert, Pin 2.

The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If CONV
is held high (CAL low) the converter will do continuous conversions.

BP/UP - Bipolar/Unipolar, Pin 6.

The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Inputs, Pins 7, 8.

Analog differential inputs to the delta-sigma modulator.

VREF+, VREF- - Differential Voltage Reference Inputs, Pins 9, 10.

A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Power Supply Connections

VA+ - Positive Analog Power, Pin 11.

Positive analog supply voltage. Nominally +5 volts.

VD+ - Positive Digital Power, Pin 13.

Positive digital supply voltage. Nominally +5 volts or +3.3 volts.

GND - Ground, Pin 12.

Ground.

20 DS125F3
 CS5509

SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and
the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of
full-scale.

Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - LSB]. Units
are in LSBs.

Unipolar Offset
The deviation of the first code transition from the ideal ( LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal ( LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

DS125F3 21
 CS5509

PACKAGE DIMENSIONS

MILLIMETERS INCHES
pins MIN NOM MAX
MIN NOM MAX
16 9.91 10.16 10.41 0.390 0.400 0.410
20 12.45 12.70 12.95 0.490 0.500 0.510
24 14.99 15.24 15.50 0.590 0.600 0.610
D 28 17.53 17.78 18.03 0.690 0.700 0.710

MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
SOIC
E1 E A 2.41 2.54 2.67 0.095 0.100 0.105
A1 0.127 - 0.300 0.005 - 0.012
A2 2.29 2.41 2.54 0.090 0.095 0.100
b 0.33 0.46 0.51 0.013 0.018 0.020
c 0.203 0.280 0.381 0.008 0.011 0.015
D see table above
E 10.11 10.41 10.67 0.398 0.410 0.420
E1 7.42 7.49 7.57 0.292 0.295 0.298
A2 e
A µ 1.14 1.27 1.40 0.040 0.050 0.055
c L 0.41 - 0.89 0.016 - 0.035
A1 L µ
e b 0° - 8° 0° - 8°

22 DS125F3
 CS5509

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Peak Relfow Temp MSL Rating* Maximum Floor Life
CS5509-ASZ (lead free) 260 °C 3 7 Days

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

DS125F3 23
 CS5509

REVISION HISTORY
Revision Date Changes
F1 Aug ‘97 First “final” release.
F2 Aug ‘05 Added lead-free device ordering info. Added legal notice. Added MSL data.
F3 Jul ‘09 Removed PDIP and leaded (Pb) devices from ordering information.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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24 DS125F3