CS5504

Low Power, 20-Bit A/D Converter

Features Description
l Delta-Sigma A/D Converter The CS5504 is a 2-channel, fully differential 20-bit, seri-
- 20-bit No Missing Codes al-output CMOS A/D converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
- Linearity Error: ±0.0007%FS low cost, high resolution measurement at output word
l 2 Differential Inputs rates up to 200 samples per second.
- Pin Selectable Unipolar/Bipolar Ranges The on-chip digital filter offers superior line rejection at
- Common Mode Rejection 50 Hz and 60 Hz when the device is operated from a
105 dB @ dc 32.768 kHz clock (output word rate = 20 Hz.).
120 dB @ 50, 60 Hz
The CS5504 has on-chip self-calibration circuitry which
l Either 5V or 3.3V Digital Interface can be initiated at any time or temperature to ensure
l On-chip Self-Calibration Circuitry minimum offset and full-scale errors.
l Output Update Rates up to 200/second Low power, high resolution and small package size
l Low Power Consumption: 4.4 mW make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery-
powered instruments.

ORDERING INFORMATION
CS5504-BP -40° to +85° C 20-pin Plastic DIP
CS5504-BS -40° to +85° C 20-pin SOIC
I

VREF+ VREF- VA+ VA- DGND VD+

12 13 14 15 16 17

2
8 CS
AIN1+ 18
Serial SCLK
10 Interface
AIN1- 4th-Order 19
Digital Logic SDATA
9 MUX Delta-Sigma
Filter 20
AIN2+ Modulator DRDY
11
AIN2-

4
1 CAL
A0 Calibration µC 7
BP/UP
Calibration SRAM OSC

3 5 6

CONV XIN XOUT

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1997 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS126F1
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 1
 CS5504

ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
3.3V ± 5%; VREF+ = 2.5V, VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to GND
at AIN.) (Notes 1, 2)

Parameter* Min Typ Max Units

Specified Temperature Range -40 to +85 °C
Accuracy
Linearity Error - 0.0007 0.0015 ±%FS
Differential Nonlinearity (No Missing Codes) 20 - - Bits
Full Scale Error (Note 3) - ±4 ±32 LSB
Full Scale Drift (Note 4) - ±8 - LSB
Unipolar Offset (Note 3) - ±8 ±32 LSB
Unipolar Offset Drift (Note 4) - ±8 - LSB
Bipolar Offset (Note 3) - ±4 ±16 LSB
Bipolar Offset Drift (Note 4) - ±4 - LSB
Noise (Referred to Output) - 2.6 - LSBrms
Analog Input
Analog Input Range: Unipolar (Note 5) - 0 to +2.5 - V
Bipolar - ±2.5 - V
Common Mode Rejection: dc - 105 - dB
50, 60- Hz (Note 2) 120 - - dB
Off Channel Isolation - 120 - dB
Input Capacitance - 15 - pF
DC Bias Current (Note 1) - 5 - nA
Power Supplies
DC Power Supply Currents: ITotal - 465 600 µA
IAnalog - 425 - µA
IDigital - 40 - µA
Power Dissipation (Note 6) - 4.4 6.0 mW
Power Supply Rejection - 80 - dB
Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5504’s source
impedance requirements. Refer to the text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25 °C
5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. All outputs unloaded. All inputs CMOS levels.

* Refer to the Specification Definitions immediately following the Pin Description Section.

Specifications are subject to change without notice.

2 DS126F1
 CS5504

DYNAMIC CHARACTERISTICS
Parameter Symbol Ratio Units
Modulator Sampling Frequency fs fclk/2 Hz
Output Update Rate (CONV = 1) fout fclk/1622 Hz
Filter Corner Frequency f-3dB fclk/1928 Hz
Settling Time to 1/2 LSB (FS Step) ts 1/fout s

5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%;
DGND = 0.) (Notes 2, 7)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN VIH 3.5 - - V
All Pins Except XIN VIH 2.0 - - V
Low-Level Input Voltage: XIN VIL - - 1.5 V
All Pins Except XIN VIL - - 0.8 V
High-Level Output Voltage (Note 8) VOH (VD+)-1.0 - - V
Low-Level Output Voltage Iout = 1.6 mA VOL - - 0.4 V
Input Leakage Current Iin - ±1 ±10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF
Notes: 7. All measurements are performed under static conditions.
8. Iout = -100 µA. This guarantees the ability to drive one TTL load. (V OH = 2.4V @ Iout = -40 µA).

3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
VA- = -5V ±10%; GND = 0V.) (Notes 2, 7)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage: XIN VIH 0.7VD+ - - V
All Pins Except XIN VIH 0.6VD+ - - V
Low-Level Input Voltage: XIN VIL - - 0.3VD+ V
All Pins Except XIN VIL - - 0.16VD+ V
High-Level Output Voltage Iout = -400 µA VOH (VD+)-0.3 - - V
Low-Level Output Voltage Iout = 400 µA VOL - - 0.3 V
Input Leakage Current Iin - ±1 ±10 µA
3-State Leakage Current IOZ - - ±10 µA
Digital Output Pin Capacitance Cout - 9 - pF

DS126F1 3
 CS5504

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Oscillator XIN 30.0 32.768 53.0 kHz
External Clock fclk 30 - 330 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 9) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times: Any Digital Input (Note 9) tfall - - 1.0 µs
Any Digital Output - 20 - ns
Start-Up
Power-On Reset Period (Note 10) tres - 10 - ms
Oscillator Start-up Time XTAL = 32.768 kHz (Note 11) tosu - 500 - ms
Wake-up Period (Note 12) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL=1) (Note 13) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration t cal - 3246/fclk - s
Conversion
Set Up Time A0 to CONV High tsac 50 - - ns
Hold Time A0 after CONV High thca 100 - - ns
CONV Pulse Width tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk - - s
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 14) tcon - 1624/fclk - s
Notes: 9. Specified using 10% and 90% points on waveform of interest.
10. An internal power-on-reset is activated whenever power is applied to the device.
11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
12. The wake-up period begins once the oscillator starts; or when using an external fclk, after the
power-on reset time elapses.
13. Calibration can also be initiated by pulsing CAL high while CONV=1.
14. Conversion time will be 1622/fclk if CONV remains high continuously.

4 DS126F1
 CS5504

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Master Clock Frequency Internal Oscillator XIN 30.0 32.768 53.0 kHz
External Clock fclk 30 - 330 kHz
Master Clock Duty Cycle 40 - 60 %
Rise Times: Any Digital Input (Note 9) trise - - 1.0 µs
Any Digital Output - 50 - ns
Fall Times: Any Digital Input (Note 9) tfall - - 1.0 µs
Any Digital Output - 20 - ns
Start-Up
Power-On Reset Period (Note 10) tres - 10 - ms
Oscillator Start-up Time XTAL = 32.768 kHz (Note 11) tosu - 500 - ms
Wake-up Period (Note 12) twup - 1800/fclk - s
Calibration
CONV Pulse Width (CAL=1) (Note 13) tccw 100 - - ns
CONV and CAL High to Start of Calibration tscl - - 2/fclk+200 ns
Start of Calibration to End of Calibration t cal - 3246/fclk - s
Conversion
Set Up Time A0 to CONV High tsac 50 - - ns
Hold Time A0 after CONV High thca 100 - - ns
CONV Pulse Widh tcpw 100 - - ns
CONV High to Start of Conversion tscn - - 2/fclk+200 ns
Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk - - s
Hold Time BP/UP stable after DRDY falls tbuh 0 - - ns
Start of Conversion to End of Conversion (Note 14) tcon - 1624/fclk - s

DS126F1 5
 CS5504

XIN

XIN/2

CAL
t ccw
CONV
t scl t cal
STATE Standby Calibration Standby

Figure 1. Calibration Timing (Not to Scale)

XIN

XIN/2

A0
t sac t hca
CONV
t cpw
DRDY

BP/UP
t bus t buh
t scn t con
STATE Standby Conversion Standby

Figure 2. Conversion Timing (Not to Scale)

6 DS126F1
 CS5504

5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%;

VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Serial Clock fsclk 0 - 2.5 MHz
Serial Clock Pulse Width High tph 200 - - ns
Pulse Width Low tpl 200 - - ns
Access Time: CS Low to data valid (Note 15) tcsd - 60 200 ns
Maximum Delay Time: (Note 16)
SCLK falling to new SDATA bit tdd - 150 310 ns
Output Float Delay: CS high to output Hi-Z (Note 17) tfd1 - 60 150 ns
SCLK falling to Hi-Z tfd2 - 160 300 ns
Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high
sooner than 2/fclk + 200 ns after CS goes low.
16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
17. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ±
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter Symbol Min Typ Max Units

Serial Clock fsclk 0 - 1.25 MHz
Serial Clock Pulse Width High tph 200 - - ns
Pulse Width Low tpl 200 - - ns
Access Time: CS Low to data valid (Note 15) tcsd - 100 200 ns
Maximum Delay Time: (Note 16)
SCLK falling to new SDATA bit tdd - 400 600 ns
Output Float Delay: CS high to output Hi-Z (Note 17) tfd1 - 70 150 ns
SCLK falling to Hi-Z tfd2 - 320 500 ns

DS126F1 7
 CS5504

DRDY

CS
t csd t fd1
SDATA(o) Hi-Z MSB MSB-1 MSB-2
t dd
SCLK(i)

DRDY

CS
t csd
SDATA(o) Hi-Z MSB MSB-1 LSB+2 LSB+1 LSB
t dd t ph t fd2
SCLK(i)
t pl

Figure 3. Timing Relationships; Serial Data Read (Not to Scale)

8 DS126F1
 CS5504

RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 18)

Parameter Symbol Min Typ Max Units

DC Power Supplies:
Positive Digital VD+ 3.15 5.0 5.5 V
(VA+) - (VA-) Vdiff 4.5 10 11 V
Positive Analog VA+ 4.5 5.0 11 V
Negative Analog VA- 0 -5.0 -5.5 V
Analog Reference Voltage (VREF+)- 1.0 2.5 3.6 V
(Note 19) (VREF-)
Analog Input Voltage: (Note 20)
Unipolar VAIN 0 - (VREF+)-(VREF-) V
Bipolar VAIN -((VREF+)-(VREF-)) - (VREF+)-(VREF-) V
Notes: 18. All voltages with respect to ground.
19. The CS5504 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
20. The CS5504 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode
the CS5504 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-))
and will output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5504
will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output
all 0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).

ABSOLUTE MAXIMUM RATINGS*

Parameter Symbol Min Typ Max Units
DC Power Supplies: Digital Ground (Note 21) DGND -0.3 - (VD+)-0.3 V
Positive Digital (Note 22) VD+ -0.3 - 6.0 or VA+ V
Positive Analog VA+ -0.3 - 12 V
Negative Analog VA- +0.3 - -6.0 V
Input Current, Any Pin Except Supplies (Notes 23, 24) Iin - - ±10 mA
Output Current Iout - - ±25 mA
Power Dissipation (Total) (Note 25) - - 500 mW
Analog Input Voltage AIN and VREF pins VINA (VA-)-0.3 - (VA+)+0.3 V
Digital Input Voltage VIND -0.3 - (VD+)+0.3 V
Ambient Operating Temperature TA -40 - 85 °C
Storage Temperature Tstg -65 - 150 °C
Notes: 21. No pin should go more positive than (VA+)+0.3V.
22. VD+ must always be less than (VA+) +0.3V, and can never exceed +6.0 V.
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
25. Total power dissipation, including all input currents and output currents.
* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

DS126F1 9
 CS5504

GENERAL DESCRIPTION tion of this command will not occur until the
complete wake-up period elapses. If no com-
The CS5504 is a low power, 20-bit, monolithic mand is given, the device enters the standby
CMOS A/D converter designed specifically for state.
measurement of dc signals. The CS5504 in-
cludes a delta-sigma charge-balance converter, a Calibration
voltage reference, a calibration micro controller
with SRAM, a digital filter and a serial interface. After the initial application of power, the
CS5504 must enter the calibration state prior to
The CS5504 is optimized to operate from a performing accurate conversions. During calibra-
32.768 kHz crystal but can be driven by an ex- tion, the chip executes a two-step process. The
ternal clock whose frequency is between 30 kHz device first performs an offset calibration and
and 330 kHz. When the digital filter is operated then follows this with a gain calibration. The
with a 32.768 kHz clock, the filter has zeros pre- two calibration steps determine the zero refer-
cisely at 50 and 60 Hz line frequencies and ence point and the full scale reference point of
multiples thereof. the converter’s transfer function. From these
points it calibrates the zero point and a gain
The CS5504 uses a "start convert" command to slope to be used to properly scale the output
latch the input channel selection and to start a digital codes when doing conversions.
convolution cycle on the digital filter. Once the
filter cycle is completed, the output port is up- The calibration state is entered whenever the
dated. When operated with a 32.768 kHz clock CAL and CONV pins are high at the same time.
the ADC converts and updates its output port at The state of the CAL and CONV pins at power-
20 samples/sec. The output port operates in a on are recognized as commands, but will not be
synchronous externally-clocked interface format. executed until the end of the 1800 clock cycle
wake-up period.

THEORY OF OPERATION If CAL and CONV become active (high) during

the 1800 clock cycle wake-up time, the con-
Basic Converter Operation verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up
The CS5504 A/D converter has three operating time has elapsed, the converter will be in the
states. These are stand-by, calibration, and con- standby mode waiting for instruction and will
version. When power is first applied, an internal enter the calibration cycle immediately if CAL
power-on reset delay of about 10 ms resets all of and CONV become active. The calibration lasts
the logic in the device. The oscillator must then for 3246 clock cycles. Calibration coefficients
begin oscillating before the device can be con- are then retained in the SRAM (static RAM) for
sidered functional. After the power-on reset is use during conversion.
applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This The states of A0 and BP/UP are ignored during
allows the delta-sigma modulator and other cir- calibration but should remain stable throughout
cuitry (which are operating with very low the calibration period to minimize noise.
currents) to reach a stable bias condition prior to
entering into either the calibration or conversion When conversions are performed in unipolar
states. During the 1800 cycle wake-up period, mode or in bipolar mode, the converter uses the
the device can accept an input command. Execu- same calibration factors to compute the digital
10 DS126F1
 CS5504

output code. The only difference is that in bipo- Conversion

lar mode the on-chip microcontroller offsets the
computed output word by a code value of The conversion state can be entered at the end of
8000H. This means that the bipolar measure- the calibration cycle, or whenever the converter
ment range is not calibrated from full scale is idle in the standby mode. If CONV is taken
positive to full scale negative. Instead it is cali- high to initiate a calibration cycle ( CAL also
brated from the bipolar zero scale point to full high), and remains high until the calibration cy-
scale positive. The slope factor is then extended cle is completed (CAL is taken low after CONV
below bipolar zero to accommodate the negative transitions high), the converter will begin a con-
input signals. The converter can be used to con- version upon completion of the calibration
vert both unipolar and bipolar signals by period. The device will perform a conversion on
changing the BP/UP pin. Recalibration is not re- the input channel selected by A0 when CONV
quired when switching between unipolar and transitions high. Table 1 indicates the multi-
bipolar modes. plexer channel selection truth table.

At the end of the calibration cycle, the on-chip A0 Channel Addressed

micro controller checks the logic state of the 0 AIN1
CONV signal. If the CONV input is low the de- 1 AIN2
vice will enter the standby mode where it waits Table 1. Multiplexer Truth Table
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the con- The A0 input is latched internal to the CS5504
verter will enter the conversion state and when CONV rises. A0 has internal pull-down
perform a conversion on the input channel. The circuits which default the multiplexer to channel
CAL signal can be returned low any time after AIN1.
calibration is initiated. CONV can also be re-
turned low, but it should never be taken low and The BP/UP pin is not a latched input. The
then taken back high until the calibration period BP/UP pin controls how the output word from
has ended and the converter is in the standby the digital filter is processed. In bipolar mode
state. If CONV is taken low and then high the output word computed by the digital filter is
again with CAL high while the converter is cali- offset by 80000H (see Understanding Converter
brating, the device will interrupt the current Calibration). BP/UP can be changed after a con-
calibration cycle and start a new one. If CAL is version is started as long as it is stable for 82
taken low and CONV is taken low and then high clock cycles of the conversion period prior to
during calibration, the calibration cycle will DRDY falling. If one wishes to intermix meas-
continue as the conversion command is disre- urement of bipolar and unipolar signals on
garded. The state of BP/UP is not important various input channels, it is best to switch the
during calibrations. BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV The digital filter in the CS5504 has a Finite Im-
signal high continuously. Once the calibration is pulse Response and is designed to settle to full
completed, a conversion will be performed. At accuracy in one conversion time.
the end of the conversion, DRDY will fall to in-
dicate the first valid conversion after the If CONV is left high, the CS5504 will perform
calibration has been completed. continuous conversions. The conversion time
will be 1622 clock cycles. If conversion is initi-
DS126F1 11
 CS5504

ated from the standby state, there may be up to as the maximum signal magnitude stays within
two XIN clock cycles of uncertainty as to when the supply voltages.
conversion actually begins. This is because the
internal logic operates at one half the external The A/D converter is intended to measure dc or
clock rate and the exact phase of the internal low frequency inputs. It is designed to yield ac-
clock may be 180° out of phase relative to the curate conversions even with noise exceeding
XIN clock. When a new conversion is initiated the input voltage range as long as the spectral
from the standby state, it will take up to two components of this noise will be filtered out by
XIN clock cycles to begin. Actual conversion the digital filter. For example, with a 3.0 volt
will use 1624 clock cycles before DRDY goes reference in unipolar mode, the converter will
low to indicate that the serial port has been up- accurately convert an input dc signal up to
dated. See the Serial Interface Logic section of 3.0 volts with up to 15% overrange for 60 Hz
the data sheet for information on reading data noise. A 3.0 volt dc signal could have a 60 Hz
from the serial port. component which is 0.5 volts above the maxi-
mum input of 3.0 (3.5 volts peak; 3.0 volts dc
In the event the A/D conversion command plus 0.5 volts peak noise) and still accurately
(CONV going positive) is issued during the con- convert the input signal (XIN = 32.768 kHz).
version state, the current conversion will be This assumes that the signal plus noise ampli-
terminated and a new conversion will be initi- tude stays within the supply voltages.
ated.
The CS5504 converters output data in binary
Voltage Reference format when converting unipolar signals and in
offset binary format when converting bipolar
The CS5504 uses a differential voltage reference signals. Table 2 outlines the output coding for
input. The positive input is VREF+ and the both unipolar and bipolar measurement modes.
negative input is VREF-. The voltage between
VREF+ and VREF- can range from 1 volt mini- Unipolar Input Output Bipolar Input
mum to 3.6 volts maximum. The gain slope will Voltage Codes Voltage
track changes in the reference without recalibra- >(VREF - 1.5 LSB) FFFFF >(VREF - 1.5 LSB)
tion, accommodating ratiometric applications. VREF - 1.5 LSB FFFFF
VREF - 1.5 LSB
Analog Input Range FFFFE
80000
VREF/2 - 0.5 LSB -0.5 LSB
The analog input range is set by the magnitude
7FFFF
of the voltage between the VREF+ and VREF-
00001
pins. In unipolar mode the input range will + 0.5 LSB -VREF + 0.5 LSB
equal the magnitude of the voltage reference. In 00000
bipolar mode the input voltage range will equate <(+ 0.5 LSB) 00000 <(VREF + 0.5 LSB)
to plus and minus the magnitude of the voltage
Note: Table excludes common mode voltage on the
reference. While the voltage reference can be as signal and reference inputs.
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs Table 2. Output Coding
VREF+ and VREF- stay within the supply volt-
ages for the A/D. The differential input voltage
can also have any common mode value as long

12 DS126F1
 CS5504

Converter Performance tor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the
The CS5504 A/D converter has excellent linear- actual input voltage due to the offset voltage of
ity performance. Calibration minimizes the the buffer. Timing allows one half of a XIN
errors in offset and gain. The CS5504 device clock cycle for the voltage on the sample capaci-
has no missing code performance to 20-bits. tor to settle to its final value.
The converter achieves Common Mode Rejec-
tion (CMR) at dc of 105 dB typical, and CMR at An equation for the maximum acceptable source
50 and 60 Hz of 120 dB typical. resistance is derived.

The CS5504 can experience some drift as tem- −1

Rsmax =
peratu re chan ges . Th e CS5 504 uses  Ve 
2XIN (15pF + CEXT ) ln  
chopper-stabilized techniques to minimize drift. V + 15pF (100mv) 
Measurement errors due to offset or gain drift  e (15pF + CEXT ) 
 
can be eliminated at any time by recalibrating
the converter.
This equation assumes that the offset voltage of
Analog Input Impedance Considerations the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
The analog input of the CS5504 can be modeled which is acceptable. CEXT is the combination
as illustrated in Figure 4 (the model ignores the of any external or stray capacitance.
multiplexer switch resistance). Capacitors (15 pF
each) are used to dynamically sample each of For a maximum error voltage (Ve) of 600 nV in
the inputs (AIN+ and AIN-). Every half XIN cy- the CS5504 (1/4LSB at 20-bits), the above equa-
cle the switch alternately connects the capacitor tion indicates that when operating from a
to the output of the buffer and then directly to 32.768 kHz XIN, source resistances up to 84 kΩ
the AIN pin. Whenever the sample capacitor is in the CS5504 are acceptable in the absence of
switched from the output of the buffer to the external capacitance (CEXT = 0).
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input The VREF+ and VREF- inputs have nearly the
source to settle the voltage of the sample capaci- same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
AIN+
+ 15 pF
V os ≤ 100 mV Internal Digital Filter Characteristics
-
Bias
Voltage The digital filter in the CS5504 is the combina-
AIN-
15 pF tion of a comb filter and a low pass filter. The
+
V os ≤ 100 mV comb filter has zeros in its transfer function
-
which are optimally placed to reject line interfer-
ence frequencies (50 and 60 Hz and their
multiples) when the CS5504 is clocked at

Figure 4. Analog Input Model

DS126F1 13
 CS5504

-20 X1 = 32.768kHz
X2 = 330.00kHz Frequency Notch Frequency Minimum
-40 Depth Attenuation
(Hz) (dB) (Hz) (dB)
Attenuation (dB)

-60 50 125.6 55.5

50±1%
-80 60 126.7 60±1% 58.4
100 145.7 100±1% 62.2
-100 120 136.0 120±1% 68.4
-120 150 118.4 150±1% 74.9
180 132.9 180±1% 87.9
-140 200 102.5 200±1% 94.0
XIN = 32.768 kHz
-160 240 108.4 240±1% 104.4
X1 0 40 80 120 160 200 240
X2 0 402.83 805.66 1208.5 1611.3 2014.2 2416.9
Frequency (Hz)

Figure 5. Filter Magnitude Plot to 260 Hz Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)

0 180

Flatness 135
-20
Frequency dB
1 -0.010 90
-40 2 -0.041
Phase (Degrees)
Attenuation (dB)

3 -0.093
45
4 -0.166
-60
5 -0.259
0
6 -0.374
-80 7 -0.510
8 -0.667
-45
-100 9 -0.846
10 -1.047 -90
XIN = 32.768 kHz
17 -3.093 XIN = 32.768 kHz
-120 -135

-140 -180
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Frequency (Hz) Frequency (Hz)

Figure 6. Filter Magnitude Plot to 50 Hz Figure 7. Filter Phase Plot to 50 Hz

32.768 kHz. Figures 5, 6 and 7 illustrate the of these interference frequencies even if the fun-
magnitude and phase characteristics of the filter. damental line frequency should vary ± 1% from
Figure 5 illustrates the filter attenuation from dc its specified frequency. The -3dB corner fre-
to 260 Hz. At exactly 50, 60, 100, and 120 Hz quency of the filter when operating from a
the filter provides over 120 dB of rejection. Ta- 32.768 kHz clock is 17 Hz. Figure 7 illustrates
ble 3 indicates the filter attenuation for each of that the phase characteristics of the filter are pre-
the potential line interference frequencies when cisely linear phase.
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation

14 DS126F1
 CS5504

If the CS5504 is operated at a clock rate other crystal with tight specifications for both initial
than 32.768 kHz, the filter characteristics, in- frequency and for drift over temperature. To
cluding the comb filter zeros, will scale with the maintain excellent frequency stability, these
operating clock frequency. Therefore, optimum crystals are specified only over limited operating
rejection of line frequency interference will oc- temperature ranges (i.e. -10 °C to +60 °C) by the
cur with the CS5504 running at 32.768 kHz. manufacturers. Applications of these crystals
with the CS5504 does not require tight initial
Anti-Alias Considerations for Spectral tolerance or low tempco drift. Therefore, a lower
Measurement Applications cost crystal with looser initial tolerance and tem-
pco will generally be adequate for use with the
Input frequencies greater than one half the out- CS5504. Also check with the manufacturer
put word rate (CONV = 1) may be aliased by about wide temperature range application of
the converter. To prevent this, input signals their standard crystals. Generally, even those
should be limited in frequency to no greater than crystals specified for limited temperature range
one half the output word rate of the converter will operate over much larger ranges if fre-
(when quency stability over temperature is not a
CONV =1). Frequencies close to the modulator requirement. The frequency stability can be as
sample rate (XIN/2) and multiples thereof may bad as ±3000 ppm over the operating tempera-
also be aliased. If the signal source includes ture range and still be typically better than the
spectral components above one half the output line frequency (50 Hz or 60 Hz) stability over
word rate (when CONV = 1) these components cycle-to-cycle during the course of a day.
should be removed by means of low-pass filter-
ing prior to the A/D input to prevent aliasing. Serial Interface Logic
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+ The digital filter in the CS5504 takes 1624 clock
and VREF-) may also be aliased. Filtering of the cycles to compute an output word once a con-
reference voltage to remove these spectral com- version begins. At the end of the conversion
ponents from the reference voltage is desirable. cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
Crystal Oscillator DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
The CS5504 is designed to be operated using a port is either empty or unselected (CS = 1). If
32.768 kHz "tuning fork" type crystal. One end the port is empty or unselected, the digital filter
of the crystal should be connected to the XIN will update the port with a new output word.
input. The other end should be attached to When new data is put into the port DRDY will
XOUT. Short lead lengths should be used to go low.
minimize stray capacitance.
Reading Serial Data
Over the industrial temperature range (-40 to
+85 °C) the on-chip gate oscillator will oscillate SDATA is the output pin for the serial data.
with other crystals in the range of 30 kHz to 53 When CS goes low after new data becomes
kHz. The chip will operate with external clock available (DRDY goes low), the SDATA pin
frequencies from 30 kHz to 330 kHz over the in- comes out of Hi-Z with the MSB data bit pre-
dustrial temperature range. The 32.768 kHz sent. SCLK is the input pin for the serial clock.
crystal is normally specified as a time-keeping If the MSB data bit is on the SDATA pin, the

DS126F1 15
 CS5504

first rising edge of SCLK enables the shifting The following power supply options are possi-
mechanism. This allows the falling edges of ble:
SCLK to shift subsequent data bits out of the
port. Note that if the MSB data bit is output and VA+ = +5V to +10V, VA- = 0V, VD+ = +5V
the SCLK signal is high, the first falling edge of VA+ = +5V, VA- = -5V, VD+ = +5V
VA+ = +5V, VA- = 0V to -5V, VD+ = +3.3V
SCLK will be ignored because the shifting
mechanism has not become activated. After the
The CS5504 cannot be operated with a 3.3V
first rising edge of SCLK, each subsequent fall-
digital supply if VA+ is greater than +5.5V.
ing edge will shift out the serial data. Once the
LSB is present, the falling edge of SCLK will
Figure 8 illustrates the System Connection Dia-
cause the SDATA output to go to Hi-Z and
gram for the CS5504 using a single +5V supply.
DRDY to return high. The serial port register
Note that all supply pins are bypassed with
will be updated with a new data word upon the
completion of another conversion if the serial 0.1 µF capacitors and that the VD+ digital sup-
port has been emptied, or if the CS is inactive ply is derived from the VA+ supply.
(high).
Figure 9 illustrates the CS5504 using dual sup-
CS can be operated asynchronously to the plies of +5 and -5V.
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low Figure 10 illustrates the CS5504 using dual sup-
for at least two XIN clock cycles plus 200 ns plies of +10V analog and +5V digital.
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port. When using separate supplies for VA+ and
VD+, VA+ must be established first. VD+
Power Supplies and Grounding should never become more positive than VA+
under any operating condition. Remember to in-
The analog and digital supply pins to the vestigate transient power-up conditions, when
CS5504 are brought out on separate pins to one power supply may have a faster rise time.
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
analog ground pin. No analog ground pin is re-
quired because the inputs for measurement and
for the voltage reference are differential and re-
quire no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5504 requires that the supply voltage on
the VA+ pin always be more positive than the
voltage on any other pin of the device. If this
requirement is not met, the device can latch-up
or be damaged. In all circumstances the VA+
voltage must remain more positive than the VD+
or DGND pins; VD+ must remain more positive
than the DGND pin.

16 DS126F1
 CS5504

10Ω

+5V
0.1 µF 0.1 µF
Analog
Supply 14 17
VA+ VD+

Calibration 4
CAL
Control Optional
5
XIN Clock
Source
Bipolar/ 6
7 XOUT
Unipolar BP/UP 32.768 kHz
Input Select
CS5504
18
8 SCLK
AIN1+ Serial
Analog* 10 Data
AIN1-
Signal 19 Interface
9 SDATA
Sources AIN2+
11
AIN2- 20
DRDY
*Unused analog inputs should
be tied to signal ground 2
CS
Control
12 1 Logic
+ VREF+ A0
Voltage
Reference 13 3
- VREF- CONV

16
DGND
VA- Unused Logic
15 inputs must be
connected to
VD+ or DGND

Figure 8. CS5504 System Connection Diagram Using Single Supply

DS126F1 17
 CS5504

10Ω

+5V
0.1 µF 0.1 µF
Analog
Supply 14 17
VA+ VD+

Calibration 4
CAL
Control Optional
5
XIN Clock
Source
Bipolar/ 6
7 XOUT
Unipolar BP/UP 32.768 kHz
Input Select
CS5504
18
8 SCLK
AIN1+ Serial
Analog* 10 Data
AIN1-
Signal 19 Interface
9 SDATA
Sources AIN2+
11
AIN2- 20
DRDY
*Unused analog inputs should
be tied to signal ground 2
CS
Control
12 1 Logic
+ VREF+ A0
Voltage
Reference 13 3
- VREF- CONV

16
DGND
0.1 µF VA- Unused Logic
-5V
Analog 15 inputs must be
Supply connected to
VD+ or DGND

Figure 9. CS5504 System Connection Diagram Using Dual Supplies

18 DS126F1
 CS5504

Note: VD+ should never be more positive than VA+

+10V +5V
0.1 µF 0.1 µF
Analog Digital
Supply 14 17 Supply
VA+ VD+

Calibration 4
CAL
Control Optional
5
XIN Clock
Source
Bipolar/ 6
7 XOUT
Unipolar BP/UP 32.768 kHz
Input Select
CS5504
18
8 SCLK
AIN1+ Serial
Analog* 10 Data
AIN1-
Signal 19 Interface
9 SDATA
Sources AIN2+
11
AIN2- 20
DRDY
*Unused analog inputs should
be tied to signal ground 2
CS
Control
12 1 Logic
+ VREF+ A0
Voltage
Reference 13 3
- VREF- CONV

16
DGND
VA- Unused Logic
15 inputs must be
connected to
VD+ or DGND

Figure 10. CS5504 System Connection Diagram Using Dual Supply,

+10V Analog, +5V Digital

Schematic & Layout Review Service

Confirm Optimum
Schematic & Layout
Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

DS126F1 19
 CS5504

PIN DESCRIPTIONS*

MULTIPLEXER SELECTION INPUT A0 1 20 DRDY DATA READY

CHIP SELECT CS 2 19 SDATA SERIAL DATA OUTPUT
CONVERT CONV 3 18 SCLK SERIAL CLOCK INPUT
CALIBRATE CAL 4 17 VD+ POSITIVE DIGITAL POWER
CRYSTAL IN XIN 5 16 DGND DIGITAL GROUND
CRYSTAL OUT XOUT 6 15 VA- NEGATIVE ANALOG POWER
BIPOLAR/UNIPOLAR BP/UP 7 14 VA+ POSITIVE ANALOG POWER
DIFFERENTIAL ANALOG INPUT AIN1+ 8 13 VREF- VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN2+ 9 12 VREF+ VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT AIN1- 10 11 AIN2- DIFFERENTIAL ANALOG INPUT

*Pinout applies to both PDIP and SOIC

Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 2.
This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 20.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 19.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 18.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.
20 DS126F1
 CS5504

Control Input Pins

CAL - Calibrate, Pin 4.
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.

CONV - Convert, Pin 3.

The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If
CONV is held high (CAL low) the converter will do continuous conversions.

BP/UP - Bipolar/Unipolar, Pin 7.

The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.

A0 - Multiplexer Selection Input, Pin 1.

Selects the input channel for conversion. A0=0=AIN1. A0 is latched when CONV transitions
from low to high. This input has a pull-down resistor internal to the chip.

Measurement and Reference Inputs

AIN1+, AIN2+, AIN1-, AIN2- - Differential Analog Inputs, Pins 8, 9, 10, 11.
Analog differential inputs to the delta-sigma modulator.

VREF+, VREF- - Differential Voltage Reference Inputs, Pins 12, 13.

A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.

Power Supply Connections

VA+ - Positive Analog Power, Pin 14.
Positive analog supply voltage. Nominally +5 volts.

VA- - Negative Analog Power, Pin 15.

Negative analog supply voltage. Nominally -5volts.

VD+ - Positive Digital Power, Pin 17.

Positive digital supply voltage. Nominally +5 volts or +3.3 volts.

DGND - Digital Ground, Pin 16.

Digital Ground.

DS126F1 21
 CS5504

SPECIFICATION DEFINITIONS

Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.

Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.

Full Scale Error

The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB].
Units are in LSBs.

Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.

Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs

22 DS126F1
 CS5504

APPENDIX

The following companies provide 32.768 kHz crystals in many package varieties and temperature
ranges.

Fox Electronics Taiwan X’tal Corp.

5570 Enterprise Parkway 5F. No. 16, Sec 2, Chung Yang S. RD.
Fort Meyers, FL 33905 Reitou, Taipei, Taiwan R. O. C.
(813) 693-0099 Tel: 02-894-1202
Fax: 02-895-6207
Micro Crystal Division / SMH
702 West Algonquin Road Interquip Limited
Arlington Heights, IL 60005 24/F Million Fortune Industrial Centre
(708) 806-1485 34-36 Chai Wan Kok Street, Tsuen Wan N T
Tel: 4135515
SaRonix Fax: 4137053
4010 Transport Street
Palo Alto, California 94303 S& T Enterprises, Ltd.
(415) 856-6900 Rm 404 Blk B
Sea View Estate
Statek North Point, Hong Kong
512 North Main Tel: 5784921
Orange, California 92668 Fax: 8073126
(714) 639-7810
Mr. Darren Mcleod
IQD Ltd. Hy-Q International Pty. Ltd.
North Street 12 Rosella Road,
Crewkerne FRANKSON, 3199
Somerset TA18 7AK Victoria, Australia
England Tel: 61-3-783 9611
01460 77155 Fax: 61-3-783 9703

Mr. Pierre Hersberger

Microcrystal/DIV. ETA S.A.
Schild-Rust-Strasse 17
Grenchen CH-2540
Switzerland
065 53 05 57

DS126F1 23
• Notes •
 CDB5504

Evaluation Board for CS5504 A/D Converter

Features Description
l Operation with on-board 32.768 kHz crystal The CDB5504 is a circuit board designed to provide
or off-board clock source quick evaluation of the CS5504 A/D converter.
l DIP Switch Selectable:BP/UP mode; The board provides buffered digital signals, an on-board
Channel selection precision voltage reference, options for using an external
l On-board precision voltage reference clock, and a momentary switch to initiate calibration.

l Access to all digital control pins ORDERING INFORMATION

CDB5504 Evaluation Board
I

AIN2-

CS5504 B
AIN2+ H
U
E
F
A
AIN1- F
D
E
E
R
R
AIN1+ S

CLKIN
VREF

+5V GND -5V

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 1998 MAR ‘95
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
DS126DB1
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 25
 CDB5504

Introduction

The CDB5504 evaluation board provides a quick and U3 are used to buffer the converter for inter-
means of testing the CS5504 A/D converter. The face to off-board circuits. The buffers are used
CS5504 converter require a minimal amount of on the evaluation board only because the exact
external circuitry. The evaluation board comes loading and off-board circuitry is unknown.
configured with the A/D converter chip operat- Most applications will not require the buffer ICs
ing from a 32.768 kHz crystal and with an for proper operation.
off-chip precision 2.5 volt reference. The board
provides access to all of the digital interface pins To put the board in operation, select either bipo-
of the CS5504 chip. lar or unipolar mode with DIP switch S2. Then
press the CAL pushbutton after the board is
The board is configured for operation from +5 powered up. This initiates calibration of the con-
and -5 volt power supplies, but can be operated verter which is required before measurements
from a single +5 volt supply if the -5V binding can be taken.
post is shorted to the GND binding post.
To select an input, one of two channels, use DIP
switch S2 to select the input for A0 (see Ta-
Evaluation Board Overview ble 1). Once A0 is selected, the CONV switch
(S2-3) must be switched on (closed) and then
The board provides a complete means of making open to cause the CONV signal to transition low
the CS5504 A/D converter chip function. The to high. This latches the A0 channel selection
user must provide a means of taking the output into the converter. With CONV high (S2-3 open)
data from the board in serial format and using it the converter will convert continuously.
in his system.
Figure 3 illustrates the CAB5504 adapter board.
Figure 1 illustrates the schematic for the board. The CAB5504 translates a CS5505 pinout to a
The board comes configured for the A/D con- CS5504 pinout.
verter chip to operate from the 32.768 kHz
watch crystal. A BNC connector for an external Figures 4 and 5 illustrate the evaluation board
clock is provided on the board. To connect the layout while Figure 6 illustrates the component
external BNC source to the converter chip, a cir- placement (silkscreen) of the evaluation board.
cuit trace must be cut. Then a jumper must be
inserted in the proper holes to connect the XIN
pin of the converter to the input line from the
BNC. The BNC input is terminated with a 50Ω
resistor. Remove this resistor if driving from a
logic gate. See the schematic in Figure 1.

The board comes with the A/D converter A0 Channel Addressed

VREF+ and VREF- pins hard-wired to the 0 AIN1
2.5 volt bandgap voltage reference IC on the 1 AIN2
board.
Table 1. Multiplexer Truth Table
All of the control pins of the CS5504 are avail-
able at the J1 header connector. Buffer ICs U2
26 DS126DB1
DS126DB1

R22 +5
+5
+ C16
10 +5
10 µF
CAL DRDY
VD+
R9
+5 SCLK
C7 10 C10
0.1 µF C11 R11 SDATA
+5V +5 0.1 µF 0.01 µF 100k
C2 C5 14 17 J2
D1 + AGND R10 20k
VA+ VD+
6.8V 10 µF 0.1 µF CAL
GND DGND 4
CAL
C17 VD+ R17
+ C3 C4
TP10
R27 VD+ CONV
D2
10 µF 0.1 µF 1A 1K 3 0.1 µF 1 3 47k
6.8V 12 CONV U2A
VREF+ 2
-5V -5 R26 C19 CS
10nF TP9
1B 1K 13 2 4 5
VREF- CS U2B
C20 VD+ R18
10nF A0
2 6 2A TP8 R19
+5 LT1019 1 6 7 100k 47k
R8 C8 A0 U2C
C9 -2.5 V 5 0.1 µF VD+
25k 2B A1
0.1 µF 4 U1
TP7 R20
10 9 100k
CS5504 U2D
3A
+ DRDY
External TP11
20 11 12
VREF _ 3B DRDY U2E
R23 SDATA
TP12 100k
TP3 19 14 15
402 11 SDATA U2F
AIN2- AIN2-
R7 TP13 R24 8 SCLKO
R28 100k
100k TP4 18 5 U3B 6
402 SCLK
AIN2+ 9 AIN2+ VD+ 0.1 µF
R6 R25 4
R29 100k VD+ SCLKI
TP5 14
100k 2 C18
402 10 U3A R1
AIN1- AIN1- R16 100k 3
R5 TP14 BP/UP
R30 1 100k
TP6 7 11 12
100k 402 BP/UP U3D
8 AIN1+
AIN1+ 13 J1
R4
R31 U2 74HC4050
100k TP15 R21 7 VD+
C12 C13 C14 C15 U3 74HC125
U3C
47k 8 9 S2
0.01 µF 0.01 µF 0.01 µF 0.01 µF

CDB5504
10 A1

VA- XIN XOUT DGND A0

R3
15 5 6 16 CONV
50
-5 Y1 BP/UP
CLKIN C1
R2 32.768
0.1 µF kHz
200
Note: Buffers not required for general applications.
Figure 1. ADC Connections
27
 CDB5504

A0 1 20 DRDY
CS 2 19 SDATA
CONV 3 18 SCLK
CAL 4 17 VD+
XIN 5 16 DGND
XOUT 6 15 VA-
BP/UP 7 14 VA+
AIN1+ 8 13 VREF-
AIN2+ 9 12 VREF+
AIN1- 10 11 AIN2-

Figure 2. CS5504 Pin Layout

1 1 20 14

10 11

12 13

Figure 3. CAB5504 Adapter Board

28 DS126DB1
 CDB5504

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

DS126DB1 29
 CDB5504

Figure 5. Bottom Trace Layer (NOT TO SCALE)

30 DS126DB1
 CDB5504

AIN2-
AIN1+

AIN2+
AIN-

AIN1-
CDB5504

Figure 6. Silk Screen Layer (NOT TO SCALE)

DS126DB1 31