NXP Semiconductors Document Number: IMX8MNCEC

Rev. 1, 03/2021
Data Sheet: Technical Data
MIMX8MN6DVTJZAA MIMX8MN6DVTJZCA
MIMX8MN6DVTJZDA MIMX8MN5DVTJZAA
MIMX8MN4DVTJZAA MIMX8MN3DVTJZAA
MIMX8MN2DVTJZAA MIMX8MN1DVTJZAA
MIMX8MN5DVPIZCA MIMX8MN5DVPIZDA
MIMX8MN5DVPIZAA MIMX8MN3DVPIZAA
MIMX8MN1DVPIZAA

i.MX 8M Nano
Applications Processor
Datasheet for Consumer
Package Information
Products Plastic Package
FCBGA 14 x 14 mm, 0.5 mm pitch
FCBGA 11 x 11 mm, 0.5 mm pitch

Ordering Information

See Table 3 on page 6

1 i.MX 8M Nano introduction

The i.MX 8M Nano application processor represents 1. i.MX 8M Nano introduction . . . . . . . . . . . . . . . . . . . . . . . 1
NXP’s latest graphics and audio experience combining 1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
state-of-the-art media-specific features with 2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
high-performance processing while optimized for lowest 2.1. Recommended connections for unused input/output
13
power consumption. 3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 15
The i.MX 8M Nano family of processors features 3.2. Power supplies requirements and restrictions . . . 28
advanced implementation of a quad Arm® Cor- 3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 34
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35
tex®-A53 core, which operates at speeds of up to 3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 37
1.5 GHz. A general purpose Cortex®-M7 running up to 3.7. Output buffer impedance parameters . . . . . . . . . 38
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 40
750 MHz core processor is for real-time and low-power 3.9. External peripheral interface parameters . . . . . . 41
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 75
processing. 4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 75
The i.MX 8M Nano family of processors provides addi- 4.2. Boot device interface allocation . . . . . . . . . . . . . . 75
5. Package information and contact assignments . . . . . . . 77
tional computing resources and peripherals: 5.1. 14 x 14 mm package information . . . . . . . . . . . . 77
• Advanced security modules for secure boot, 5.2. 11 x 11 mm package information . . . . . . . . . . . . 93
cipher acceleration and DRM support 5.3. DDR pin function list . . . . . . . . . . . . . . . . . . . . . 108
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
• A wide range of audio interfaces, including I2S,
AC 97, TDM, and S/PDIF
• Large set of peripherals that are commonly used
in consumer/industrial market, including USB
and Ethernet

NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.

© 2019-2021 NXP Semiconductors All rights reserved.

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

Table 1. Features

Subsystem Feature

Cortex®-A53 MPCore platform Quad symmetric Cortex® -A53 processors

• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with Arm® NEONTM technology supporting the
Advanced Single Instruction Multiple Data architecture:
• Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture

Support of 64-bit Arm®v8-A architecture

512 KB unified L2 cache

Cortex®-M7 core platform Low power microcontroller available for customer application:
• low power standby mode
• IoT features including Weave
• Manage IR or wireless remote
• ML inference applications (enhanced for i.MX 8M Nano)
Cortex® M7 CPU:
• 256 KB tightly coupled memory (TCM)

Connectivity One USB 2.0 OTG controllers with integrated PHY interfaces:
• Spread spectrum clock support

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)

One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),
Ethernet AVB, and IEEE 1588

Four Universal Asynchronous Receiver/Transmitter (UART) modules

Four I2C modules

Three SPI modules

On-chip memory Boot ROM (256 KB)

On-chip RAM (512 KB + 32 KB)

GPIO and pin multiplexing General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

Power management Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient
power management

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
2 NXP Semiconductors

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

Table 1. Features (continued)

Subsystem Feature

External memory interface 16-bit DRAM interfaces:

• LPDDR4-3200
• DDR4-2400
• DDR3L-1600

8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)

eMMC 5.1 Flash (3 interfaces)

SPI NOR Flash (3 interfaces)

QuadSPI Flash with support for XIP (for Cortex®-M7 in low-power mode) and parallel
read mode of two identical FLASH devices

Multimedia Graphic Processing Unit:

• GC7000UL with OpenCL and Vulkan support
• 2 shader
• 99.8 million triangles/sec
• 0.6 giga pixel/sec
• 9.6 GFLOPs 32-bit/19.2 GFLOPs 16-bit
• Supports OpenGL ES 1.1, 2.0, 3.0, OpenCL
• Core clock frequency of 600 MHz
• Shader clock frequency of 600 MHz

LCDIF Display Controller:

• Support up to 1080p60 display through MIPI DSI

MIPI Interfaces:
• 4-lane MIPI DSI interface
• 4-lane MIPI CSI interface

Audio:
• S/PDIF input and output, including a raw capture input mode
• Five external synchronous audio interface (SAI) modules supporting I2S, AC97,
TDM, codec/DSP, and DSD interfaces, comprising one SAI with 4 Tx and 4 Rx
lanes, two SAI with 2 Tx and 2 Rx lanes, and two SAI with 1 Tx and 1Rx lane. All
ports support 49.152 MHz BCLK.
• ASRC supports processing 32 audio channels, 4 context groups, 8 kHz to 384 kHz
sample rate and 1/16 to 8x sample rate conversion ratio.
• Pulse Density Modulation (PDM) input

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 3

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

Table 1. Features (continued)

Subsystem Feature

Security Resource Domain Controller (RDC):

• supports 4 domains and up to 8 regions of DDR

Arm® TrustZone® (TZ) architecture:

• Arm® Cortex-A53 MPCore TrustZone support

On-chip RAM (OCRAM) secure region protection using OCRAM controller

High Assurance Boot (HAB)

Cryptographic acceleration and assurance module (CAAM):

• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• Side channel attack resistance
• True random number generation (RNG)
• Manufacturing protection support

Secure non-volatile storage (SNVS):

• Secure real-time clock (RTC)

Secure JTAG controller (SJC)

System debug Arm® CoreSightTM debug and trace technology

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for Quad Cortex®-A53 and Cortex®-M7 CPUs

Cross Triggering Interface (CTI)

Support for 4-pin (JTAG) debug interface

NOTE
The actual feature set depends on the part numbers as described in Table 3.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
4 NXP Semiconductors

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

1.1 Block diagram

Figure 1 shows the functional modules in the i.MX 8M Nano applications processor system.

Security Main CPU Platform Connectivity

TrustZone 1 GB Ethernet
Quad Cortex®-A53 (IEEE1588, EEE, and AVB)
DRM Ciphers
32 KB I-cache 32 KB D-cache S/PDIF Rx and Tx
Secure Clock
NEON FPU
5x I2S/SAI
eFuse Key Storage
512 KB L2 Cache
Random Number 1x USB 2.0 OTG and PHY

Low Power, Security CPU

32 KB Secure RAM PDM
Cortex®-M7
4x UART
System Control 256 KB TCM
4x I2C
3x Smart DMA

XTAL Multimedia 3x SPI

PLLs
3D Graphics: GC7000UL
External Memory
3x Watchdog
LPDDR4/DDR4/DDR3L
4x PWM 4-lane MIPI-DSI Interface

6x Timer eMMC 5.1/SD 3.0

4-lane MIPI-CSI Interface

Secure JTAG
NAND CTL (BCH62)
Temperature Sensor
ASRC
512 KB OCRAM Dual-ch QuadSPI

Figure 1. i.MX 8M Nano system block diagram

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 5

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

NOTE
Some modules shown in this block diagram are not offered on all
derivatives. See Table 2 for exceptions.
Table 2. Modules supported

Key Modules 6DVT 5DVT 4DVT 3DVT 2DVT 1DVT 5DVP 3DVP 1DVP

Cortex® A53 4x 4x 2x 2x 1x 1x 4x 2x 1x

Cortex® M7 1x 1x 1x 1x 1x 1x 1x 1x 1x

GPU 1x N/A 1x N/A 1x N/A N/A N/A N/A

MIPI DSI 1x 1x 1x 1x 1x 1x N/A N/A N/A

1.2 Ordering information

Table 3 shows examples of orderable sample part numbers covered by this data sheet. This table does not
include all possible orderable part numbers. If your desired part number is not listed in the table, or you
have questions about available parts, contact your NXP representative.

Table 3. Orderable part numbers

Cortex-A53
Qualification Temperature
Part number Sub-Family Options CPU speed Package
tier Tj (C)
grade

MIMX8MN6DVTJZAA i.MX 8M Nano 4x A53, M7, GPU, MIPI 1.5 GHz Consumer 0 to 95 14 x 14 mm,
Quad DSI 0.5 mm
pitch

MIMX8MN6DVTJZCA i.MX 8M Nano 4x A53, M7, GPU, 1.5 GHz Consumer 0 to 95 14 x 14 mm,
Quad Immersiv3D with Dolby 0.5 mm
ATMOS support1, MIPI pitch
DSI

MIMX8MN6DVTJZDA i.MX 8M Nano 4x A53, M7, GPU, 1.5 GHz Consumer 0 to 95 14 x 14 mm,
Quad Immersiv3D with Dolby 0.5 mm
ATMOS and DTS pitch
support1, MIPI DSI
MIMX8MN5DVTJZAA i.MX 8M Nano 4x A53, M7, No GPU, 1.5 GHz Consumer 0 to 95 14 x 14 mm,
QuadLite MIPI DSI 0.5 mm
pitch

MIMX8MN4DVTJZAA i.MX 8M Nano 2x A53, M7, GPU, MIPI 1.5 GHz Consumer 0 to 95 14 x 14 mm,
Dual DSI 0.5 mm
pitch

MIMX8MN3DVTJZAA i.MX 8M Nano 2x A53, M7, No GPU, 1.5 GHz Consumer 0 to 95 14 x 14 mm,
DualLite MIPI DSI 0.5 mm
pitch

MIMX8MN2DVTJZAA i.MX 8M Nano 1x A53, M7, GPU, MIPI 1.5 GHz Consumer 0 to 95 14 x 14 mm,
Solo DSI 0.5 mm
pitch

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
6 NXP Semiconductors

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

Table 3. Orderable part numbers (continued)

MIMX8MN1DVTJZAA i.MX 8M Nano 1x A53, M7, No GPU, 1.5 GHz Consumer 0 to 95 14 x 14 mm,
SoloLite MIPI DSI 0.5 mm
pitch

MIMX8MN5DVPIZCA i.MX 8M Nano 4x A53, M7, 1.4 GHz Consumer 0 to 95 11 x 11 mm,

UltraLite Immersiv3D with Dolby 0.5 mm
Quad ATMOS support1, No pitch
GPU, No MIPI DSI

MIMX8MN5DVPIZDA i.MX 8M Nano 4x A53, M7, 1.4 GHz Consumer 0 to 95 11 x 11 mm,

UltraLite Immersiv3D with Dolby 0.5 mm
Quad ATMOS and DTS pitch
support1, No GPU, No
MIPI DSI

MIMX8MN5DVPIZAA i.MX 8M Nano 4x A53, M7, No GPU, 1.4 GHz Consumer 0 to 95 11 x 11 mm,
UltraLite No MIPI DSI 0.5 mm
Quad pitch
MIMX8MN3DVPIZAA i.MX 8M Nano 2x A53, M7, No GPU, 1.4 GHz Consumer 0 to 95 11 x 11 mm,
UltraLite Dual No MIPI DSI 0.5 mm
pitch

MIMX8MN1DVPIZAA i.MX 8M Nano 1x A53, M7, No GPU, 1.4 GHz Consumer 0 to 95 11 x 11 mm,
UltraLite Solo No MIPI DSI 0.5 mm
pitch
1 Supply of this Implementation of Dolby technology does not convey a license nor imply a right under any patent, or any other
industrial or intellectual property right of Dolby Laboratories, to use this Implementation in any finished end-user or
ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

Figure 2 describes the part number nomenclature so that the users can identify the characteristics of the
specific part number.
Contact an NXP representative for additional details.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 7

Downloaded from Arrow.com.

 i.MX 8M Nano introduction

MIMX8MN@+##$$%A
Silicon revision
Fusing options
Core frequency – Arm A53
Package type – all ROHS
Data Sheet Temperature
Part differentiator
Qualification level
Part number series

Part differentiator @
Qualification level
i.MX 8M Nano Quad 6
Samples P GPU, 4x A53 Temperature Tj + A53 core frequency $$
Mass Production M i.MX 8M Nano QuadLite 5
Consumer: 0 to +95oC D 1.5 GHz JZ
*i.MX 8M Nano UltraLite Quad
No GPU, 4x A53 Industrial: -40 to 105oC C 1.4 GHz IZ
i.MX 8M Nano Dual 4
Part number series Description GPU, 2x A53 Package Type ROH Fusing %
S
IMX8MN i.MX 8M Nano i.MX 8M Nano DualLite 3
*i.MX 8M Nano UltraLite Dual FCBGA486 VT Default A
No GPU, 2x A53 14 x14mm, 0.5mm pitch
Immersiv3D w/ Dolby Atmos C
i.MX 8M Nano Solo 2 FCBGA306 VP
Immersiv3D w/ Dolby Atmos & DTS D
GPU, 1x A53 11x11mm, 0.5mm pitch
i.MX 8M Nano SoloLite 1
Silicon Rev A
*i.MX 8M Nano UltraLite Solo
No GPU, 1x A53 Rev A0 A

*i.MX 8M Nano UltraLite Quad/Dual/Solo (11x11 package) has no MIPI DSI

Figure 2. Part number nomenclature—i.MX 8M Nano family of processors

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
8 NXP Semiconductors

Downloaded from Arrow.com.

 Modules list

2 Modules list
The i.MX 8M Nano family of processors contains a variety of digital and analog modules. Table 4
describes these modules in alphabetical order.
Table 4. i.MX 8M Nano modules list

Block mnemonic Block name Brief description

APBH-DMA NAND Flash and BCH ECC DMA controller used for GPMI2 operation.
DMA Controller

Arm Arm Platform The Arm Core Platform includes a quad Cortex-A53 core and a
Cortex-M7 core. The Cortex-A53 core includes associated
sub-blocks, such as the Level 2 Cache Controller, Snoop Control
Unit (SCU), General Interrupt Controller (GIC), private timers,
watchdog, and CoreSight debug modules. The Cortex-M7 core is
used as a customer microcontroller.

BCH Binary-BCH ECC Processor The BCH module provides up to 62-bit ECC encryption/decryption
for NAND Flash controller (GPMI)

CAAM Cryptographic accelerator and CAAM is a cryptographic accelerator and assurance module. CAAM
assurance module implements several encryption and hashing functions, a run-time
integrity checker, entropy source generator, and a Pseudo Random
Number Generator (PRNG). The PRNG is certifiable by the
Cryptographic Algorithm Validation Program (CAVP) of the National
Institute of Standards and Technology (NIST).
CAAM also implements a Secure Memory mechanism. In i.MX 8M
Nano processors, the secure memory provided is 32 KB.

CCM Clock Control Module, General These modules are responsible for clock and reset distribution in the
GPC Power Controller, System Reset system, and also for the system power management.
SRC Controller

CSU Central Security Unit The Central Security Unit (CSU) is responsible for setting
comprehensive security policy within the i.MX 8M Nano platform.

CTI-0 Cross Trigger Interface Cross Trigger Interface (CTI) allows cross-triggering based on inputs
CTI-1 from masters attached to CTIs. The CTI module is internal to the
CTI-2 Cortex-A53 core platform.
CTI-3
CTI-4
DAP Debug Access Port The DAP provides real-time access for the debugger without halting
the core to access:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan chains.

DDRC Double Data Rate Controller The DDR Controller has the following features:
• Supports 16-bit LPDDR4-3200, DDR4-2400, and DDR3L-1600
• Supports up to 8 Gbyte DDR memory space

eCSPI1 Configurable SPI Full-duplex enhanced Synchronous Serial Interface, with data rate
eCSPI2 up to 52 Mbit/s. Configurable to support Master/Slave modes, four
eCSPI3 chip selects to support multiple peripherals.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 9

Downloaded from Arrow.com.

 Modules list

Table 4. i.MX 8M Nano modules list (continued)

Block mnemonic Block name Brief description

ENET1 Ethernet Controller The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to
complete the interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the ENET chapter
of the i.MX 8M Nano Applications Processor Reference Manual
(IMX8MNRM) for details.

FlexSPI FlexSPI The FlexSPI module acts as an interface to external serial flash
devices. This module contains the following features:
• Flexible sequence engine to support various flash vendor devices
• Single pad/Dual pad/Quad pad mode of operation
• Single Data Rate/Double Data Rate mode of operation
• Parallel Flash mode
• DMA support
• Memory mapped read access to connected flash devices
• Multi master access with priority and flexible and configurable
buffer for each master

GIC Generic Interrupt Controller The GIC handles all interrupts from the various subsystems and is
ready for virtualization.

GPC General Power Control Module The GPC independently control reset and gated clock to each
switched power domain when powering on/off the domain.

GPIO1 General Purpose I/O Modules Used for general purpose input/output to external ICs. Each GPIO
GPIO2 module supports up to 32 bits of I/O.
GPIO3
GPIO4
GPIO5

GPMI General Purpose Memory The GPMI module supports up to 8x NAND devices and 62-bit ECC
Interface encryption/decryption for NAND Flash Controller (GPMI2). GPMI
supports separate DMA channels for each NAND device.

GPT1 General Purpose Timer Each GPT is a 32-bit “free-running” or “set-and-forget” mode timer
GPT2 with programmable prescaler and compare and capture register. A
GPT3 timer counter value can be captured using an external event and can
GPT4 be configured to trigger a capture event on either the leading or
GPT5 trailing edges of an input pulse. When the timer is configured to
GPT6 operate in “set-and-forget” mode, it is capable of providing precise
interrupts at regular intervals with minimal processor intervention.
The counter has output compare logic to provide the status and
interrupt at comparison. This timer can be configured to run either on
an external clock or on an internal clock.

GPU3D Graphics Processing Unit-3D The GPU3D provides hardware acceleration for 3D graphics
algorithms with sufficient processor power to run desktop quality
interactive graphics applications on displays.

I2C1 I2C Interface I2C provides serial interface for external devices. Data rates of up to
I2C2 320 kbps are supported.
I2C3
I2C4

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
10 NXP Semiconductors

Downloaded from Arrow.com.

 Modules list

Table 4. i.MX 8M Nano modules list (continued)

Block mnemonic Block name Brief description

IOMUXC IOMUX Control This module enables flexible I/O multiplexing. Each IO pad has a
default as well as several alternate functions. The alternate functions
are software configurable.

LCDIF LCD interface The LCDIF is a general purpose display controller used to drive a
wide range of display devices varying in size and capability, the key
feature of the display controller includes:
• Support 8-bit/16-bit/24-bit/32-bit pixel depth
• Support DOTCLK mode for MIPI-DPI interface
• Support resolution up to 1920 x 1200p60

MIPI CSI (four-lane) MIPI Camera Serial Interface This module provides one four-lane MIPI camera serial interfaces,
which operates up to a maximum bit rate of 1.5 Gbps.

MIPI DSI (four-lane) MIPI Display Serial Interface This module provides a four-lane MIPI display serial interface
operating up to a maximum bit rate of 1.5 Gbps.

OCOTP_CTRL OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface
for reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically programmable poly fuses (eFUSEs). The OCOTP_CTRL
also provides a set of volatile software-accessible signals that can be
used for software control of hardware elements, not requiring non
volatility. The OCOTP_CTRL provides the primary user-visible
mechanism for interfacing with on-chip fuse elements. Among the
uses for the fuses are unique chip identifiers, mask revision
numbers, cryptographic keys, JTAG secure mode, boot
characteristics, and various control signals requiring permanent non
volatility.

OCRAM On-Chip Memory controller The On-Chip Memory controller (OCRAM) module is designed as an
interface between the system’s AXI bus and the internal (on-chip)
SRAM memory module.
In i.MX 8M Nano processors, the OCRAM is used for controlling the
512 KB multimedia RAM through a 64-bit AXI bus.

PDM Pulse Density Modulation The PDM supports up to 8-channels (4 lanes).

PWM1 Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is
PWM2 optimized to generate sound from stored sample audio images. It
PWM3 can also generate tones. It uses 16-bit resolution and a 4x16 data
PWM4 FIFO to generate sound.

SAI2 Synchronous Audio Interface The SAI module provides a synchronous audio interface (SAI) that
SAI3 supports full duplex serial interfaces with frame synchronization,
SAI5 such as I2S, AC97, TDM, and codec/DSP interfaces.
SAI6
SAI7

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 11

Downloaded from Arrow.com.

 Modules list

Table 4. i.MX 8M Nano modules list (continued)

Block mnemonic Block name Brief description

SDMA Smart Direct Memory Access The SDMA is a multichannel flexible DMA engine. It helps in
maximizing system performance by offloading the various cores in
dynamic data routing. It has the following features:
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Multi channel DMA supporting up to 32 time-division multiplexed
DMA channels
• 48 events with total flexibility to trigger any combination of
channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between Arm and SDMA
• Very fast Context-Switching with 2-level priority based preemptive
multi tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment,
decrement, and no address changes on source and destination
address)
• DMA ports can handle unidirectional and bidirectional flows (Copy
mode)
• Up to 8-word buffer for configurable burst transfers for EMIv2.5
• Support of byte-swapping and CRC calculations
• Library of Scripts and API is available

SJC Secure JTAG Controller The SJC provides JTAG interface (designed to be compatible with
JTAG TAP standards) to internal logic. The i.MX 8M Nano family of
processors uses JTAG port for system debugging.
The JTAG port must be accessible during platform initial laboratory
bring-up, for troubleshooting, as well as for software debugging by
authorized entities. The i.MX 8M Nano SJC incorporates three
security modes for protecting against unauthorized accesses.
Modes are selected through eFUSE configuration.

SNVS Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock,
Security State Machine, Master Key Control, and Violation/Tamper
Detection and reporting.

SPDIF1 Sony Philips Digital A standard audio file transfer format, developed jointly by the Sony
Interconnect Format and Phillips corporations. It supports Transmitter and Receiver
functionality.

TEMPSENSOR Temperature Sensor Temperature sensor

TZASC Trust-Zone Address Space The TZASC (TZC-380 by Arm) provides security address region
Controller control functions required for intended application. It is used on the
path to the DRAM controller.

UART1 UART Interface Each of the UARTv2 modules supports the following serial data
UART2 transmit/receive protocols and configurations:
UART3 • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even,
UART4 odd, or none)
• Programmable baud rates up to 4 Mbps. This is a higher max
baud rate relative to the 1.875 MHz, which is stated by the
TIA/EIA-232-F standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting
auto-baud

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
12 NXP Semiconductors

Downloaded from Arrow.com.

 Modules list

Table 4. i.MX 8M Nano modules list (continued)

Block mnemonic Block name Brief description

uSDHC1 SD/MMC and SDXC i.MX 8M Nano SoC characteristics:

uSDHC2 Enhanced Multi-Media Card / All the MMC/SD/SDIO controller IPs are based on the uSDHC IP.
uSDHC3 Secure Digital Host Controller They are designed to support:
• SD/SDIO standard, up to version 3.0.
• MMC standard, up to version 5.1.
• 1.8 V and 3.3 V operation, but do not support 1.2 V operation.
• 1-bit/4-bit SD and SDIO modes, 1-bit/4-bit/8-bit MMC mode.
One uSDHC controller (SD1) can support up to an 8-bit interface, the
other controller (SD2) can only support up to a 4-bit interface.

USB 2.0 1x USB 2.0 controller and PHY One USB controller and PHY that support USB 2.0.

WDOG1 Watchdog The watchdog (WDOG) timer supports two comparison points
WDOG2 during each counting period. Each of the comparison points is
WDOG3 configurable to evoke an interrupt to the Arm core, and a second
point evokes an external event on the WDOG line.

2.1 Recommended connections for unused input/output

If a function of the i.MX 8M Nano is not in use, the I/Os and power rails of that function can be terminated
to reduce overall board power.
Table 5 shows the recommended connections for 14 x 14 mm package unused power supply rails.
Table 5. Recommended connections for 14 x 14 mm package unused power supply rails

Recommendations
Function Ball Name
if Unused

MIP-CSI and VDD_MIPI_0P8, VDD_MIPI_1P2, VDD_MIPI_1P8 Leave unconnected

MIPI-DSI
USB1 VDD_USB_0P8, VDD_USB_1P8, VDD_USB_3P3 Leave unconnected

GPU VDD_GPU Leave unconnected

Digital I/O NVCC_CLK, NVCC_ECSPI, NVDD_ENET, NVCC_GPIO1, NVCC_I2C, All digital I/O
supplies NVCC_JTAG, NVCC_NAND, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, NVCC_SD1, supplies listed in this
NVCC_SD2, NVCC_UART, NVCC_SNVS_1P8, PVCC0_1P8, PVCC1_1P8, table must be
PVCC2_1P8 powered under
normal conditions
whether the
associated I/O pins
are in use or not, and
associated I/O pins
need to enable pull
in pad control
register to limit any
floating gate current.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 13

Downloaded from Arrow.com.

 Modules list

Table 6 shows the recommended connections for 11 x 11 mm package unused power supply rails.
Table 6. Recommended connections for 11 x 11 mm package unused power supply rails

Recommendations
Function Ball Name
if Unused

MIP-CSI VDD_MIPI_1P2 Leave unconnected

USB1 VDD_USB_0P8, VDD_USB_1P8, VDD_USB_3P3 Leave unconnected

Digital I/O NVCC_ENET_GPIO_SAI2, NVCC_CLK_JTAG_PVCC_1P8, NVCC_I2C_UART, All digital I/O

supplies NVCC_SAI3_SAI5, NVCC_SD1_NAND, NVCC_ECSPI, NVCC_SD2, supplies listed in this
NVCC_SNVS_1P8 table must be
powered under
normal conditions
whether the
associated I/O pins
are in use or not, and
associated I/O pins
need to enable pull
in pad control
register to limit any
floating gate current.

Table 7 shows recommended connections for 14 x 14 mm package unused signal contacts/interfaces.

Table 7. Recommended connections for 14 x 14 mm package unused signal contacts/interfaces

Recommendations
Function Ball Name
if Unused

MIPI-CSI MIPI_CSI_CLK_P, MIPI_CSI_CLK_N, MIPI_CSI_Dx_P, MIPI_CSI_Dx_N Tie all signals to

ground

MIPI-DSI MIPI_VREG_CAP, MIPI_DSI_CLK_P, MIPI_DSI_CLK_N, MIPI_DSI_Dx_P, Leave unconnected

MIPI_DSI_Dx_N

USB1 USB1_VBUS, USB1_DN, USB1_DP, USB1_ID, USB1_TXRTUNE Leave unconnected

Table 8 shows recommended connections for 11 x 11 mm package unused signal contacts/interfaces.

Table 8. Recommended connections for 11 x 11 mm package unused signal contacts/interfaces

Recommendations
Function Ball Name
if Unused

USB1 USB1_VBUS, USB1_DN, USB1_DP, USB1_ID, USB1_TXRTUNE Leave unconnected

MIPI-CSI MIPI_CSI_CLK_P, MIPI_CSI_CLK_N, MIPI_CSI_Dx_P, MIPI_CSI_Dx_N Tie all signals to

ground

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
14 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX 8M Nano family
of processors.

3.1 Chip-level conditions

This section provides the device-level electrical characteristics for the IC. See Table 9 for a quick reference
to the individual tables and sections.
Table 9. i.MX 8M Nano chip-level conditions

For these characteristics, … Topic appears …

Absolute maximum ratings on page 15

Thermal resistance on page 18

Operating ranges on page 19

External clock sources on page 22

Estimated power supply maximum currents on page 23

Power modes on page 24

Power supplies requirements and restrictions on page 28

3.1.1 Absolute maximum ratings

CAUTION
Stresses beyond those listed under Table 10 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the operating ranges or parameters tables is not implied.

Table 10. Absolute maximum ratings for 14 x 14 mm package

Parameter description Symbol Min Max Unit Notes

Core supply voltages VDD_ARM -0.3 1.15 V —

VDD_SOC

Power supply for GPU VDD_GPU -0.3 1.15 V —

DDR PHY supply voltage VDD_DRAM -0.3 1.15 V —

DDR I/O supply voltage NVCC_DRAM -0.3 1.575 V —

DRAM PLL supply voltage VDD_DRAM_PLL_0P8 -0.3 1.15 V —

VDD_DRAM_PLL_1P8 -0.3 2.15 V —

SNVS IO supply voltage NVCC_SNVS_1P8 -0.3 2.15 V —

VDD_SNVS supply voltage VDD_SNVS_0V8 -0.3 0.95 V —

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 15

Downloaded from Arrow.com.

 Electrical characteristics

Table 10. Absolute maximum ratings for 14 x 14 mm package (continued)

Parameter description Symbol Min Max Unit Notes

GPIO supply voltage NVCC_JTAG, -0.3 3.8 V —

NVCC_GPIO1,
NVCC_ENET,
NVCC_SD1,
NVCC_SD2,
NVCC_NAND,
NVCC_SAI2,
NVCC_SAI3,
NVCC_SAI5,
NVCC_ECSPI,
NVCC_I2C,
NVCC_UART,
NVCC_CLK

GPIO pre-driver supply voltage PVCC0_1P8, -0.3 2.15 V —

PVCC1_1P8,
PVCC2_1P8

Isolated core supply voltage VDD_ANA_0P8 -0.3 1.15 V —

Analog core supply voltage VDD_ANA0_1P8 -0.3 2.15 V —

VDD_ANA1_1P8 -0.3 2.15 V —

Arm PLL supply voltage VDD_ARM_PLL_0P8 -0.3 1.15 V —

VDD_ARM_PLL_1P8 -0.3 2.15 V —

VDD_MIPI_0P8 -0.3 1.15 V —

MIPI PHY supply voltage
VDD_MIPI_1P2 -0.3 1.45 V —

VDD_MIPI_1P8 -0.3 2.15 V —

VDD_USB_0P8 -0.3 1.15 V —

USB PHY supply voltage
VDD_USB_1P8 -0.3 2.15 V —

VDD_USB_3P3 -0.3 3.95 V —

USB_VBUS input detected USB1_VBUS -0.3 3.95 V —

XTAL supply voltage VDD_24M_XTAL_1P8 -0.3 2.15 V —
oC
Storage temperature range TSTORAGE -40 150 —

Table 11. Absolute maximum ratings for 11 x 11 mm package

Parameter description Symbol Min Max Unit Notes

Core and DDR PHY supply VDD_SOC -0.3 1.15 V —

voltage

DDR I/O supply voltage NVCC_DRAM -0.3 1.575 V —

DRAM PLL supply voltage VDD_DRAM_PLL_1P8 -0.3 2.15 V —

SNVS IO supply voltage NVCC_SNVS_1P8 -0.3 2.15 V —

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
16 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 11. Absolute maximum ratings for 11 x 11 mm package (continued)

Parameter description Symbol Min Max Unit Notes

VDD_SNVS supply voltage VDD_SNVS_0V8 -0.3 0.95 V —

GPIO supply voltage NVCC_ENET_GPIO_S -0.3 3.8 V —

AI2,
NVCC_I2C_UART,
NVCC_SAI3_SAI5,
NVCC_SD1_NAND,
NVCC_ECSPI,
NVCC_SD2

GPIO supply voltage NVCC_CLK_JTAG_PV -0.3 2.15 V —

CC_1P8

XTAL, Analog core, MIPI PHY VDD_ANA1_XTAL_MIP -0.3 2.15 V —

and USB PHY 1.8 V supply I_USB_1P8
voltage

Analog core and ARM PLL 1.8 V VDD_ANA0_ARM_PLL -0.3 2.15 V —

supply voltage _1P8

MIPI PHY 1.2 V supply voltage VDD_MIPI_1P2 -0.3 1.45 V —

USB PHY 3.3 V supply voltage VDD_USB_3P3 -0.3 3.95 V —

USB_VBUS input detected USB1_VBUS -0.3 3.95 V —

XTAL supply voltage VDD_24M_XTAL_1P8 -0.3 2.15 V —

oC
Storage temperature range TSTORAGE -40 150 —

Table 12. Electrostatic discharge and latch up ratings

Parameter description Rating Reference Comment

Electrostatic Discharge Human Body Model (HBM) ±1000 V JS-001-2017 —

(ESD)
Charged Device Model (CDM) ±250 V JS-002-2018 —

Latch UP (LU) Immunity level: Mandatory requirement:

• Class I@ 25 oC ambient A JESD78E JTAG_TMS pin must be
temperature A connected with a 50 ohm
• Class II @ 105 oC ambient series resistor near the
temperature component.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 17

Downloaded from Arrow.com.

 Electrical characteristics

3.1.2 Thermal resistance

3.1.2.1 14 x 14 mm FCBGA package thermal resistance

Table 13 displays the 14 x 14 mm FCBGA package thermal resistance data.
Table 13. 14 x 14 mm package thermal resistance data

Rating Test conditions Symbol Value Unit Notes

o 1, 2
Junction to Ambient Single layer board (1s) RJA 30 C/W
Natural Convection Four layer board (2s2p)
o 1, 2, 3
Junction to Ambient Four layer board (2s2p) RJA 22.9 C/W
Natural Convection Four layer board (2s2p)
o 1, 3
Junction to Ambient (@200 ft/min) Single layer board (1s) RJMA 24 C/W
oC/W 1, 3
Junction to Ambient (@200 ft/min) Four layer board (2s2p) RJMA 18.5
oC/W 4
Junction to Board — RJB 7.8
oC/W 5
Junction to Case — RJC 4

Junction to Package Top Natural Convection JT 0.2 oC/W 6

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JESD51-2 with the single layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal.
4
Thermal resistance between the die and printed circuit board per JEDEC JESD51-8. Board temperature is measured on the
top surface of the board near the package.
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6 Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.

3.1.2.2 11 x 11 mm FCBGA package thermal resistance

Table 14 displays the 11 x 11 mm FCBGA package thermal resistance data.
Table 14. 11 x 11 mm thermal resistance data1

Value
Rating Board type2 Symbol Unit
Coreless

Junction to Ambient Thermal Resistance3 JESD51-9, 2s2p RJA 27.7 oC/W

Junction-to-Top of Package Thermal JESD51-9, 2s2p JT 5.2 oC/W

Characterization Parameter3

Junction to Case Resistance4 JESD51-9, 1s RJC 11 oC/W

1
Non-uniform power is applied on the die.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
18 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

2
Thermal test board meets JEDEC specification for this package (JESD51-9). Test board has 40 vias under die shadow
mapped according to BGA layout under die. Each via is 0.2 mm in diameter and connects top layer with the first buried plane
layer.
3
Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not
meant to predict the performance of a package in an application-specific environment.
4
Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the surface
temperature at the package top side.

3.1.3 Operating ranges

Table 15 provides the operating ranges of the i.MX 8M Nano applications processor. For details on the
chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M Nano
Applications Processor Reference Manual (IMX8MNRM).
Table 15. Operating ranges for 14 x 14 mm package

Symbol Min Typ Max1 Unit Comment

VDD_ARM 0.805 0.850 0.950 V Power supply for Cortex® A53, 1.2 GHz

0.900 0.950 1.000 V Power supply for Cortex® A53, 1.4 GHz

0.950 1.000 1.050 V Power supply for Cortex® A53, 1.5 GHz2

VDD_SOC3 0.805 0.850 0.900 V Power supply for SoC logic4, Cortex® M7
600 MHz

0.900 0.950 1.000 V Power supply for SoC logic, overdrive

mode, Cortex® M7 750 MHz

VDD_GPU3 0.805 0.850 0.900 V Power supply for 3D GPU, nominal mode,
400 MHz

0.900 0.950 1.000 V Power supply for 3D GPU, overdrive

mode, 600 MHz

VDD_DRAM3 0.805 0.850 0.900 V Power supply for DDRC, 0.85 V supports
up to 1.2 GHz (DDR clock)

0.900 0.950 1.000 V Power supply for DDRC, 0.95 V supports

up to 1.6 GHz (DDR clock)

VDD_SNVS_0P8 0.760 0.800 0.900 V Power supply for SNVS core logic

NVCC_SNVS_1P8 1.620 1.800 1.980 V Power supply for GPIO pre-driver in

SNVS bank

NVCC_JTAG, 1.650 1.800 1.950 V Power supply for GPIO when it is in 1.8 V
NVCC_GPIO1, mode
NVCC_ENET, NVCC_SD1,
NVCC_SD2, NVCC_NAND,
NVCC_SAI2, NVCC_SAI3, 3.000 3.300 3.600 V Power supply for GPIO when it is in 3.3 V
NVCC_SAI5, mode
NVCC_ECSPI, NVCC_I2C,
NVCC_UART,
NVCC_CLK

NVCC_ENET 2.250 2.500 2.750 V Power supply for GPIO when it is in 2.5 V
mode

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 19

Downloaded from Arrow.com.

 Electrical characteristics

Table 15. Operating ranges for 14 x 14 mm package (continued)

Symbol Min Typ Max1 Unit Comment

PVCC0_1P8, 1.650 1.800 1.950 V Power supply for GPIO pre-driver

PVCC1_1P8,
PVCC2_1P8

VSS — — — V Ground for all core logic and I/O

NVCC_DRAM 1.283 1.35 1.425 V DDR3L

1.14 1.2 1.26 V DDR4

1.06 1.1 1.14 V LPDDR4

DRAM_VREF 0.49 x 0.5 x 0.51 x V Internal output, no connection is needed.

NVCC_DRAM NVCC_DRAM NVCC_DRAM

VDD_DRAM_PLL_0P8 0.805 0.850 0.900 V Power supply for DRAM PLL, nominal
mode

0.900 0.950 1.000 V Power supply for DRAM PLL, overdrive

mode

VDD_ANA0_1P8 1.71 1.8 1.89 V Analog 1.8 V core power

VDD_ANA1_1P8

VDD_ANA_0P8 0.805 0.850 0.900 V Supplies for Analog PLL, nominal mode

0.900 0.950 1.000 V Supplies for Analog PLL, overdrive mode

VDD_ARM_PLL_0P8 0.805 0.850 0.900 V Power supply for Arm PLL, nominal mode

0.900 0.950 1.000 V Power supply for Arm PLL, overdrive

mode

VDD_ARM_PLL_1P8 1.71 1.8 1.89 V Arm PLL 1.8 V power

VDD_24M_XTAL_1P8 1.71 1.8 1.89 V XTAL 1.8 V power

VDD_DRAM_PLL_1P8 1.71 1.8 1.89 V Analog 1.8 V core power

VDD_MIPI_0P8 0.805 0.850 0.900 V Digital supply for MIPI PHY, nominal
mode

0.900 0.950 1.000 V Digital supply for MIPI PHY, overdrive

mode

VDD_MIPI_1P2 1.14 1.2 1.26 V 1.2 V power for analog

VDD_MIPI_1P8 1.71 1.8 1.89 V 1.8 V power for PLL and analog

VDD_USB_0P8 0.805 0.850 0.900 V Digital power supply from PHY’s I/O
power pads, nominal mode

0.900 0.950 1.000 V Digital power supply from PHY’s I/O

power pads, overdrive mode

VDD_USB_1P8 1.71 1.80 1.89 V 1.8 V analog power supply

VDD_USB_3P3 3.069 3.30 3.6 V 3.3 V analog power supply

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
20 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 15. Operating ranges for 14 x 14 mm package (continued)

Symbol Min Typ Max1 Unit Comment

USB1_VBUS 1.34 — 3.60 V USB_VBUS input detect signal

Temperature Sensor — ±3 ±5 °C Sensing temperature range 10°C to

Accuracy5 105°C
T o
J 0 — +95 C See Table 3 for complete list of junction
temperature capabilities.
1
Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the
supply tolerance) is recommended. This results in an optimized power/speed ratio.
2
For VDD_ARM at 1.0V typical, Power-on Hours will decreased if junction temperature is increased. Please refer to i.MX 8M
Nano Product Lifetime Usage (AN12983) for details.
3
VDD_DRAM, VDD_SOC, and VDD_GPU are required to be tied together and keep same or ground.
4
Booting VDD_SOC at 0.800 V ±5% is acceptable (Vmin = 0.760 V). Software is expected to program the VDD_SOC voltage
to the typical value in this table prior to first DRAM memory access.
5
“EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly.

Table 16. Operating ranges for 11 x11 mm package

Symbol Min Typ Max1 Unit Comment

VDD_SOC 0.805 0.850 0.900 V Power supply for SoC logic2, Cortex® M7
600 MHz; Cortex® A53, 1.2 GHz,
nominal mode, 1.2 GHz DDR clock

0.900 0.950 1.000 V Power supply for SoC logic2, Cortex® M7

750 MHz; Cortex® A53, 1.4 GHz,
overdrive mode, 1.6 GHz DDR clock

VDD_SNVS_0P8 0.760 0.800 0.900 V Power supply for SNVS core logic

NVCC_SNVS_1P8 1.620 1.800 1.980 V Power supply for GPIO pre-driver in

SNVS bank

NVCC_I2C_UART, 1.650 1.800 1.950 V Power supply for GPIO when it is in 1.8 V
NVCC_SAI3_SAI5, mode
NVCC_SD1_NAND,
NVCC_ECSPI,
NVCC_SD2, 3.000 3.300 3.600 V Power supply for GPIO when it is in 3.3 V
NVCC_ENET_GPIO_SAI2 mode

NVCC_CLK_JTAG_PVCC_ 1.650 1.800 1.950 V Power supply for GPIO and GPIO
1P8 pre-driver in 1.8 V mode

VSS — — — V Ground for all core logic and I/O

NVCC_DRAM 1.283 1.35 1.425 V DDR3L

1.14 1.2 1.26 V DDR4

1.06 1.1 1.14 V LPDDR4

DRAM_VREF 0.49 x 0.5 x 0.51 x V Internal output, no connection is needed.

NVCC_DRAM NVCC_DRAM NVCC_DRAM

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 21

Downloaded from Arrow.com.

 Electrical characteristics

Table 16. Operating ranges for 11 x11 mm package (continued)

Symbol Min Typ Max1 Unit Comment

VDD_ANA1_XTAL_MIPI_U 1.71 1.8 1.89 V 1.8 V power for Analog core, XTAL, MIPI
SB_1P8, PLL and analog, USB analog and ARM
VDD_ANA0_ARM_PLL_1P PLL
8

VDD_DRAM_PLL_1P8 1.71 1.8 1.89 V Analog 1.8 V core power

VDD_MIPI_1P2 1.14 1.2 1.26 V 1.2 V power for analog

VDD_USB_3P3 3.069 3.30 3.6 V 3.3 V analog power supply

USB1_VBUS 1.34 — 3.60 V USB_VBUS input detect signal

Temperature Sensor — ±3 ±5 °C Sensing temperature range 10°C to

Accuracy2 105°C
T oC
J 0 — +95 See Table 3 for complete list of junction
temperature capabilities.
1
Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the
supply tolerance) is recommended. This results in an optimized power/speed ratio.
2 “EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly.

3.1.4 External clock sources

Each i.MX 8M Nano processor has two external input system clocks: a low frequency (RTC_XTALI) and
a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watch-dog counters. The clock input can only
be connected to an external oscillator. RTC_XTALO should be directly connected to VDD_SNVS_0P8.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either an external oscillator or a crystal using
internal oscillator amplifier.
Table 17 shows the interface frequency requirements.
Table 17. External input clock frequency

Parameter Description Symbol Min Typ Max Unit

RTC_XTALI Oscillator1 fckil — 32.7682 — kHz

1,3
XTALI Oscillator fxtal 24 MHz
1
The required frequency stability of this clock source is application dependent.
2 Recommended nominal frequency 32.768 kHz.
3 External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier.

The typical values shown in Table 17 are required for use with NXP software to ensure precise time
keeping and USB operation. For RTC_XTALI operation, an external oscillator is necessary. RTC_XTALO
should be directly connected to VDD_SNVS_0P8 when using an external 32.768 kHz oscillator.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
22 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

NOTE
There is no internal RC oscillator.
Table 18 shows the external input clock for OSC32K.
Table 18. External input clock for OSC32K

Symbol Min Typ Max Unit

Frequency f — 32.768 — kHz

RTC_XTALI VIH 0.7 x NVCC_SNVS_1P8 — NVCC_SNVS_1P8 V

VIL 0 — 0.3 x NVCC_SNVS_1P8 V

3.1.5 Estimated power supply maximum currents

Power consumption is highly dependent on the application. Estimating the maximum supply currents
required for power supply design is difficult because the use cases that requires maximum supply current
is not a realistic use cases.
The table below represents the estimated maximum current on the power supply rails and should be used
as a guideline for power supply selection. The data below is based on a combination of design simulation
and characterization data based on typical datasheet voltages. Actual power consumption for typical use
cases are lower than values presented on the table below.

Table 19. Estimated power supply maximum currents for 14 x 14 mm package

Power rail Max current Unit

VDD_ARM 2200 mA

VDD_SOC 1000 mA

VDD_GPU 800 mA

VDD_DRAM 800 mA

VDD_ANA_0P8 50 mA

VDD_ANA0_1P8 250 mA
VDD_ANA1_1P8

NVCC_SNVS_1P8 3 mA

NVCC_<XXX> Imax = N x C x V x (0.5 x F)

Where:
NVCC_DRAM N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock
rate (F).
In this equation, Imax is in Amps, C in Farads, V in
Volts, and F in Hertz.

DRAM_VFEF 10 mA

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 23

Downloaded from Arrow.com.

 Electrical characteristics

Table 20. Estimated power supply maximum currents for 11 x 11 mm package

Power rail Max current Unit

VDD_SOC 3000 mA

NVCC_SNVS_1P8 3 mA

VDD_ANA1_XTAL_MIPI_USB_1P8, 250 mA
VDD_ANA0_ARM_PLL_1P8,
VDD_DRAM_PLL_1P8

VDD_MIPI_1P2 100 mA

NVCC_<XXX> Imax = N x C x V x (0.5 x F)

Where:
NVCC_DRAM N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 x F)—Data change rate. Up to 0.5 of the clock
rate (F).
In this equation, Imax is in Amps, C in Farads, V in
Volts, and F in Hertz.

DRAM_VFEF 10 mA

3.1.6 Power modes

The i.MX 8M Nano supports the following power modes:
• RUN Mode: All external power rails are on, CPU is active and running; other internal modules can
be on/off based on application.
• IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU
can automatically enter this mode. The CPU can be in the power-gated state but with L2 data
retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still
remains powered. The M7 core can remain running. Compared with RUN mode, all the external
power rails from the PMIC remain the same, and most of the modules still remain in their state.
• SUSPEND Mode: The most efficient power saving mode where all the clocks are off and all the
unnecessary power supplies are off.
• SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains
on to keep RTC and SNVS logic alive.
• OFF Mode: All power rails are off.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
24 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 21 summaries the power supply states in all the power modes.
Table 21. Chip power in different LP mode for 14 x 14 mm package

Mode Supply Typ.1 Unit

SNVS VDD_SNVS_0P8 0.10

NVCC_SNVS_1P8 1.20 mW
2
Total 1.30

SUSPEND NVCC 0.80

NVCC_DRAM 2.40

NVCC_ENET 0.10

NVCC_SNVS_1P8 0.20

PVCC 0.60
mW
VDD_DRAM 9.40

VDD_MIPI_0P8 0.10

VDD_SNVS_0P8 0.10

VDD_SOC 4.50

VDD_ARM_PLL_0P8 0.10

VDD_USB_0P8 2.50

Total2 20.80

Low-V SUSPEND3 NVCC 0.70

NVCC_DRAM 1.50

NVCC_ENET 0.10

NVCC_SNVS_1P8 0.20

PVCC 0.60
mW
VDD_DRAM 6.80

VDD_MIPI_0P8 0.20

VDD_SNVS_0P8 0.10

VDD_SOC 3.50

VDD_ARM_PLL_0P8 0.10

VDD_USB_0P8 2.60

Total2 16.40
1
All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25oC, under
non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption
measurement application note for more details.
2 Sum of the listed supply rails.
3 Low-V suspend mode is low voltage suspend mode. Comparing with suspend mode (VDD_SOC/GPU/DRAM at 0.8 V), Low-V

suspend mode sets VDD_SOC/GPU/DRAM at 0.75 V.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 25

Downloaded from Arrow.com.

 Electrical characteristics

Table 22. Chip power in different LP mode for 11 x 11 mm package

Mode Supply Typ.1 Unit

SUSPEND VDD_SOC 12.1

NVCC_DRAM 2

VDD_SNVS_0P8 0.1

NVCC_SNVS_1P8 0.2

NVCC_CLK_JTAG_PVCC_1P8 1
mW
NVCC_I2C_UART 0.2
NVCC_SAI3_SAI5
NVCC_SD1_NAND
NVCC_ECSPI
NVCC_SD2

NVCC_ENET_GPIO_SAI2 0.3

Total 15.9
2
Low-V SUSPEND VDD_SOC 9.9

NVCC_DRAM 1.5

VDD_SNVS_0P8 0.1

NVCC_SNVS_1P8 0.2

NVCC_CLK_JTAG_PVCC_1P8 0.9
mW
NVCC_I2C_UART 0.2
NVCC_SAI3_SAI5
NVCC_SD1_NAND
NVCC_ECSPI
NVCC_SD2

NVCC_ENET_GPIO_SAI2 0.3

Total 13.1

SNVS VDD_SNVS_0P8 0.1 mW

NVCC_SNVS_1P8 0.3

Total 0.4
1
All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25oC, under
non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption
measurement application note for more details.
2 Low-V suspend mode is low voltage suspend mode. Comparing with suspend mode (VDD_SOC at 0.8 V), Low-V suspend

mode sets VDD_SOC at 0.75 V.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
26 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 23 and Table 25 summary the power supply states in all the power modes.

Table 23. The power supply states for 14 x 14 mm package

Power rail OFF SNVS SUSPEND1 IDLE RUN

VDD_ARM OFF OFF OFF ON ON

VDD_SOC OFF OFF ON ON ON

VDD_GPU OFF OFF OFF OFF ON/OFF

VDD_DRAM OFF OFF ON ON ON

Misc_1P82 OFF OFF ON ON ON

1
Misc_0P8 OFF OFF ON ON ON

VDD_MIPI_1P2 OFF OFF ON ON ON

VDD_MIPI_0P8 OFF OFF ON ON ON

VDD_DRAM_PLL_0P8 OFF OFF ON ON ON

VDD_SNVS_0P8 OFF ON ON ON ON

NVCC_SNVS_1P8 OFF ON ON ON ON

NVCC_<XXX> OFF OFF ON ON ON

PVCCx_1P8 OFF OFF ON ON ON

NVCC_DRAM OFF OFF ON ON ON

1 SUSPEND is covering normal suspend mode (VDD_SOC/GPU/DRAM at 0.8 V) and Low-V suspend
(VDD_SOC/GPU/DRAM at 0.75 V).
2 See Table 24

Table 24. Group name

Misc_1P8 VDD_24M_XTAL_1P8
VDD_ANA0_1P8
VDD_ANA1_1P8
VDD_ARM_PLL_1P8
VDD_DRAM_PLL_1P8
VDD_MIPI_1P8
VDD_USB_1P8

Misc_0P8 VDD_ANA_0P8
VDD_ARM_PLL_0P8
VDD_USB_0P8

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 27

Downloaded from Arrow.com.

 Electrical characteristics

Table 25. The power supply states for 11 x 11 mm package

Power rail OFF SNVS SUSPEND IDLE RUN

VDD_SOC OFF OFF ON ON ON

VDD_ANA1_XTAL_MIPI_ OFF OFF ON ON ON

USB_1P8,
VDD_ANA0_ARM_PLL_
1P8,
VDD_DRAM_PLL_1P8

VDD_MIPI_1P2 OFF OFF ON ON ON

VDD_SNVS_0P8 OFF ON ON ON ON

NVCC_SNVS_1P8 OFF ON ON ON ON

NVCC_<XXX> OFF OFF ON ON ON

NVCC_DRAM OFF OFF ON ON ON

3.2 Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario)

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
28 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.2.1 Power-up sequence

Figure 3 illustrates the power-up sequence for 14 x 14 mm package of i.MX 8M Nano applications
processor.

NVCC_SNVS_1P8
T1
VDD_SNVS_0P8
T2
RTC_RESET_B
T3
32K RTC_XTALI
t1
PMIC_ON_REQ
VDD_SOC,VDD_ANA_0P8,VDD_ARM_PLL_0P8 T4
VDD_USB_0P8
T5
VDD_GPU,VDD_DRAM,
VDD_DRAM_PLL_0P8
T6
VDD_MIPI_0P8
T7
VDD_ARM
VDD_ANAx_1P8,VDD_DRAM_PLL_1P8,VDD_MIPI_1P8, T8
VDD_24M_XTAL_1P8,VDD_USB_1P8
VDD_ARM_PLL_1P8 T9
PVCCx_1P8, NVCC_xxx (1.8 V)
T10
NVCC_DRAM
T11
NVCC_xxx (2.5 and 3.3 V),VDD_USB_3P3
T12
VDD_MIPI_1P2
T13
POR_B

Figure 3. The power-up sequence for 14 x 14 mm package

NOTE
VDD_MIPI_1P2 should power up after VDD_MIPI_0P8 and
VDD_MIPI_1P8, and it can power up before the POR_B release or after the
POR_B release.
Table 26 represents the timing parameters of the power-up sequence for 14 x 14 mm package.

Table 26. Power-up sequence for 14 x 14 mm package

Description Min Typ Max Unit

T1 Delay from NVCC_SNVS_1P8 to VDD_SNVS_0P8 0 2 — ms

T2 Delay from VDD_SNVS_0P8 high or RTC_SET_B de-assert 0 10 — ms

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 29

Downloaded from Arrow.com.

 Electrical characteristics

Table 26. Power-up sequence for 14 x 14 mm package (continued)

Description Min Typ Max Unit

T3 Delay from RTC_RESET_B de-assert to stable 32 k existed — 40 100 s

T4 Delay from PMIC_ON_REQ assert to analog 0.8 V on 0 0.2 — ms

T5 Delay from analog 0.8 V on to analog 0.8/0/9 V on 0 2 — ms

T6 Delay from analog 0.8/0.9 V on to PHY 0.9 V on 0 15 — s

T7 Delay from PHY 0.9 V on to VDD_ARM on 0 2 — ms

T8 Delay from VDD_ARM on to analog 1.8 V on 0 15 — s

T9 Delay from analog 1.8 V on to digital 1.8 V on 0 2 — ms

T10 Delay from digital 1.8 V on to NVCC_DRAM on 0 2 — ms

T11 Delay from NVCC_DRAM on to digital 2.5 V and 3.3 V on 0 2 — ms

T12 Delay from digital 2.5 V and 3.3 V on to PHY 1.2 V on 0 2 — ms

T131 Delay from digital 2.5 V and 3.3 V on to POR_B de-assert 0 20 — ms

t1 Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up.

For ramp up requirement, only VDD_ANA0_1P8 has 5 s minimum requirement, others do not have such
requirement.
During power-up, make sure NVCC_xxx - PVCCx_1P8 < 2 V.
1
The values of T13 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
30 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Figure 4 illustrates the power-up sequence for 11 x 11 mm package of i.MX 8M Nano applications
processor.

NVCC_SNVS_1P8
T1
VDD_SNVS_0P8
T2
RTC_RESET_B
T3
32K RTC_XTALI
t1
PMIC_ON_REQ
T4
VDD_SOC
T5
VDD_ANA1_XTAL_MIPI_USB_1P8,
VDD_ANA0_ARM_PLL_1P8,VDD_DRAM_PLL_1P8
T6
NVCC_xxx (1.8V)
T7
NVXX_DRAM
T8
NVCC_xxx (3.3 V), VDD_USB_3P3
T9
VDD_MIPI_1P2
T10
POR_B

Figure 4. The power-up sequence for 11 x 11 mm package

NOTE
VDD_MIPI_1P2 should power up after Analog 1.8 V on, and it can power
up before POR_B release or after POR_B release.
Table 27 represents the timing parameters of the power-up sequence for 11 x 11 mm package.
Table 27. Power-up sequence for 11 x 11 mm package

Description Min Typ Max Unit

T1 Delay from NVCC_SNVS_1P8 to VDD_SNVS_0P8 0 2 — ms

T2 Delay from VDD_SNVS_0P8 high or RTC_SET_B de-assert 0 10 — ms

T3 Delay from RTC_RESET_B de-assert to stable 32 k existed — 40 100 s

T4 Delay from PMIC_ON_REQ assert to ARM, analog and PHY 0 5 — ms

0.8/0.9 V on

T5 Delay from SOC, analog and PHY 0.8/0.9 V to analog 1.8 V on 0 15 — s

T6 Delay from analog 1.8 V on to digital 1.8 V on 0 2 — ms

T7 Delay from digital 1.8 V on to NVCC_DRAM on 0 2 — ms

T8 Delay from NVCC_DRAM on to digital 3.3 V on 0 2 — ms

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 31

Downloaded from Arrow.com.

 Electrical characteristics

Table 27. Power-up sequence for 11 x 11 mm package (continued)

Description Min Typ Max Unit

T9 Delay from analog 1.8 V on to PHY 1.2 V on 0 2 — ms

T10 Delay from digital 3.3 V on to POR_B de-assert1 0 20 — ms

t1 Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up.

For ramp up requirement, only VDD_ANA0_ARM_PLL_1P8 has 5 s minimum requirement, others do not have
such requirement.
1
The values of T10 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts.

3.2.2 Power-down sequence

Figure 5 illustrates the power-down sequence for 14 x 14 mm package of i.MX 8M Nano applications
processor.

VDD_MIPI_1P2
T1
NVCC_xxx (2.5 and 3.3 V)
T2
NVCC_DRAM
T3
PVCCx_1P8, NVCC_xxx (1.8V)
T4
VDD_ANAx_1P8, VDD_DRAM_PLL_1P8,VDD_MIPI_1P8
VDD_24M_XTAL_1P8,VDD_USB_1P8
T5
VDD_ARM
T6
VDD_MIPI_0P8
VDD_GPU, VDD_DRAM,
T7
VDD_DRAM_PLL_0P8
T8
VDD_SOC, VDD_ANA_0P8
VDD_USB_0P8
T9
32K RTC_XTALI
T10
RTC_RESET_B
T11
VDD_SNVS_0P8
T12
NVCC_SNVS_1P8

Figure 5. The power-down sequence for 14 x 14 mm package

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
32 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 28 represents the timing parameters of the power-down sequence for 14 x 14 mm package.
Table 28. Power-down sequence for 14 x 14 mm package

Description Min Typ Max Unit

T1 Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off 0 10 — ms

T2 Delay from digital 2.5 V and 3.3 V off to NVCC_DRAM off 0 10 — ms

T3 Delay from NVCC_DRAM off to digital 1.8 V off 0 10 — ms

T4 Delay from digital 1.8 V off to analog 1.8 V off 0 10 — ms

T5 Delay from analog 1.8 V off to VDD_ARM off 0 10 — ms

T6 Delay from VDD_ARM off to PHY 0.9 V off 0 10 — ms

T7 Delay from PHY 0.9 V off to analog 0.8/0.9 V off 0 10 — ms

T8 Delay from analog 0.8/0.9 V off to analog 0.8 V off 0 10 — ms

T9 Delay from analog 0.8 V off to 32k off 0 10 — ms

T10 Delay from 32k off to RTC_RESET_B assert 0 10 — ms

T11 Delay from RTC_RESET_B assert to VDD_SNVS_0P8 off 0 10 — ms

T12 Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off 0 10 — ms

During power-down, make sure NVCC_xxx - PVCCx_1P8 < 2 V.

Figure 6 illustrates the power-down sequence for 11 x 11 mm package of i.MX 8M Nano applications
processor.

VDD_MIPI_1P2
T1
NVCC_xxx (3.3 V)
T2
NVCC_DRAM
T3
NVCC_xxx (1.8 V)
T4
VDD_ANA1_XTAL_MIPI_USB_1P8
VDD_ANA0_ARM_PLL_1P8,VDD_DRAM_PLL_1P8 T5
VDD_SOC
T6
32K RTC_XTALI
T7
RTC_RESET_B
T8
VDD_SNVS_0P8
T9
NVCC_SNVS_1P8

Figure 6. The power-down sequence for 11 x 11 mm package

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 33

Downloaded from Arrow.com.

 Electrical characteristics

Table 29 represents the timing parameters of the power-down sequence for 11 x 11 mm package.
Table 29. Power-down sequence for 11 x 11 mm package

Description Min Typ Max Unit

T1 Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off 0 10 — ms

T2 Delay from digital 2.5 V and 3.3 V off to NVCC_DRAM off 0 10 — ms

T3 Delay from NVCC_DRAM off to digital 1.8 V off 0 10 — ms

T4 Delay from digital 1.8 V off to analog 1.8 V off 0 10 — ms

T5 Delay from analog 1.8 V off to VDD_SOC off 0 40 — ms

T6 Delay from VDD_SOC off to 32k off 0 10 — ms

T7 Delay from 32k off to RTC_RESET_B assert 0 10 — ms

T8 Delay from RTC_RESET_B assert to VDD_SNVS_0P8 off 0 10 — ms

T9 Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off 0 10 — ms

3.3 PLL electrical characteristics

Table 30 shows PLL electrical characteristics.

Table 30. PLL electrical parameters

PLL type Parameter Value

AUDIO_PLL1 Clock output range Maximum 650 MHz

Reference clock 24 MHz

Lock time1 500 s

AUDIO_PLL2 Clock output range Maximum 650 MHz

Reference clock 24 MHz

Lock time 500 s

VIDEO_PLL1 Clock output range Maximum 650 MHz

Reference clock 24 MHz

Lock time 500 s

SYS_PLL1 Clock output range 800 MHz

Reference clock 24 MHz

Lock time 50 s

SYS_PLL2 Clock output range 1 GHz

Reference clock 24 MHz

Lock time 50 s

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
34 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 30. PLL electrical parameters (continued)

PLL type Parameter Value

SYS_PLL3 Clock output range 600 MHz — 1 GHz

Reference clock 24 MHz

Lock time 50 s

ARM_PLL Clock output range 800 MHz — 2 GHz

Reference clock 24 MHz

Lock time 50 s

M7_ALT_PLL Clock output range 400 MHz — 800 MHz

Reference clock 24 MHz

Lock time 50 s

DRAM_PLL Clock output range 400 MHz — 800 MHz

Reference clock 24 MHz

Lock time 500 s

GPU_PLL Clock output range 800 MHz — 1600 MHz

Reference clock 24 MHz

Lock time 50 s
1
Lock time is referring from PLL enable to valid lock flag time.

3.4 On-chip oscillators

3.4.1 OSC24M
A 24 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU,
BUS, and high-speed interfaces. For fractional PLLs, the 24 MHz clock from the oscillator can be used as
the PLL reference clock directly.

Table 31. Crystal specifications1

Parameter Description Min Typ Max Unit

Frequency — 24 — MHz

Cload — 12 — pF

Drive level 100 — — W

ESR — — 80 
1
Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 35

Downloaded from Arrow.com.

 Electrical characteristics

3.4.2 OSC32K
An external 32.768 kHz oscillator is necessary.

3.5 General purpose I/O (GPIO) DC parameters

Table 32 shows DC parameters for GPIO pads. The parameters in Table 32 are guaranteed per the
operating ranges in Table 15, unless otherwise noted.

Table 32. GPIO DC parameters

Parameter Symbol Test Conditions Min Typ Max Unit

High-level output voltage VOH (1.8 V) IOH = 1.6/3.2/6.4/9.6 mA (1.8 V) 0.8 x VDD — VDD V
IOH = 2/4/8/12 mA (3.3 V)
VOH (3.3 V) 0.8 x VDD — VDD V

Low-level output voltage VOL (1.8 V) IOL = 1.6/3.2/6.4/9.6 mA (1.8 V) 0 — 0.2 x VDD V
IOL = 2/4/8/12 mA (3.3 V)
VOL (3.3 V) 0 — 0.2 x VDD V

High-level input voltage VIH — 0.7 x VDD — VDD + 0.3 V

Low-level input voltage VIL — -0.3 — 0.3 x VDD V

Pull-up resistor — VDD = 1.65 - 1.95V 12 22 49 K

Temp = 0 - 95 oC
Pull-down resistor — 13 23 48 K

Pull-up resistor — VDD = 2.25 - 2.75V 13 24 69 K

Temp = 0 - 95 oC
Pull-down resistor — 9.1 33 69 K

Pull-up resistor — VDD = 3.0 - 3.6V 18 37 72 K

Temp = 0 - 95 oC
Pull-down resistor — 24 43 87 K

High level input current IIH — -4 — 4 A

Low level input current IIL — -0.7 — 0.7 A

Table 33. Additional leakage parameters

Parameter Symbol Pins Min Max Unit

USB1_Dx -30 30

High level input current IIH MIPI_CSI -4 4 A

USB1_ID, ONOFF, POR_B -1 1

USB1_ID -200 200

Low level input current IIL USB1_Dx -6 6 A

MIPI_CSI, ONOFF, POR_B -0.7 0.7

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
36 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.5.1 DDR I/O DC electrical characteristics

The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory
Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs.
DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout
requirements stated in the hardware development guide for the i.MX 8M Nano applications processor.

3.6 I/O AC parameters

This section includes the AC parameters of the following I/O types:
• General Purpose I/O (GPIO)
The GPIO load circuit and output transition time waveforms are shown in Figure 7 and Figure 8.
From Output Test Point
Under Test
CL

CL includes package, probe and fixture capacitance

Figure 7. Load circuit for output

OVDD
80% 80%

20% 20%
Output (at pad) 0V
tr tf

Figure 8. Output transition time waveform

3.6.1 General purpose I/O AC parameters

This section presents the I/O AC parameters for GPIO in different modes. Note that the fast or slow I/O
behavior is determined by the appropriate control bits in the IOMUXC control registers.
Table 34. Maximum frequency of operation for input

Maximum frequency (MHz)

VDD = 1.8 V, CL = 50 pF VDD = 3.3 V, CL = 50 pF

450 440

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 37

Downloaded from Arrow.com.

 Electrical characteristics

Table 35. Maximum frequency of operation for output

Maximum Frequency (MHz)

Parameter
VDD = 1.8 V VDD = 3.3 V

dse[2:0] sre[1:0] Driver type CL = 10 pF CL = 20 pF CL = 10 pF CL = 20 pF

00X 0X 1x Slow Slew 150 80 120 65

00X 1X 1x Fast Slew 150 80 120 65

10X 0X 2x Slow Slew 160 90 150 80

10X 1X 2x Fast Slew 160 90 150 80

01X 0X 4x Slow Slew 200 100 180 90

01X 1X 4x Fast Slew 200 100 180 90

11X 0X 6x Slow Slew 250 130 200 100

11X 1X 6x Fast Slew 250 130 200 100

3.7 Output buffer impedance parameters

This section defines the I/O impedance parameters of the i.MX 8M Nano family of processors for the
following I/O types:
NOTE
DDR I/O output driver impedance is measured with “long” transmission
line of impedance Ztl attached to I/O pad and incident wave launched into
transmission line. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 9).

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
38 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

OVDD

PMOS (Rpu)
Ztl W, L = 20 inches
ipp_do pad
predriver
Cload = 1p

NMOS (Rpd)

OVSS
U,(V)
Vin (do)
VDD

t,(ns)
0

U,(V)
Vout (pad)
OVDD

Vref1 Vref2
Vref

t,(ns)
0
Vovdd - Vref1
Rpu = x Ztl
Vref1

Vref2
Rpd = x Ztl
Vovdd - Vref2

Figure 9. Impedance matching load for measurement

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 39

Downloaded from Arrow.com.

 Electrical characteristics

3.7.1 DDR I/O output buffer impedance

Table 36 shows DDR I/O output buffer impedance of i.MX 8M Nano family of processors.
Table 36. DDR I/O output buffer impedance

Typical
Test Conditions
Parameter Symbol DSE Unit
NVCC_DRAM = 1.35 V NVCC_DRAM = 1.2 V NVCC_DRAM = 1.1 V
(Drive Strength)
(DDR3L) (DDR4) (LPDDR4)

Output Driver Rdrv 000000 Hi-Z Hi-Z Hi-Z

Impedance
000010 240 240 240

001000 120 120 120

001010 80 80 80

011000 60 60 60

011010 48 48 48

111000 40 40 40

111010 34 34 34

Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240  external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

3.8 System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 8M Nano
processor.

3.8.1 Reset timings parameters

Figure 10 shows the reset timing and Table 37 lists the timing parameters.

POR_B
(Input)

CC1

Figure 10. Reset timing diagram

Table 37. Reset timing parameters

ID Parameter Min Max Unit

CC1 Duration of POR_B to be qualified as valid. 1 — RTC_XTALI cycle

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
40 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.8.2 WDOG Reset timing parameters

Figure 11 shows the WDOG reset timing and Table 38 lists the timing parameters.

WDOGx_B
(Output)

CC3

Figure 11. WDOGx_B timing diagram

Table 38. WDOGx_B timing parameters

ID Parameter Min Max Unit

CC3 Duration of WDOG1_B Assertion 1 — RTC_XTALI cycle

NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOGx_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the
IOMUXC chapter of the i.MX 8M Nano Applications Processor Reference
Manual (IMX8MNRM) for detailed information.

3.9 External peripheral interface parameters

The following subsections provide information on external peripheral interfaces.

3.9.1 ECSPI timing parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing
parameters for master and slave modes.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 41

Downloaded from Arrow.com.

 Electrical characteristics

3.9.1.1 ECSPI Master mode timing

Figure 12 depicts the timing of ECSPI in master mode. Table 39 lists the ECSPI master mode timing
characteristics.

ECSPIx_RDY_B

ECSPIx_SS_B CS10 CS5

CS3 CS2 CS6
CS1
CS4
ECSPIx_SCLK
CS2
CS7 CS3

ECSPIx_MOSI

CS9
CS8
ECSPIx_MISO

Figure 12. ECSPI Master mode timing diagram

Table 39. ECSPI Master mode timing parameters

ID Parameter Symbol Min Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read tclk 43 — ns

ECSPIx_SCLK Cycle Time–Write 15

CS2 ECSPIx_SCLK High or Low Time–Read tSW 21.5 — ns

ECSPIx_SCLK High or Low Time–Write 7

CS3 ECSPIx_SCLK Rise or Fall1 tRISE/FALL — — ns

CS4 ECSPIx_SS_B pulse width tCSLH Half ECSPIx_SCLK period — ns

CS5 ECSPIx_SS_B Lead Time (CS setup time) tSCS Half ECSPIx_SCLK period - 4 — ns

CS6 ECSPIx_SS_B Lag Time (CS hold time) tHCS Half ECSPIx_SCLK period - 2 — ns
CS7 ECSPIx_MOSI Propagation Delay (CLOAD = 20 pF) tPDmosi -1 1 ns

CS8 ECSPIx_MISO Setup Time tSmiso 18 — ns

CS9 ECSPIx_MISO Hold Time tHmiso 0 — ns

CS10 RDY to ECSPIx_SS_B Time2 tSDRY 5 — ns

1
See specific I/O AC parameters Section 3.6, I/O AC parameters”.
2
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
42 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.9.1.2 ECSPI Slave mode timing

Figure 13 depicts the timing of ECSPI in Slave mode. Table 40 lists the ECSPI Slave mode timing
characteristics.

ECSPIx_SS_B
CS1 CS2 CS6 CS5
CS4
ECSPIx_SCLK
CS2
CS9
ECSPIx_MISO

CS7 CS8
ECSPIx_MOSI

Figure 13. ECSPI Slave mode timing diagram

Table 40. ECSPI Slave mode timing parameters

ID Parameter Symbol Min Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read tclk 15 — ns

ECSPI_SCLK Cycle Time–Write 43

CS2 ECSPIx_SCLK High or Low Time–Read tSW 7 — ns

ECSPIx_SCLK High or Low Time–Write 21.5

CS4 ECSPIx_SS_B pulse width tCSLH Half ECSPIx_SCLK period — ns

CS5 ECSPIx_SS_B Lead Time (CS setup time) tSCS 5 — ns

CS6 ECSPIx_SS_B Lag Time (CS hold time) tHCS 5 — ns

CS7 ECSPIx_MOSI Setup Time tSmosi 4 — ns

CS8 ECSPIx_MOSI Hold Time tHmosi 4 — ns

CS9 ECSPIx_MISO Propagation Delay (CLOAD = 20 pF) tPDmiso 4 19 ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 43

Downloaded from Arrow.com.

 Electrical characteristics

3.9.2 Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC

timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data
rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing.

3.9.2.1 SD/eMMC5.1 (single data rate) AC timing

Figure 14 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 41 lists the SD3.0/eMMC5.1 (SDR)
timing characteristics.
SD4

SD2
SD1
SD5

SDx_CLK
SD3
SD6

Output from uSDHC to card

SDx_DATA[7:0]
SD7 SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 14. SD3.0/eMMC5.1 (SDR) timing

Table 41. SD3.0/eMMC5.1 (SDR) interface timing specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock Frequency (Low Speed) fPP1 0 400 kHz

Clock Frequency (SD/SDIO Full Speed/High Speed) fPP2 0 25/50 MHz

Clock Frequency (MMC Full Speed/High Speed) fPP3 0 20/52 MHz

Clock Frequency (Identification Mode) fOD 100 400 kHz

SD2 Clock Low Time tWL 7 — ns

SD3 Clock High Time tWH 7 — ns

SD4 Clock Rise Time tTLH — 3 ns

SD5 Clock Fall Time tTHL — 3 ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6 uSDHC Output Delay tOD 6.6 3.6 ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
44 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 41. SD3.0/eMMC5.1 (SDR) interface timing specification (continued)

ID Parameter Symbols Min Max Unit

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7 uSDHC Input Setup Time tISU 2.5 — ns

4
SD8 uSDHC Input Hold Time tIH 1.5 — ns
1
In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2
In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0 – 25 MHz. In High-speed mode,
clock frequency can be any value between 0 – 50 MHz.
3
In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0 – 20 MHz. In High-speed mode,
clock frequency can be any value between 0 – 52 MHz.
4
To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

3.9.2.2 eMMC5.1/SD3.0 (dual data rate) AC timing

Figure 15 depicts the timing of eMMC5.1/SD3.0 (DDR). Table 42 lists the eMMC5.1/SD3.0 (DDR)
timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to
CMD).

SD1

SDx_CLK

SD2 SD2

Output from eSDHCv3 to card

......
SDx_DATA[7:0]
SD3 SD4

Input from card to eSDHCv3

SDx_DATA[7:0] ......

Figure 15. eMMC5.1/SD3.0 (DDR) timing

Table 42. eMMC5.1/SD3.0 (DDR) interface timing specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock Frequency (eMMC5.1 DDR) fPP 0 52 MHz

SD1 Clock Frequency (SD3.0 DDR) fPP 0 50 MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2 uSDHC Output Delay tOD 2.7 6.9 ns

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 45

Downloaded from Arrow.com.

 Electrical characteristics

Table 42. eMMC5.1/SD3.0 (DDR) interface timing specification (continued)

ID Parameter Symbols Min Max Unit

SD3 uSDHC Input Setup Time tISU 2.4 — ns

SD4 uSDHC Input Hold Time tIH 1.3 — ns

3.9.2.3 HS400 DDR AC timing

Figure 16 depicts the timing of HS400 mode, and Table 43 lists the HS400 timing characteristics. Be
aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD
input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check
SD5, SD6, and SD7 parameters in Table 45 SDR50/SDR104 Interface Timing Specification for CMD
input/output timing for HS400 mode.

SD1
SD2 SD3
SCK
SD4 SD5 SD4 SD5
DAT0
Output from DAT1
...
uSDHC to eMMC DAT7

Strobe
SD6 SD7
DAT0
Input from DAT1
eMMC to uSDHC ...
DAT7

Figure 16. HS400 Mode timing

Table 43. HS400 interface timing specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock frequency fPP 0 200 MHz

SD2 Clock low time tCL 0.46 x tCLK 0.54 x tCLK ns

SD3 Clock high time tCH 0.46 x tCLK 0.54 x tCLK ns

uSDHC Output/Card Inputs DAT (Reference to SCK)

SD4 Output skew from data of edge of SCK tOSkew1 0.45 — ns

SD5 Output skew from edge of SCk to data tOSkew2 0.45 — ns

uSDHC Input/Card Outputs DAT (Reference to Strobe)

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
46 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 43. HS400 interface timing specification (continued)

ID Parameter Symbols Min Max Unit

SD6 uSDHC input skew tRQ — 0.45 ns

SD7 uSDHC hold skew tRQH — 0.45 ns

3.9.2.4 HS200 Mode AC timing

Figure 17 depicts the timing of HS200 mode, and Table 44 lists the HS200 timing characteristics.

SD1

SD2 SD3

SCK
SD4/SD5

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

Figure 17. HS200 timing

iti

Table 44. HS200 interface timing specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock Frequency Period tCLK 5.0 — ns

SD2 Clock Low Time tCL 0.3 x tCLK 0.7 x tCLK ns

SD3 Clock High Time tCH 0.3 x tCLK 0.7 x tCLK ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5 uSDHC Output Delay tOD -1.6 1 ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1

SD8 uSDHC Output Data Window tODW 0.5 x tCLK — ns

1 HS200 is for 8 bits while SDR104 is for 4 bits.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 47

Downloaded from Arrow.com.

 Electrical characteristics

3.9.2.5 SDR50/SDR104 AC timing

Figure 18 depicts the timing of SDR50/SDR104, and Table 45 lists the SDR50/SDR104 timing
characteristics.

SD1

SD2 SD3

SCK
SD4/SD5

8-bit output from uSDHC to eMMC

SD6 SD7

8-bit input from eMMC to uSDHC

SD8

Figure 18. SDR50/SDR104 timing

Table 45. SDR50/SDR104 interface timing specification

ID Parameter Symbols Min Max Unit

Card Input Clock

SD1 Clock Frequency Period tCLK 5 — ns

SD2 Clock Low Time tCL 0.46 x tCLK 0.54 x tCLK ns

SD3 Clock High Time tCH 0.46 x tCLK 0.54 x tCLK ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4 uSDHC Output Delay tOD -3 1 ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5 uSDHC Output Delay tOD -1.6 1 ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD6 uSDHC Input Setup Time tISU 2.4 — ns

SD7 uSDHC Input Hold Time tIH 1.4 — ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1

SD8 uSDHC Output Data Window tODW 0.5 x tCLK — ns

1
Data window in SDR100 mode is variable.

3.9.2.6 Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.5/5.0/5.1 can be 1.8 V or 3.3 V depending on the working mode. The DC
parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are identical to those shown in
Table 32, "GPIO DC parameters," on page 36.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
48 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.9.3 Ethernet controller (ENET) AC electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive
at timing specs/constraints for the physical interface.
Table 46. ENET signal mapping

RGMII/RMII
Pad name Mode Alt mode Direction Comments
signal

ENET_MDC MDC RMII/RGMII ALT0 O —

ENET_MDIO MDIO RMII/RGMII ALT0 I/O —

ENET_TD3 TX_D3 RGMII ALT0 O Only used for RGMII

ENET_TD2 REF_CLK RMII ALT1 I/O Used as RMII clock and RGMII data, there
are two RMII clock schemes.
TX_D2 RGMII ALT0 • MAC generate output 50M reference clock
for PHY, and MAC also use this 50M clock.
• MAC use external 50M clock.
For RMII—ENET_TD2 functions as RMII
REF_CLK when configured in the ALT1
mode.

ENET_TD1 TX_D1 RMII/RGMII ALT0 O —

ENET_TD0 TX_D0 RMII/RGMII ALT0 O —

ENET_TX_CTL TX_EN RMII ALT0 O —

TX_CTL RGMII ALT0

ENET_TXC TX_ER RMII ALT1 O For RMII—ENET_TXC functions as RMII

TX_ER when configured in the ALT1 mode.
TXC RGMII ALT0 For RGMII—ENET_TXC functions as RGMII
TXC when configured in the ALT0 mode.

ENET_RX_CTL RX_EN RMII ALT0 I —

(CRS_DV)

RX_CTL RGMII ALT0

ENET_RXC RX_ER RMII ALT1 I For RMII—ENET_RXC functions as RMII

RX_ER when configured in the ALT1 mode.
RXC RGMII ALT0 For RGMII—ENET_RXC functions as RGMII
RXC when configured in the ALT0 mode.

ENET_RD0 RX_D0 RMII/RGMII ALT0 I —

ENET_RD1 RX_D1 RMII/RGMII ALT0 I —

ENET_RD2 RX_D2 RGMII ALT0 I —

ENET_RD3 RX_D3 RGMII ALT0 I —

GPIO1_IO06 MDC RMII/RGMII ALT1 O —

GPIO1_IO07 MDIO RMII/RGMII ALT1 I/O —

I2C1_SCL MDC RMII/RGMII ALT1 O —

I2C1_SDA MDIO RMII/RGMII ALT1 I/O —

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 49

Downloaded from Arrow.com.

 Electrical characteristics

Table 46. ENET signal mapping (continued)

RGMII/RMII
Pad name Mode Alt mode Direction Comments
signal

GPIO1_IO08 1588_EVENT0_ RMII/RGMII ALT1 I Capture/compare block input/output event

IN bus signal. When configured for capture and
a rising edge is detected, the current timer
value is latched and transferred into the
corresponding ENET_TCCRn register for
inspection by software. When configured for
compare, the corresponding signal
1588_EVENT is asserted for one cycle when
the timer reaches the compare value
programmed in register ENET_TCCRn. An
interrupt or DMA request can be triggered if
the corresponding bit in ENET_TCSRn[TIE]
or ENET_TSCRn[TDRE] is set.

GPIO1_IO09 1588_EVENT0_ RMII/RGMII ALT1 O —

OUT

I2C2_SCL 1588_EVENT1_ RMII/RGMII ALT1 I —

IN

I2C2_SDA 1588_EVENT1_ RMII/RGMII ALT1 O —

OUT

GPIO1_IO00 ENET_PHY_RE RGMII ALT1 O Reference clock for PHY.

F_CLK_ROOT

SD1_CLK MDC RMII ALT1 O —

SD1_CMD MDIO RMII ALT1 I/O —

SD1_DATA0 TX_D1 RMII ALT1 O —

SD1_DATA1 TX_D0 RMII ALT1 O —

SD1_DATA2 RX_D0 RMII ALT1 I —

SD1_DATA3 RX_D1 RMII ALT1 I —

SD1_DATA4 TX_EN RMII ALT1 O —

SD1_DATA5 TX_ER RMII ALT1 O For RMII—SD1_DATA5 functions as RMII

TX_ER when configured in the ALT1 mode.

SD1_DATA6 RX_EN RMII ALT1 I —

(CRS_DV)

SD1_DATA7 RX_ER RMII ALT1 I For RMII—SD1_DATA7 functions as RMII

RX_ER when configured in the ALT1 mode.

SD1_RESET_B REF_CLK RMII ALT1 O For RMII—SD1_RESET_B functions as RMII

REF_CLK when configured in the ALT1
mode.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
50 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.9.3.1 RMII mode timing

Figure 19 shows RMII mode timings. Table 47 describes the timing parameters (M16–M21) shown in the
figure.

M16

M17
ENET_CLK (input)

M18

ENET_TXD[1:0] (output)
ENET_TX_EN

M19

ENET_RX_EN (input)
ENET_RXD[1:0]
ENET_RX_ER
M20 M21

Figure 19. RMII mode signal timing diagram

Table 47. RMII signal timing

ID Characteristic Min. Max. Unit

M16 ENET_CLK pulse width high 35% 65% ENET_CLK period

M17 ENET_CLK pulse width low 35% 65% ENET_CLK period
M18 ENET_CLK to ENET_TXD[1:0], ENET_TXD invalid 4 — ns
M19 ENET_CLK to ENET_TXD[1:0], ENET_TXD valid — 15 ns
M20 ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER to ENET_CLK setup 4 — ns
M21 ENET_CLK to ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER hold 2 — ns

3.9.3.2 RGMII signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 51

Downloaded from Arrow.com.

 Electrical characteristics

Table 48. RGMII signal switching specifications1

Symbol Description Min. Max. Unit

Tcyc2 Clock cycle duration 7.2 8.8 ns

TskewT3 Data to clock output skew at transmitter -500 500 ps
TskewR 3 Data to clock input skew at receiver 1 2.6 ns
4
Duty_G Duty cycle for Gigabit 45 55 %
Duty_T4 Duty cycle for 10/100T 40 60 %
Tr/Tf Rise/fall time (20–80%) — 0.75 ns
1
The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
2
For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
3
For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional
trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value
is unspecified.
4
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.

2'-))?48#ATTRANSMITTER
4SKEW4

2'-))?48$NNTO

2'-))?48?#4, 48%. 48%22

4SKEW2

2'-))?48#ATRECEIVER

Figure 20. RGMII transmit signal timing diagram original

2'-))?28#ATTRANSMITTER
4SKEW4

2'-))?28$NNTO

2'-))?28?#4, 28$6 28%22

4SKEW2

2'-))?28#ATRECEIVER

Figure 21. RGMII receive signal timing diagram original

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
52 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

)NTERNALDELAY
2'-))?28#SOURCEOFDATA

4SETUP4 4HOLD4

2'-))?28$NNTO

2'-))?28?#4, 28$6 28%22

4SETUP2 4HOLD2

2'-))?28#ATRECEIVER

Figure 22. RGMII receive signal timing diagram with internal delay

3.9.4 General-purpose media interface (GPMI) timing

The i.MX 8M Nano GPMI controller is a flexible interface NAND Flash controller with 8-bit data width,
up to 200 MB/s I/O speed and individual chip select.
It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode
separately, as described in the following subsections.

3.9.4.1 Asynchronous mode AC timing (ONFI 1.0 compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 23 through Figure 26
depicts the relative timing between GPMI signals at the module level for different operations under
Asynchronous mode. Table 49 describes the timing parameters (NF1–NF17) that are shown in the figures.

.!.$?#,% NF1 NF2

NF3 NF4
.!.$?#%?"

.!.$?7%?" NF5

.!.$?!,% NF6 NF7

NF8 NF9
.!.$?$!4!XX Command

Figure 23. Command Latch cycle timing diagram

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 53

Downloaded from Arrow.com.

 Electrical characteristics

NF1
.!.$?#,%

NF3
.!.$?#%?"
NF10
.!.$?7%?" NF5 NF11

.!.$?!,% NF6 NF7

NF8 NF9
NAND_DATAxx Address

Figure 24. Address Latch cycle timing diagram

.!.$?#,% NF1

.!.$?#%?" NF3
NF10
.!.$?7%?" NF5 NF11

.!.$?!,% NF6 NF7

NF8 NF9
.!.$?$!4!XX Data to NF

Figure 25. Write Data Latch cycle timing diagram

.!.$?#,%

.!.$?#%?"
NF14
.!.$?2%?" NF13 NF15

.!.$?2%!$9?" NF12
NF16 NF17

.!.$?$!4!XX Data from NF

Figure 26. Read Data Latch cycle timing diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%?"
NF14

.!.$?2%?" NF13 NF15

.!.$?2%!$9?" NF12 NF17

NF16
NAND_DATAxx Data from NF

Figure 27. Read Data Latch cycle timing diagram (EDO mode)

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
54 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 49. Asynchronous mode timing parameters1

Timing
T = GPMI Clock Cycle
ID Parameter Symbol Unit
Min. Max.

NF1 NAND_CLE setup time tCLS (AS + DS)  T - 0.12 [see notes2,3 ] ns
NF2 NAND_CLE hold time tCLH DH  T - 0.72 [see note ] 2
ns
NF3 NAND_CE0_B setup time tCS (AS + DS + 1)  T [see notes 3,2
] ns
NF4 NAND_CE0_B hold time tCH (DH+1)  T - 1 [see note2 ] ns
NF5 NAND_WE_B pulse width tWP DS  T [see note ]2
ns
NF6 NAND_ALE setup time tALS (AS + DS)  T - 0.49 [see notes 3,2
] ns
NF7 NAND_ALE hold time tALH DH  T - 0.42 [see note2 ] ns
NF8 Data setup time tDS DH  T - 0.26 [see note2] ns
NF9 Data hold time tDH DH  T - 1.37 [see note2] ns
NF10 Write cycle time tWC (DS + DH)  T [see note2] ns
NF11 NAND_WE_B hold time tWH DH  T [see note2] ns
NF12 Ready to NAND_RE_B low tRR4 (AS + 2)  T [see 3,2] — ns
NF13 NAND_RE_B pulse width tRP DS  T [see note2] ns
NF14 READ cycle time tRC (DS + DH)  T [see note2] ns
NF15 NAND_RE_B high hold time tREH DS  T [see note2] ns
NF16 Data setup on read tDSR — (DS  T -0.67)/18.38 [see ns
notes5,6]
NF17 Data hold on read tDHR 0.82/11.83 [see notes5,6] — ns
1
GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2 AS minimum value can be 0, while DS/DH minimum value is 1.
3
T = GPMI clock period -0.075 ns (half of maximum p-p jitter).
4
NF12 is guaranteed by the design.
5 Non-EDO mode.
6
EDO mode, GPMI clock  100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 26), NF16/NF17 are different from the definition in non-EDO mode (Figure 25).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples
NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay
value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Nano
Applications Processor Reference Manual [IMX8MNRM]). The typical value of this control register is
0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value
should be made larger to compensate the board delay.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 55

Downloaded from Arrow.com.

 Electrical characteristics

3.9.4.2 Source synchronous mode AC timing (ONFI 2.x compatible)

Figure 28 to Figure 30 show the write and read timing of Source Synchronous mode.
NF19
NF18
.!.$?#%?"

NF23
NAND_CLE
NF25 NF26

NF24
NAND_ALE
NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

NAND_DQS
Output enable

NF20 NF20

NF21 NF21

NAND_DATA[7:0] CMD ADD

NAND_DATA[7:0]
Output enable

Figure 28. Source Synchronous mode command and address timing diagram

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
56 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

NF19
NF18
.!.$?#%?"

NF23 NF24
.!.$?#,% NF25 NF26

NF23 NF24
.!.$?!,% NF25 NF26

NAND_WE/RE_B

NF22

.!.$?#,+

NF27

.!.$?$13 NF27

.!.$?$13
Output enable

NF29 NF29

.!.$?$1;=

NF28 NF28

.!.$?$1;=
Output enable

Figure 29. Source Synchronous mode data write timing diagram

NF18
.!.$?#%?" NF19

NF23 NF24
.!.$?#,% NF25 NF26

NF23 NF24
NAND_ALE NF25 NF26

.!.$?7%2% NF25
NF25

NF22
NF26

.!.$?#,+

.!.$?$13

.!.$?$13
/UTPUTENABLE

.!.$?$!4!;=

.!.$?$!4!;=
/UTPUTENABLE

Figure 30. Source Synchronous mode data read timing diagram

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 57

Downloaded from Arrow.com.

 Electrical characteristics

.!.$?$13

NF30

.!.$?$!4!;= D0 D1 D2 D3

NF30 NF31 NF31

Figure 31. NAND_DQS/NAND_DQ read valid window

Table 50. Source Synchronous mode timing parameters1

Timing
T = GPMI Clock Cycle
ID Parameter Symbol Unit
Min. Max.

NF18 NAND_CE0_B access time tCE CE_DELAY  T - 0.79 [see note 2] ns

NF19 NAND_CE0_B hold time tCH 0.5  tCK - 0.63 [see note2] ns
NF20 Command/address NAND_DATAxx setup time tCAS 0.5  tCK - 0.05 ns
NF21 Command/address NAND_DATAxx hold time tCAH 0.5  tCK - 1.23 ns
NF22 clock period tCK — ns
NF23 preamble delay tPRE PRE_DELAY  T - 0.29 [see note2] ns
NF24 postamble delay tPOST POST_DELAY  T - 0.78 [see note2] ns
NF25 NAND_CLE and NAND_ALE setup time tCALS 0.5  tCK - 0.86 ns
NF26 NAND_CLE and NAND_ALE hold time tCALH 0.5  tCK - 0.37 ns
NF27 NAND_CLK to first NAND_DQS latching transition tDQSS T - 0.41 [see note2] ns
NF28 Data write setup — 0.25  tCK - 0.35
NF29 Data write hold — 0.25  tCK - 0.85
NF30 NAND_DQS/NAND_DQ read setup skew — — 2.06
NF31 NAND_DQS/NAND_DQ read hold skew — — 1.95
1 GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
2 T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).

For DDR Source Synchronous mode, Figure 31 shows the timing diagram of
NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns
(max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an
delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be
controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI
chapter of the i.MX 8M Nano Applications Processor Reference Manual [IMX8MNRM]). Generally, the
typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the
board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the
board delay.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
58 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.9.4.3 ONFI NV-DDR2 mode (ONFI 3.2 compatible)

3.9.4.3.1 Command and address timing

ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.
See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible), for details.

3.9.4.3.2 Read and write timing

ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 3.9.4.4, Toggle
mode AC Timing, for details.

3.9.4.4 Toggle mode AC Timing

3.9.4.4.1 Command and address timing

NOTE
Toggle mode command and address timing is the same as ONFI 1.0
compatible Asynchronous mode AC timing. See Section 3.9.4.1,
Asynchronous mode AC timing (ONFI 1.0 compatible), for details.

3.9.4.4.2 Read and write timing

Figure 32. Toggle mode data write timing

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 59

Downloaded from Arrow.com.

 Electrical characteristics

DEV?CLK

.!.$?#%X?"

.&

.!.$?#,%

.!.$?!,%

 T#+
.!.$?7%?" .& T#+

.!.$?2%?" .&

T#+
T#+
T#+

.!.$?$13

.!.$?$!4!;=

Figure 33. Toggle mode data read timing

Table 51. Toggle mode timing parameters

Timing
T = GPMI Clock Cycle
ID Parameter Symbol Unit
Min. Max.

NF1 NAND_CLE setup time tCLS (AS + DS)  T - 0.12 [see note1s,2]
NF2 NAND_CLE hold time tCLH DH  T - 0.72 [see note2]
NF3 NAND_CE0_B setup time tCS (AS + DS)  T - 0.58 [see notes,2]
NF4 NAND_CE0_B hold time tCH DH  T - 1 [see note2]
NF5 NAND_WE_B pulse width tWP DS  T [see note2]
NF6 NAND_ALE setup time tALS (AS + DS)  T - 0.49 [see notes,2]
NF7 NAND_ALE hold time tALH DH  T - 0.42 [see note2]
NF8 Command/address NAND_DATAxx setup time tCAS DS  T - 0.26 [see note2]
NF9 Command/address NAND_DATAxx hold time tCAH DH  T - 1.37 [see note2]
NF18 NAND_CEx_B access time tCE CE_DELAY  T [see notes3,2] — ns
NF22 clock period tCK — — ns
NF23 preamble delay tPRE PRE_DELAY  T [see notes4,2] — ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
60 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 51. Toggle mode timing parameters (continued)

Timing
T = GPMI Clock Cycle
ID Parameter Symbol Unit
Min. Max.

NF24 postamble delay tPOST POST_DELAY  T + 0.43 [see — ns

note2]
NF28 Data write setup tDS5 0.25  tCK - 0.32 — ns
NF29 Data write hold tDH 5
0.25  tCK - 0.79 — ns
6
NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ — 3.18 ns
NF31 NAND_DQS/NAND_DQ read hold skew tQHS6 — 3.27 ns
1
AS minimum value can be 0, while DS/DH minimum value is 1.
2
T = tCK (GPMI clock period) - 0.075 ns (half of maximum p-p jitter).
3
CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started
with enough time of ALE/CLE assertion to low level.
4 PRE_DELAY + 1  (AS + DS)
5
Shown in Figure 32.
6
Shown in Figure 33.

For DDR Toggle mode, Figure 31 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid
window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI
samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which
is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Nano
Applications Processor Reference Manual [IMX8MNRM]). Generally, the typical delay value is equal to
0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be
ignored, the delay value should be made larger to compensate the board delay.

3.9.5 I2C bus characteristics

The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is
designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now
NXP Semiconductors).

3.9.6 MIPI D-PHY timing parameters

MIPI D-PHY electrical specifications are compliance.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 61

Downloaded from Arrow.com.

 Electrical characteristics

Table 52. MIPI PHY worst power dissipation1

Power consume on Power consume on Power consume on Total power

MODE
VDD_MIPI_0P8 (mW) VDD_MIPI_1P2 (mW) VDD_MIPI_1P8 (mW) consume (mW)

M4 on 226.1 4.1 35.6 265.8

S4 on

M4 on 164.7 4.03 28.6 197.33

2.1 Gbps
S4 off

M4 off 63.02 0 15.8 78.82

S4 on

ULPS 4.26 0.0367 0.0584 4.36

1
M4 indicates MIPI DSI have 4 data lane enable (at least 1 clock lane enable). S4 indicates MIPI CSI have 4 data lane enable
(at least 1 clock lane enable).

3.9.7 PDM timing parameters

Figure 34 illustrates the input timing of the PDM.

PDM Clock

PDM Bitstream

ipg_clk_app

Pulse right

pre_channel_1

ipg_dee_clk

Channel 1

Channel 0

Figure 34. PDM input timing

PDM clock operative range is from 500 kHz to 6 MHz. Within range, only need to configure ipg_clk_app
rate and CLKDIV without I/O timing concerns.

3.9.8 Pulse width modulator (PWM) timing parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
62 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 35 depicts the timing of the PWM, and Table 53 lists the PWM timing parameters.

0 0

07-N?/54

Figure 35. PWM timing

Table 53. PWM output timing parameters

ID Parameter Min Max Unit

PWM Module Clock Frequency 0 66 (ipg_clk) MHz

P1 PWM output pulse width high 12 — ns

P2 PWM output pulse width low 12 — ns

3.9.9 FlexSPI timing parameters

Measurements are with a load of 15 pF and an input slew rate of 1 V/ns.

3.9.9.1 FlexSPI input/read timing

There are three sources for the internal sample clock for FlexSPI read data:
• Dummy read strobe generated by FlexSPI controller and looped back internally
(FlexSPIn_MCR0[RXCLKSRC] = 0x0)
• Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x1)
• Read strobe provided by memory device and input from DQS pad
(FlexSPIn_MCR0[RXCLKSRC] = 0x3)
The following sections describe input signal timing for each of these four internal sample clock sources.

3.9.9.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2

Table 54. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol Parameter Min. Max. Unit Notes

— [D:] Frequency of operation — 66 MHz —

1
F1 [D:] Setup time for incoming data 8.67 — ns
F2 [D:] Hold time for incoming data 0 — ns —
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 63

Downloaded from Arrow.com.

 Electrical characteristics

Table 55. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2

Symbol Parameter Min. Max. Unit Notes

— [D:] Frequency of operation — 133 MHz —

1
F1 [D:] Setup time for incoming data 1.5 — ns

F2 [D:] Hold time for incoming data 1 — ns —

1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.

FLEXSPI_SCLK
F1 F2 F1 F2
FLEXSPI_DATA[7:0]

Internal Sample Clock

Figure 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2

NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.

3.9.9.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge)
• A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising
edge
Table 56. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

Symbol Parameter Min. Max. Unit

— [D:] Frequency of operation — 166 MHz

F3 [D:] Time from SCK to data valid — — ns

F4 [D:] Time from SCK to DQS — — ns

— [D:] Time delta between TSCKD and -2 2 ns

TSCKDQS

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
64 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

FLEXSPI_SCLK
F3 F3

FLEXSPI_DATA[7:0]
F4 F4
FLEXSPI_DQS

Figure 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 57. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

Symbol Parameter Min. Max. Unit

— [D:] Frequency of operation — 166 MHz

F5 [D:] Time from SCK to data valid — — ns

F6 [D:] Time from SCK to DQS — — ns

— [D:] Time delta between TSCKD and -2 2 ns

TSCKDQS

FLEXSPI_SCLK
F5 F5 F5
FLEXSPI_DATA[7:0]
F6 F6 F6
FLEXSPI_DQS

Internal Sample Clock

Figure 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half-cycle delayed DQS falling edge.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 65

Downloaded from Arrow.com.

 Electrical characteristics

3.9.9.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2

Table 58. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol Parameter Min. Max. Unit Notes

— [D:] Frequency of operation — 33 MHz —

1
F1 [D:] Setup time for incoming data 8.67 — ns
F2 [D:] Hold time for incoming data 0 — ns —
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.

Table 59. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2

Symbol Parameter Min. Max. Unit Notes

— [D:] Frequency of operation — 66 MHz —

1
F1 [D:] Setup time for incoming data 1.5 — ns
F2 [D:] Hold time for incoming data 1 — ns —
1
The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be
decreased by up to 2ns.

SCLK
F1 F2 F1 F2

SIO[0:7]

Internal Sample Clocks

Figure 39. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2

3.9.9.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

Table 60. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1)

Symbol Parameter Min. Max. Unit

— [D:] Frequency of operation — 166 MHz

TSCKD [D:] Time from SCK to data valid — — ns

TSCKDQS [D:] Time from SCK to DQS — — ns

TSCKD - TSCKDQS [D:] Time delta between TSCKD and -0.6 0.6 ns
TSCKDQS

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
66 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

SCK
TSCKD
SIO[0:7]
TSCKDQS

DQS

Figure 40. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3

3.9.9.2 FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.

3.9.9.2.1 SDR mode

Table 61. FlexSPI output timing in SDR mode

Symbol Parameter Min. Max. Unit

— [D:] Frequency of operation1 — 166 MHz

TCK [D:] SCK clock period 6.02 — ns

TDSO [D:] Output data setup time 2 — ns

TDHO [D:] Output data hold time 2 — ns

TCSS [D:] Chip select output setup time 3 x TCK - 1 — ns

TCSH [D:] Chip select output hold time 3 x TCK - 1 — ns

1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the
FlexSPI SDR input timing specifications.

NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the
default values are shown above. See the i.MX 8M Nano Applications
Processor Reference Manual (IMX8MNRM) for more details.

SCK
TCSS TCK
TCSH
CS
TDVO TDVO

SIO[0:7]
TDHO TDHO

Figure 41. FlexSPI output timing in SDR mode

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 67

Downloaded from Arrow.com.

 Electrical characteristics

3.9.9.2.2 DDR mode

Table 62. FlexSPI output timing in DDR mode

Symbol Parameter Min. Max. Unit

— [D:] Frequency of operation1 — 166 MHz

TCK [D:] SCK clock period 6.02 — ns

TDSO [D:] Output data setup time — 0.6 ns

TDHO [D:] Output data hold time 0.6 — ns

TCSS [D:] Chip select output setup time 3 x TCK - 1.075 — ns

TCSH [D:] Chip select output hold time 3 x TCK - 1.075 — ns

1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the
FlexSPI SDR input timing specifications.

NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the
default values are shown above. See the i.MX 8M Nano Applications
Processor Reference Manual (IMX8MNRM) for more details.

SCK
TCSS TCK
TCSH
CS
TDVO TDVO

SIO[0:7]
TDHO TDHO

Figure 42. FlexSPI output timing in DDR mode

3.9.10 SAI/I2S switching specifications

This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes.
All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 63. Master mode SAI timing (50 MHz)1

Num Characteristic Min Max Unit

S1 SAI_MCLK cycle time 20 — ns

S2 SAI_MCLK pulse width high/low 40% 60% MCLK period

S3 SAI_BCLK cycle time 20 — ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
68 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Table 63. Master mode SAI timing (50 MHz)1 (continued)

Num Characteristic Min Max Unit

S4 SAI_BCLK pulse width high/low 40% 60% BCLK period

S5 SAI_BCLK to SAI_FS output valid — 2 ns

S6 SAI_BCLK to SAI_FS output invalid 0 — ns

S7 SAI_BCLK to SAI_TXD valid — 2 ns

S8 SAI_BCLK to SAI_TXD invalid 0 — ns

S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 2 — ns

S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns

1
To achieve 50 MHz for BCLK operation, clock must be set in feedback mode.

Table 64. Master mode SAI timing (25 MHz)

Num Characteristic Min Max Unit

S1 SAI_MCLK cycle time 40 — ns

S2 SAI_MCLK pulse width high/low 40% 60% MCLK period

S3 SAI_BCLK cycle time 40 — ns

S4 SAI_BCLK pulse width high/low 40% 60% BCLK period

S5 SAI_BCLK to SAI_FS output valid — 2 ns

S6 SAI_BCLK to SAI_FS output invalid 0 — ns

S7 SAI_BCLK to SAI_TXD valid — 2 ns

S8 SAI_BCLK to SAI_TXD invalid 0 — ns

S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 12 — ns

S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 69

Downloaded from Arrow.com.

 Electrical characteristics

Figure 43. SAI timing—Master modes

Table 65. Slave mode SAI timing (50 MHz)1

Num Characteristic Min Max Unit

S11 SAI_BCLK cycle time (input) 20 — ns

S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period

S13 SAI_FS input setup before SAI_BCLK 2 — ns

S14 SAI_FA input hold after SAI_BCLK 2 — ns

S17 SAI_RXD setup before SAI_BCLK 2 — ns

S18 SAI_RXD hold after SAI_BCLK 2 — ns

1 TX does not support 50 MHz operation in Slave mode.

Table 66. Slave mode SAI timing (25 MHz)

Num Characteristic Min Max Unit

S11 SAI_BCLK cycle time (input) 40 — ns

S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period

S13 SAI_FS input setup before SAI_BCLK 12 — ns

S14 SAI_FA input hold after SAI_BCLK 2 — ns

S15 SAI_BCLK to SAI_TXD/SAI_FS output valid — 7 ns

S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 — ns

S17 SAI_RXD setup before SAI_BCLK 12 — ns

S18 SAI_RXD hold after SAI_BCLK 2 — ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
70 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

Figure 44. SAI Timing — Slave Modes

3.9.11 SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 67 and Figure 45 and Figure 46 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Table 67. SPDIF timing parameters

Timing Parameter Range

Parameter Symbol Unit
Min Max

SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns

SPDIF_OUT output (Load = 50 pf)

• Skew — — 1.5 ns
• Transition rising — — 24.2
• Transition falling — — 31.3

SPDIF_OUT output (Load = 30 pf) 1.5

• Skew — — 13.6 ns
• Transition rising — — 18.0
• Transition falling — —

Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns

SPDIF_SR_CLK high period srckph 16.0 — ns

SPDIF_SR_CLK low period srckpl 16.0 — ns

Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns

SPDIF_ST_CLK high period stclkph 16.0 — ns

SPDIF_ST_CLK low period stclkpl 16.0 — ns

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 71

Downloaded from Arrow.com.

 Electrical characteristics

srckp

SPDIF_SR_CLK srckpl srckph

VM VM
(Output)

Figure 45. SPDIF_SR_CLK timing diagram

stclkp

SPDIF_ST_CLK stclkpl stclkph

VM VM
(Input)

Figure 46. SPDIF_ST_CLK timing diagram

3.9.12 UART I/O configuration and timing parameters

3.9.12.1 UART RS-232 I/O configuration in different modes

The i.MX 8M Nano UART interfaces can serve both as DTE or DCE device. This can be configured by
the DCEDTE control bit (default 0—DCE mode). Table 68 shows the UART I/O configuration based on
the enabled mode.
Table 68. UART I/O configuration vs. mode

DTE Mode DCE Mode

Port
Direction Description Direction Description

UARTx_RTS_B Output UARTx_RTS_B from DTE to DCE Input UARTx_RTS_B from DTE to DCE

UARTx_CTS_B Input UARTx_CTS_B from DCE to DTE Output UARTx_CTS_B from DCE to DTE

UARTx_TX_ DATA Input Serial data from DCE to DTE Output Serial data from DCE to DTE

UARTx_RX_DATA Output Serial data from DTE to DCE Input Serial data from DTE to DCE

3.9.12.2 UART RS-232 Serial mode timing

This section describes the electrical information of the UART module in the RS-232 mode.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
72 NXP Semiconductors

Downloaded from Arrow.com.

 Electrical characteristics

3.9.12.2.1 UART transmitter

Figure 47 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit
format. Table 69 lists the UART RS-232 Serial mode transmit timing characteristics.
Possible
UA1 UA1 Parity
Bit
Next
Start Start
UARTx_TX_DATA Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP Bit
(output) BIT

UA1 UA1

Figure 47. UART RS-232 Serial mode transmit timing diagram

Table 69. RS-232 Serial mode transmit timing parameters

ID Parameter Symbol Min Max Unit

UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 - Tref_clk2 1/Fbaud_rate + Tref_clk —

1
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

3.9.12.2.2 UART receiver

Figure 48 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 70 lists
Serial mode receive timing characteristics.
Possible
Parity
UA2 UA2
Bit
Next
Start Start
UARTx_RX_DATA Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP Bit
(output) BIT

UA2 UA2

Figure 48. UART RS-232 Serial mode receive timing diagram

Table 70. RS-232 Serial mode receive timing parameters

ID Parameter Symbol Min Max Unit

UA2 Receive Bit Time1 tRbit 1/Fbaud_rate2 - 1/(16 x 1/Fbaud_rate + 1/(16 x —

Fbaud_rate) Fbaud_rate)
1
The UART receiver can tolerate 1/(16 x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16 x Fbaud_rate).
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 73

Downloaded from Arrow.com.

 Electrical characteristics

3.9.13 USB PHY parameters

This section describes the USB-OTG PHY parameters.

3.9.13.1 Pad/Package/Board connections

The USB1_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link.
The USB1_VBUS pin must be isolated by an external 30 K1% precision resistor.
The USB 2.0 PHY uses USB1_TXRTUNE and an external resistor to calibrate the USB1_DP/DN 45 
source impedance. The external resistor value is 200  1% precision on USB1_TXRTUNE pad to ground.

3.9.13.2 USB PHY worst power consumption

Table 71 shows the USB 2.0 PHY worst power dissipation.
Table 71. USB 2.0 PHY worst power dissipation

Mode VDD_USB_0P8 VDD_USB_3P3 VDD_USB_1P8 Total Power

HS TX 8.286 4.63 23.409 70.448

FS TX 6.767 12.52 5.968 63.22

LS TX 7.001 mA 13.58 mA 6.224 mA 67.779 mW

Suspend 0.752 0.164 0.106 1.465

Sleep 0.761 0.163 0.106 1.472

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
74 NXP Semiconductors

Downloaded from Arrow.com.

 Boot mode configuration

4 Boot mode configuration

This section provides information on Boot mode configuration pins allocation and boot devices interfaces
allocation.

4.1 Boot mode configuration pins

Table 72 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,
Fusemap, and eFuse” chapter in the i.MX 8M Nano Applications Processor Reference Manual
(IMX8MNRM).

Table 72. Fuses and associated pins used for boot

Interface IP instance Allocated pads during boot Comment

BOOT_MODE0 Input ccmsrcgpcmix.BOOT_MODE[0] Boot mode selection

BOOT_MODE1 Input ccmsrcgpcmix.BOOT_MODE[1]

BOOT_MODE2 Input ccmsrcgpcmix.BOOT_MODE[2]

BOOT_MODE3 Input ccmsrcgpcmix.BOOT_MODE[3]

4.2 Boot device interface allocation

Table 73 lists the interfaces that can be used by the boot process in accordance with the specific Boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 73. Interface allocation during boot

Interface IP Instance Allocated Pads During Boot Comment

SPI ECSPI-1 ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO, The chip-select pin used depends
ECSPI1_SS0 on the fuse “CS select (SPI only)“.
SPI ECSPI-2 ECSPI2_SCLK, ECSPI2_MOSI, ECSPI2_MISO, The chip-select pin used depends
ECSPI2_SS0 on the fuse “CS select (SPI only)“.

SPI ECSPI-3 UART1_RXD, UART1_TXD, UART2_RXD, The chip-select pin used depends
UART2_TXD on the fuse “CS select (SPI only)“.

NAND Flash GPMI NAND_ALE, NAND_CE0_B, NAND_CLE, 8-bit, only CS0 is supported.
NAND_DATA00,NAND_DATA01,NAND_DATA02,
NAND_DATA03,NAND_DATA04,NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B, NAND_READY_B, NAND_WE_B,
NAND_WP_B

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 75

Downloaded from Arrow.com.

 Boot mode configuration

Table 73. Interface allocation during boot (continued)

Interface IP Instance Allocated Pads During Boot Comment

SD/MMC USDHC-1 GPIO1_IO03, GPIO1_IO06, GPIO1_IO07, 1, 4, or 8-bit

SD1_RESET_B, SD1_CLK, SD1_CMD,
SD1_STROBE, SD1_DATA0, SD1_DATA1,
SD1_DATA2, SD1_DATA3, SD1_DATA4,
SD1_DATA5, SD1_DATA6, SD1_DATA7

SD/MMC USDHC-2 GPIO1_IO04, GPIO1_IO08, GPIO1_IO07, 1 or 4-bit

SD2_RESET_B, SD2_WP, SD2_CLK, SD2_CMD,
SD2_DATA0, SD2_DATA1, SD2_DATA2,
SD2_DATA3

SD/MMC USDHC-3 NAND_CE1_B, NAND_CE2_B, NAND_CE3_B, 1, 4, or 8-bit

NAND_CLE, NAND_DATA02, NAND_DATA03,
NAND_DATA04,NAND_DATA05,NAND_DATA06,
NAND_DATA07, NAND_RE_B, NAND_READY_B,
NAND_WE_B, NAND_WP_B
FlexSPI FlexSPI NAND_ALE, NAND_CE0_B, NAND_CE1_B, For FlexSPI flash
NAND_CE2_B, NAND_CE3_B, NAND_CLE,
NAND_DATA00,NAND_DATA01,NAND_DATA02,
NAND_DATA03,NAND_DATA04,NAND_DATA05,
NAND_DATA06, NAND_DATA07, NAND_DQS,
NAND_RE_B

USB USB_OTG PHY Dedicated USB pins —

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
76 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

5 Package information and contact assignments

This section includes the contact assignment information and mechanical package drawing.

5.1 14 x 14 mm package information

5.1.1 14 x 14 mm, 0.5 mm pitch, ball matrix

Figure 49 shows the top, bottom, and side views of the 14 × 14 mm FCBGA package.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 77

Downloaded from Arrow.com.

 Package information and contact assignments

Figure 49. 14 X 14 MM BGA, case x package top, bottom, and side views

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
78 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

5.1.2 14 x 14 mm supplies contact assignments and functional contact

assignments
Table 74 shows supplies contact assignments for the 14 x 14 mm package.

Table 74. i.MX 8M Nano 14 x 14 mm supplies contact assignments

Supply Rail Name Ball(s) Position(s) Remark

NVCC_CLK M19 Supply for CLK interface

NVCC_DRAM P7, K8, N8, R8, V8, K9, L9, M9, N9, R9, T9, U9, V9 Supply for DRAM interface

NVCC_ECSPI H10 Supply for ECSPI interface

NVCC_ENET W22 Supply for ENET interface

NVCC_GPIO1 W12 Supply for GPIO1 interface

NVCC_I2C J11 Supply for I2C interface

NVCC_JTAG L19 Supply for JTAG interface

NVCC_NAND U19 Supply for NAND interface

NVCC_SAI2 V19 Supply for SAI interface

NVCC_SAI3 Y10 Supply for SAI interface

NVCC_SAI5 W17 Supply for SAI interface

NVCC_SD1 V20 Supply for SD interface

NVCC_SD2 V22 Supply for SD interface

NVCC_SNVS_1P8 J22 Supply for SNVS interface

NVCC_UART J12 Supply for UART interface

PVCC0_1P8 AB13 Digital IO pre-drive

PVCC1_1P8 T19 Digital IO pre-drive

PVCC2_1P8 J13 Digital IO pre-drive

VDD_24M_XTAL_1P8 N19 Supply for XTAL

VDD_ANA_0P8 L17, N17 Supply for Analog logic

VDD_ANA0_1P8 AA14, Y15 Supply for Analog logic

VDD_ANA1_1P8 P19, N20 Supply for Analog logic

VDD_ARM R13, T13, U13, V13, W13, T14, W14, R15, T15, U15, V15, Supply for ARM
W15, V16, W16

VDD_ARM_PLL_0P8 P16 Supply for ARM PLL

VDD_ARM_PLL_1P8 R19 Supply for ARM PLL

VDD_DRAM J10, L10, N10, R10, U10, W10 Supply for DRAM module

VDD_DRAM_PLL_0P8 P9 Supply for DRAM PLL

VDD_DRAM_PLL_1P8 P5 Supply for DRAM PLL

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 79

Downloaded from Arrow.com.

 Package information and contact assignments

Table 74. i.MX 8M Nano 14 x 14 mm supplies contact assignments (continued)

VDD_GPU R11, U11, W11, P12, V12 Supply for GPU

VDD_MIPI_0P8 J14 Supply for MIPI PHY

VDD_MIPI_1P2 J15 Supply for MIPI PHY

VDD_MIPI_1P8 H13 Supply for MIPI PHY

VDD_SNVS_0P8 K22 Supply for SNVS logic

VDD_SOC N13, K15, L15, M15, N15, K16, R17, U17, L18, N18, R18, Supply for SOC logic
U18

VDD_USB_0P8 J17 Supply for USB PHY

VDD_USB_1P8 H15 Supply for USB PHY

VDD_USB_3P3 K19 Supply for USB PHY

VSS A1, AG1, C2, H2, Y2, AE2, B3, E3, F3, J3, K3, N3, P3, R3, —
V3, W3, AB3, AC3, AF3, C5, AE5, C6, AE6, G7, J7, K7, N7,
R7, V7, W7, AA7, C9, G9, AA9, AE9, C10, G10, AA10, AE10,
L12, M12, N12, R12, T12, U12, C13, G13, P13, Y13, AA13,
AE13, C14, AE14, C15, G15, P15, AA15, AE15, L16, M16,
N16, R16, T16, U16, C18, G18, H18, Y18, AA18, AE18, C19,
G19, AA19, AE19, K20, R20, G21, J21, K21, N21, P21, R21,
V21, W21, AA21, C22, AE22, C23, AE23, E25, F25, J25,
K25, N25, P25, R25, V25, W25, AB25, AC25, B26, A27,
AG27

Table 75 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

24M_XTALI B27 NVCC_CLK ANALOG — — Input

24M_XTALO C26 NVCC_CLK ANALOG — — Output

BOOT_MODE0 G26 NVCC_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[0] Input with PD

BOOT_MODE1 G27 NVCC_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[1] Input with PD

BOOT_MODE2 C27 NVCC_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[2] Input with PD

BOOT_MODE3 D26 NVCC_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[3] Input with PD

CLKIN1 H27 NVCC_CLK GPIO — — Input without

PU/PD
CLKIN2 J27 NVCC_CLK GPIO — — Input without
PU/PD

CLKOUT1 H26 NVCC_CLK GPIO — — Output low

without
PU/PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
80 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

CLKOUT2 J26 NVCC_CLK GPIO — — Output low

without
PU/PD
DRAM_AC00 F4 NVCC_DRAM DDR — — Output low

DRAM_AC01 F5 NVCC_DRAM DDR — — Output low

DRAM_AC02 K4 NVCC_DRAM DDR — — Input

DRAM_AC03 J4 NVCC_DRAM DDR — — Input

DRAM_AC04 L2 NVCC_DRAM DDR — — Input

DRAM_AC05 L1 NVCC_DRAM DDR — — Input

DRAM_AC06 F6 NVCC_DRAM DDR — — Input

DRAM_AC07 J5 NVCC_DRAM DDR — — Input

DRAM_AC08 J6 NVCC_DRAM DDR — — Input

DRAM_AC09 K6 NVCC_DRAM DDR — — Input

DRAM_AC10 E4 NVCC_DRAM DDR — — Input

DRAM_AC11 D5 NVCC_DRAM DDR — — Input

DRAM_AC12 N4 NVCC_DRAM DDR — — Input

DRAM_AC13 N5 NVCC_DRAM DDR — — Input

DRAM_AC14 K5 NVCC_DRAM DDR — — Input

DRAM_AC15 N6 NVCC_DRAM DDR — — Input

DRAM_AC16 M1 NVCC_DRAM DDR — — Input

DRAM_AC17 M2 NVCC_DRAM DDR — — Input

DRAM_AC19 N2 NVCC_DRAM DDR — — Input

DRAM_AC20 AB4 NVCC_DRAM DDR — — Output low

DRAM_AC21 AB5 NVCC_DRAM DDR — — Output low

DRAM_AC22 W4 NVCC_DRAM DDR — — Input

DRAM_AC23 V4 NVCC_DRAM DDR — — Input

DRAM_AC24 U2 NVCC_DRAM DDR — — Input

DRAM_AC25 U1 NVCC_DRAM DDR — — Input

DRAM_AC26 N1 NVCC_DRAM DDR — — Input

DRAM_AC27 R6 NVCC_DRAM DDR — — Input

DRAM_AC28 W6 NVCC_DRAM DDR — — Input

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 81

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

DRAM_AC29 V6 NVCC_DRAM DDR — — Input

DRAM_AC30 AC4 NVCC_DRAM DDR — — Input

DRAM_AC31 AD5 NVCC_DRAM DDR — — Input

DRAM_AC32 R4 NVCC_DRAM DDR — — Input

DRAM_AC33 R5 NVCC_DRAM DDR — — Input

DRAM_AC34 T1 NVCC_DRAM DDR — — Input

DRAM_AC35 T2 NVCC_DRAM DDR — — Input

DRAM_AC36 V5 NVCC_DRAM DDR — — Input

DRAM_AC37 W5 NVCC_DRAM DDR — — Input

DRAM_AC38 AB6 NVCC_DRAM DDR — — Input

DRAM_ALERT_N R2 NVCC_DRAM DDR — — Input

DRAM_DM0 A4 NVCC_DRAM DDR — — Input

DRAM_DM1 F1 NVCC_DRAM DDR — — Input

DRAM_DQ00 A5 NVCC_DRAM DDR — — Input

DRAM_DQ01 B5 NVCC_DRAM DDR — — Input

DRAM_DQ02 D2 NVCC_DRAM DDR — — Input

DRAM_DQ03 D1 NVCC_DRAM DDR — — Input

DRAM_DQ04 C1 NVCC_DRAM DDR — — Input

DRAM_DQ05 B1 NVCC_DRAM DDR — — Input

DRAM_DQ06 A3 NVCC_DRAM DDR — — Input

DRAM_DQ07 B4 NVCC_DRAM DDR — — Input

DRAM_DQ08 F2 NVCC_DRAM DDR — — Input

DRAM_DQ09 G2 NVCC_DRAM DDR — — Input

DRAM_DQ10 J1 NVCC_DRAM DDR — — Input

DRAM_DQ11 J2 NVCC_DRAM DDR — — Input

DRAM_DQ12 K2 NVCC_DRAM DDR — — Input

DRAM_DQ13 K1 NVCC_DRAM DDR — — Input

DRAM_DQ14 E1 NVCC_DRAM DDR — — Input

DRAM_DQ15 E2 NVCC_DRAM DDR — — Input

DRAM_DQS0_N B2 NVCC_DRAM — — — Input

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
82 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

DRAM_DQS0_P A2 NVCC_DRAM DDRCLK — — Input

DRAM_DQS1_N H1 NVCC_DRAM — — — Input

DRAM_DQS1_P G1 NVCC_DRAM DDRCLK — — Input

DRAM_RESET_N R1 NVCC_DRAM DDR — — Output low

DRAM_VREF P1 NVCC_DRAM DDR — — —

DRAM_ZN P2 NVCC_DRAM DDR — — —

ECSPI1_MISO A7 NVCC_ECSPI GPIO ALT5 GPIO5.IO[8] Input with PD

ECSPI1_MOSI B7 NVCC_ECSPI GPIO ALT5 GPIO5.IO[7] Input with PD

ECSPI1_SCLK D6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[6] Input with PD

ECSPI1_SS0 B6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[9] Input with PD

ECSPI2_MISO A8 NVCC_ECSPI GPIO ALT5 GPIO5.IO[12] Input with PD

ECSPI2_MOSI B8 NVCC_ECSPI GPIO ALT5 GPIO5.IO[11] Input with PD

ECSPI2_SCLK E6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[10] Input with PD

ECSPI2_SS0 A6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[13] Input with PD

ENET_MDC AC27 NVCC_ENET GPIO ALT5 GPIO1.IO[16] Input with PD

ENET_MDIO AB27 NVCC_ENET GPIO ALT5 GPIO1.IO[17] Input with PD

ENET_RD0 AE27 NVCC_ENET GPIO ALT5 GPIO1.IO[26] Input with PD

ENET_RD1 AD27 NVCC_ENET GPIO ALT5 GPIO1.IO[27] Input with PD

ENET_RD2 AD26 NVCC_ENET GPIO ALT5 GPIO1.IO[28] Input with PD

ENET_RD3 AC26 NVCC_ENET GPIO ALT5 GPIO1.IO[29] Input with PD

ENET_RXC AE26 NVCC_ENET GPIO ALT5 GPIO1.IO[25] Input with PD

ENET_RX_CTL AF27 NVCC_ENET GPIO ALT5 GPIO1.IO[24] Input with PD

ENET_TD0 AG26 NVCC_ENET GPIO ALT5 GPIO1.IO[21] Input with PD

ENET_TD1 AF26 NVCC_ENET GPIO ALT5 GPIO1.IO[20] Input with PD

ENET_TD2 AG25 NVCC_ENET GPIO ALT5 GPIO1.IO[19] Input with PD

ENET_TD3 AF25 NVCC_ENET GPIO ALT5 GPIO1.IO[18] Input with PD

ENET_TXC AG24 NVCC_ENET GPIO ALT5 GPIO1.IO[23] Input with PD

ENET_TX_CTL AF24 NVCC_ENET GPIO ALT5 GPIO1.IO[22] Input with PD

GPIO1_IO00 AG14 NVCC_GPIO1 GPIO ALT6 GPIO1.IO[0] Input with PD

1
GPIO1_IO01 AF14 NVCC_GPIO1 GPIO ALT6 GPIO1.IO[1]

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 83

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

GPIO1_IO02 AG13 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[2] Input with PU

GPIO1_IO03 AF13 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[3] Input with PD

GPIO1_IO04 AG12 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[4] Input with PD

1
GPIO1_IO05 AF12 NVCC_GPIO1 GPIO ALT6 GPIO1.IO[5]

GPIO1_IO06 AG11 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[6] Input with PD

GPIO1_IO07 AF11 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[7] Input with PD

GPIO1_IO08 AG10 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[8] Input with PD

GPIO1_IO09 AF10 NVCC_GPIO1 GPIO ALT1 GPIO1.IO[9] Input with PD

GPIO1_IO10 AD10 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[10] Input with PD

GPIO1_IO11 AC10 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[11] Input with PD

GPIO1_IO12 AB10 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[12] Input with PD

GPIO1_IO13 AD9 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[13] Input with PD

GPIO1_IO14 AC9 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[14] Input with PD

GPIO1_IO15 AB9 NVCC_GPIO1 GPIO ALT0 GPIO1.IO[15] Input with PD

I2C1_SCL E9 NVCC_I2C GPIO ALT5 GPIO5.IO[14] Input with PD

I2C1_SDA F9 NVCC_I2C GPIO ALT5 GPIO5.IO[15] Input with PD

I2C2_SCL D10 NVCC_I2C GPIO ALT5 GPIO5.IO[16] Input with PD

I2C2_SDA D9 NVCC_I2C GPIO ALT5 GPIO5.IO[17] Input with PD

I2C3_SCL E10 NVCC_I2C GPIO ALT5 GPIO5.IO[18] Input with PD

I2C3_SDA F10 NVCC_I2C GPIO ALT5 GPIO5.IO[19] Input with PD

I2C4_SCL D13 NVCC_I2C GPIO ALT5 GPIO5.IO[20] Input with PD

I2C4_SDA E13 NVCC_I2C GPIO ALT5 GPIO5.IO[21] Input with PD

JTAG_MOD D27 NVCC_JTAG GPIO ALT0 cjtag_wrapper.MOD Input with PD

JTAG_TCK F26 NVCC_JTAG GPIO ALT0 cjtag_wrapper.TCK Input with PU

JTAG_TDI E27 NVCC_JTAG GPIO ALT0 cjtag_wrapper.TDI Input with PU

JTAG_TDO E26 NVCC_JTAG GPIO ALT0 cjtag_wrapper.TDO Input with PU

JTAG_TMS2 F27 NVCC_JTAG GPIO ALT0 cjtag_wrapper.TMS Input with PU

MIPI_CSI_CLK_N A16 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_CLK_P B16 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D0_N A14 VDD_MIPI_1P8 PHY — — Input

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
84 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

MIPI_CSI_D0_P B14 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D1_N A15 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D1_P B15 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D2_N A17 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D2_P B17 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D3_N A18 VDD_MIPI_1P8 PHY — — Input

MIPI_CSI_D3_P B18 VDD_MIPI_1P8 PHY — — Input

MIPI_DSI_CLK_N A11 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_CLK_P B11 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D0_N A9 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D0_P B9 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D1_N A10 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D1_P B10 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D2_N A12 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D2_P B12 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D3_N A13 VDD_MIPI_1P8 PHY — — Output low

MIPI_DSI_D3_P B13 VDD_MIPI_1P8 PHY — — Output low

MIPI_VREG_CAP D15 0.35 - 0.45 V PHY — — Output

NAND_ALE N22 NVCC_NAND GPIO ALT5 GPIO3.IO[0] Input with PD

NAND_CE0_B N24 NVCC_NAND GPIO ALT5 GPIO3.IO[1] Input with PD

NAND_CE1_B P27 NVCC_NAND GPIO ALT5 GPIO3.IO[2] Input with PD

NAND_CE2_B M27 NVCC_NAND GPIO ALT5 GPIO3.IO[3] Input with PD

NAND_CE3_B L27 NVCC_NAND GPIO ALT5 GPIO3.IO[4] Input with PD

NAND_CLE K27 NVCC_NAND GPIO ALT5 GPIO3.IO[5] Input with PD

NAND_DATA00 P23 NVCC_NAND GPIO ALT5 GPIO3.IO[6] Input with PD

NAND_DATA01 K24 NVCC_NAND GPIO ALT5 GPIO3.IO[7] Input with PD

NAND_DATA02 K23 NVCC_NAND GPIO ALT5 GPIO3.IO[8] Input with PD

NAND_DATA03 N23 NVCC_NAND GPIO ALT5 GPIO3.IO[9] Input with PD

NAND_DATA04 M26 NVCC_NAND GPIO ALT5 GPIO3.IO[10] Input with PD

NAND_DATA05 L26 NVCC_NAND GPIO ALT5 GPIO3.IO[11] Input with PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 85

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

NAND_DATA06 K26 NVCC_NAND GPIO ALT5 GPIO3.IO[12] Input with PD

NAND_DATA07 N26 NVCC_NAND GPIO ALT5 GPIO3.IO[13] Input with PD

NAND_DQS R22 NVCC_NAND GPIO ALT5 GPIO3.IO[14] Input with PD

NAND_RE_B N27 NVCC_NAND GPIO ALT5 GPIO3.IO[15] Input with PD

NAND_READY_B P26 NVCC_NAND GPIO ALT5 GPIO3.IO[16] Input with PD

NAND_WE_B R26 NVCC_NAND GPIO ALT5 GPIO3.IO[17] Input with PD

NAND_WP_B R27 NVCC_NAND GPIO ALT5 GPIO3.IO[18] Input with PD

ONOFF A25 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.ONOFF Input without

PU/PD

PMIC_ON_REQ A24 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.PMIC_ON_REQ Open-drain

output high
with PU
PMIC_STBY_REQ E24 NVCC_SNVS_1P8 GPIO ALT0 ccmsrcgpcmix.PMIC_STBY_RE Output low
Q with PD

POR_B B24 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.POR_B Input without

PU/PD
RTC_XTALI A26 NVCC_SNVS_1P8 ANALOG ALT0 snvsmix.RTC Input

RTC_XTALO B25 NVCC_SNVS_1P8 ANALOG — — Output,

inverted of
RTC_XTALI

RTC_RESET_B F24 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.RTC_POR_B Input without

PU/PD
SAI2_MCLK AD19 NVCC_SAI2 GPIO ALT5 GPIO4.IO[27] Input with PD

SAI2_RXC AB22 NVCC_SAI2 GPIO ALT5 GPIO4.IO[22] Input with PD

SAI2_RXD0 AC24 NVCC_SAI2 GPIO ALT5 GPIO4.IO[23] Input with PD

SAI2_RXFS AC19 NVCC_SAI2 GPIO ALT5 GPIO4.IO[21] Input with PD

SAI2_TXC AD22 NVCC_SAI2 GPIO ALT5 GPIO4.IO[25] Input with PD

SAI2_TXD0 AC22 NVCC_SAI2 GPIO ALT5 GPIO4.IO[26] Input with PD

SAI2_TXFS AD23 NVCC_SAI2 GPIO ALT5 GPIO4.IO[24] Input with PD

SAI3_MCLK AD6 NVCC_SAI3 GPIO ALT5 GPIO5.IO[2] Input with PD

SAI3_RXC AG7 NVCC_SAI3 GPIO ALT5 GPIO4.IO[29] Input with PD

SAI3_RXD AF7 NVCC_SAI3 GPIO ALT5 GPIO4.IO[30] Input with PD

SAI3_RXFS AG8 NVCC_SAI3 GPIO ALT5 GPIO4.IO[28] Input with PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
86 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

SAI3_TXC AG6 NVCC_SAI3 GPIO ALT5 GPIO5.IO[0] Input with PD

SAI3_TXD AF6 NVCC_SAI3 GPIO ALT5 GPIO5.IO[1] Input with PD

SAI3_TXFS AC6 NVCC_SAI3 GPIO ALT5 GPIO4.IO[31] Input with PD

3
SAI5_MCLK AD15 NVCC_SAI5 GPIO ALT5 GPIO3.IO[25]

SAI5_RXC AC15 NVCC_SAI5 GPIO ALT5 GPIO3.IO[20] Input with PD

SAI5_RXD0 AD18 NVCC_SAI5 GPIO ALT5 GPIO3.IO[21] Input with PD

SAI5_RXD1 AC14 NVCC_SAI5 GPIO ALT5 GPIO3.IO[22] Input with PD

SAI5_RXD2 AD13 NVCC_SAI5 GPIO ALT5 GPIO3.IO[23] Input with PD

SAI5_RXD3 AC13 NVCC_SAI5 GPIO ALT5 GPIO3.IO[24] Input with PD

SAI5_RXFS AB15 NVCC_SAI5 GPIO ALT5 GPIO3.IO[19] Input with PD

SD1_CLK V26 NVCC_SD1 GPIO ALT5 GPIO2.IO[0] Input with PD

SD1_CMD V27 NVCC_SD1 GPIO ALT5 GPIO2.IO[1] Input with PD

SD1_DATA0 Y27 NVCC_SD1 GPIO ALT5 GPIO2.IO[2] Input with PD

SD1_DATA1 Y26 NVCC_SD1 GPIO ALT5 GPIO2.IO[3] Input with PD

SD1_DATA2 T27 NVCC_SD1 GPIO ALT5 GPIO2.IO[4] Input with PD

SD1_DATA3 T26 NVCC_SD1 GPIO ALT5 GPIO2.IO[5] Input with PD

SD1_DATA4 U27 NVCC_SD1 GPIO ALT5 GPIO2.IO[6] Input with PD

SD1_DATA5 U26 NVCC_SD1 GPIO ALT5 GPIO2.IO[7] Input with PD

SD1_DATA6 W27 NVCC_SD1 GPIO ALT5 GPIO2.IO[8] Input with PD

SD1_DATA7 W26 NVCC_SD1 GPIO ALT5 GPIO2.IO[9] Input with PD

SD1_RESET_B R23 NVCC_SD1 GPIO ALT5 GPIO2.IO[10] Input with PD

SD1_STROBE R24 NVCC_SD1 GPIO ALT5 GPIO2.IO[11] Input with PD

SD2_CD_B AA26 NVCC_SD2 GPIO ALT5 GPIO2.IO[12] Input with PD

SD2_CLK W23 NVCC_SD2 GPIO ALT5 GPIO2.IO[13] Input with PD

SD2_CMD W24 NVCC_SD2 GPIO ALT5 GPIO2.IO[14] Input with PD

SD2_DATA0 AB23 NVCC_SD2 GPIO ALT5 GPIO2.IO[15] Input with PD

SD2_DATA1 AB24 NVCC_SD2 GPIO ALT5 GPIO2.IO[16] Input with PD

SD2_DATA2 V24 NVCC_SD2 GPIO ALT5 GPIO2.IO[17] Input with PD

SD2_DATA3 V23 NVCC_SD2 GPIO ALT5 GPIO2.IO[18] Input with PD

SD2_RESET_B AB26 NVCC_SD2 GPIO ALT5 GPIO2.IO[19] Input with PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 87

Downloaded from Arrow.com.

 Package information and contact assignments

Table 75. i.MX 8M Nano 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

SD2_WP AA27 NVCC_SD2 GPIO ALT5 GPIO2.IO[20] Input with PD

SPDIF_EXT_CLK AF8 NVCC_SAI3 GPIO ALT5 GPIO5.IO[5] Input with PD

SPDIF_RX AG9 NVCC_SAI3 GPIO ALT5 GPIO5.IO[4] Input with PD

SPDIF_TX AF9 NVCC_SAI3 GPIO ALT5 GPIO5.IO[3] Input with PD

TSENSOR_TEST_ J23 VDD_ANA1_1P8 ANALOG — — Output low

OUT

TSENSOR_RES_E J24 VDD_ANA1_1P8 ANALOG — — —

XT
UART1_RXD E14 NVCC_UART GPIO ALT5 GPIO5.IO[22] Input with PD

UART1_TXD F13 NVCC_UART GPIO ALT5 GPIO5.IO[23] Input with PD

UART2_RXD F15 NVCC_UART GPIO ALT5 GPIO5.IO[24] Input with PD

UART2_TXD E15 NVCC_UART GPIO ALT5 GPIO5.IO[25] Input with PD

UART3_RXD E18 NVCC_UART GPIO ALT5 GPIO5.IO[26] Input with PD

UART3_TXD D18 NVCC_UART GPIO ALT5 GPIO5.IO[27] Input with PD

UART4_RXD F19 NVCC_UART GPIO ALT5 GPIO5.IO[28] Input with PD

UART4_TXD F18 NVCC_UART GPIO ALT5 GPIO5.IO[29] Input with PD

USB1_DN A22 VDD_USB_3P3 PHY — — Input

USB1_DP B22 VDD_USB_3P3 PHY — — Input

USB1_ID D22 VDD_USB_1P8 PHY — — Input

USB1_TXRTUNE E19 VDD_USB_1P8 PHY — — —

USB1_VBUS F22 VDD_USB_3P3 PHY — — —

1
During reset: output high without PU/PD; After reset: input with PU
2
Mandatory requirement: JTAG_TMS pin must be connected with a 50 ohm serial resistor near the component.
3 During reset: input without PU/PD; After reset: input with PD

5.1.3 i.MX 8M Nano 14 x 14 mm 0.5 mm pitch ball map

Table 76 shows the i.MX 8M Nano 14 x 14 mm 0.5 mm pitch ball map.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
88 NXP Semiconductors

Downloaded from Arrow.com.

 G F E D C B A

1
DRAM_DQS1_P DRAM_DM1 DRAM_DQ14 DRAM_DQ03 DRAM_DQ04 DRAM_DQ05 VSS
2

Downloaded from Arrow.com.

DRAM_DQ09 DRAM_DQ08 DRAM_DQ15 DRAM_DQ02 VSS DRAM_DQS0_N DRAM_DQS0_P 3

VSS VSS VSS DRAM_DQ06

4

NXP Semiconductors
DRAM_AC00 DRAM_AC10 DRAM_DQ07 DRAM_DM0
5

DRAM_AC01 DRAM_AC11 VSS DRAM_DQ01 DRAM_DQ00

6

DRAM_AC06 ECSPI2_SCLK ECSPI1_SCLK VSS ECSPI1_SS0 ECSPI2_SS0

7

VSS ECSPI1_MOSI ECSPI1_MISO

8

ECSPI2_MOSI ECSPI2_MISO
9

VSS I2C1_SDA I2C1_SCL I2C2_SDA VSS MIPI_DSI_D0_P MIPI_DSI_D0_N

VSS I2C3_SDA I2C3_SCL I2C2_SCL VSS MIPI_DSI_D1_P MIPI_DSI_D1_N
MIPI_DSI_CLK_P MIPI_DSI_CLK_N

MIPI_DSI_D2_P MIPI_DSI_D2_N
VSS UART1_TXD I2C4_SDA I2C4_SCL VSS MIPI_DSI_D3_P MIPI_DSI_D3_N
UART1_RXD VSS MIPI_CSI_D0_P MIPI_CSI_D0_N

VSS UART2_RXD UART2_TXD MIPI_VREG_CAP VSS MIPI_CSI_D1_P MIPI_CSI_D1_N

MIPI_CSI_CLK_P MIPI_CSI_CLK_N
MIPI_CSI_D2_P MIPI_CSI_D2_N

VSS UART4_TXD UART3_RXD UART3_TXD VSS MIPI_CSI_D3_P MIPI_CSI_D3_N

Table 76. 14 x 14 mm, 0.5 mm pitch ball map

VSS UART4_RXD USB1_TXRTUNE VSS

VSS
USB1_VBUS USB1_ID VSS USB1_DP USB1_DN

VSS

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
RTC_RESET_B PMIC_STBY_REQ POR_B PMIC_ON_REQ

VSS VSS RTC_XTALO ONOFF

BOOT_MODE0 JTAG_TCK JTAG_TDO BOOT_MODE3 24M_XTALO VSS RTC_XTALI
BOOT_MODE1 JTAG_TMS JTAG_TDI JTAG_MOD BOOT_MODE2 24M_XTALI VSS
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Package information and contact assignments

89
 90
P N M L K J H

1
DRAM_VREF DRAM_AC26 DRAM_AC16 DRAM_AC05 DRAM_DQ13 DRAM_DQ10 DRAM_DQS1_N
2

Downloaded from Arrow.com.

DRAM_ZN DRAM_AC19 DRAM_AC17 DRAM_AC04 DRAM_DQ12 DRAM_DQ11 VSS
3

VSS VSS VSS VSS

4

DRAM_AC12 DRAM_AC02 DRAM_AC03

5

VDD_DRAM_PLL_1P8 DRAM_AC13 DRAM_AC14 DRAM_AC07

6

DRAM_AC15 DRAM_AC09 DRAM_AC08

7

NVCC_DRAM VSS VSS VSS

8

NVCC_DRAM NVCC_DRAM
9

VDD_DRAM_PLL_0P8 NVCC_DRAM NVCC_DRAM NVCC_DRAM NVCC_DRAM

VDD_DRAM VDD_DRAM VDD_DRAM NVCC_ECSPI
Package information and contact assignments

NVCC_I2C

VDD_GPU VSS VSS VSS NVCC_UART

VSS VDD_SOC PVCC2_1P8 VDD_MIPI_1P8
VDD_MIPI_0P8

VSS VDD_SOC VDD_SOC VDD_SOC VDD_SOC VDD_MIPI_1P2 VDD_USB_1P8

VDD_ARM_PLL_0P8 VSS VSS VSS VDD_SOC
VDD_ANA_0P8 VDD_ANA_0P8 VDD_USB_0P8

VDD_SOC VDD_SOC VSS

VDD_ANA1_1P8 VDD_24M_XTAL_1P8 NVCC_CLK NVCC_JTAG VDD_USB_3P3

VDD_ANA1_1P8 VSS
Table 76. 14 x 14 mm, 0.5 mm pitch ball map (continued)

VSS VSS VSS VSS

NAND_ALE VDD_SNVS_0P8 NVCC_SNVS_1P8

NAND_DATA00 NAND_DATA03 NAND_DATA02 TSENSOR_TEST_OUT

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NAND_CE0_B NAND_DATA01 TSENSOR_RES_EXT

VSS VSS VSS VSS

NAND_READY_B NAND_DATA07 NAND_DATA04 NAND_DATA05 NAND_DATA06 CLKOUT2 CLKOUT1
NAND_CE1_B NAND_RE_B NAND_CE2_B NAND_CE3_B NAND_CLE CLKIN2 CLKIN1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

NXP Semiconductors
 AB AA Y W V U T R

1
DRAM_AC25 DRAM_AC34 DRAM_RESET_N
2

Downloaded from Arrow.com.

VSS DRAM_AC24 DRAM_AC35 DRAM_ALERT_N
3

VSS VSS VSS VSS

4

NXP Semiconductors
DRAM_AC20 DRAM_AC22 DRAM_AC23 DRAM_AC32
5

DRAM_AC21 DRAM_AC37 DRAM_AC36 DRAM_AC33

6

DRAM_AC38 DRAM_AC28 DRAM_AC29 DRAM_AC27

7

VSS VSS VSS VSS

8

NVCC_DRAM NVCC_DRAM
9

GPIO1_IO15 VSS NVCC_DRAM NVCC_DRAM NVCC_DRAM NVCC_DRAM

GPIO1_IO12 VSS NVCC_SAI3 VDD_DRAM VDD_DRAM VDD_DRAM
VDD_GPU VDD_GPU VDD_GPU

NVCC_GPIO1 VDD_GPU VSS VSS VSS

PVCC0_1P8 VSS VSS VDD_ARM VDD_ARM VDD_ARM VDD_ARM VDD_ARM
VDD_ANA0_1P8 VDD_ARM VDD_ARM

SAI5_RXFS VSS VDD_ANA0_1P8 VDD_ARM VDD_ARM VDD_ARM VDD-ARM VDD_ARM

VDD_ARM VDD_ARM VSS VSS VSS
NVCC_SAI5 VDD_SOC VDD_SOC

VSS VSS VDD_SOC VDD_SOC

VSS NVCC_SAI2 NVCC_NAND PVCC1_1P8 VDD_ARM_PLL_1P8

NVCC_SD1 VSS
Table 76. 14 x 14 mm, 0.5 mm pitch ball map (continued)

VSS VSS VSS VSS

SAI2_RXC NVCC_ENET NVCC_SD2 NAND_DQS

SD2_DATA0 SD2_CLK SD2_DATA3 SD1_RESET_B

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
SD2_DATA1 SD2_CMD SD2_DATA2 SD1_STROBE

VSS VSS VSS VSS

SD2_RESET_B SD2_CD_B SD1_DATA1 SD1_DATA7 SD1_CLK SD1_DATA5 SD1_DATA3 NAND_WE_B
ENET_MDIO SD2_WP SD1_DATA0 SD1_DATA6 SD1_CMD SD1_DATA4 SD1_DATA2 NAND_WP_B
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Package information and contact assignments

91
 92
AG AF AE AD AC

1
VSS
2

Downloaded from Arrow.com.

VSS
3

VSS VSS
4

DRAM_AC30
5

VSS DRAM_AC31
6

SAI3_TXC SAI3_TXD VSS SAI3_MCLK SAI3_TXFS

7

SAI3_RXC SAI3_RXD
8

SAI3_RXFS SPDIF_EXT_CLK
9

SPDIF_RX SPDIF_TX VSS GPIO1_IO13 GPIO1_IO14

GPIO1_IO08 GPIO1_IO09 VSS GPIO1_IO10 GPIO1_IO11
Package information and contact assignments

GPIO1_IO06 GPIO1_IO07

GPIO1_IO04 GPIO1_IO05
GPIO1_IO02 GPIO1_IO03 VSS SAI5_RXD2 SAI5_RXD3
GPIO1_IO00 GPIO1_IO01 VSS SAI5_RXD1

VSS SAI5_MCLK SAI5_RXC

VSS SAI5_RXD0
VSS SAI2_MCLK SAI2_RXFS
Table 76. 14 x 14 mm, 0.5 mm pitch ball map (continued)

VSS SAI2_TXC SAI2_TXD0

VSS SAI2_TXFS

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
ENET_TXC ENET_TX_CTL SAI2_RXD0

ENET_TD2 ENET_TD3 VSS

ENET_TD0 ENET_TD1 ENET_RXC ENET_RD2 ENET_RD3
VSS ENET_RX_CTL ENET_RD0 ENET_RD1 ENET_MDC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

NXP Semiconductors
 Package information and contact assignments

5.2 11 x 11 mm package information

5.2.1 11 x 11 mm, 0.5 mm pitch, ball matrix

Figure 50 shows the top, bottom, and side views of the 11 × 11 mm FCBGA package.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 93

Downloaded from Arrow.com.

 Package information and contact assignments

Figure 50. 11 X 11 MM BGA, case x package top, bottom, and side views

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
94 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

5.2.2 11 x 11 mm supplies contact assignments and functional contact

assignments
Table 77 shows supplies contact assignments for the 11 x 11 mm package.

Table 77. i.MX 8M Nano 11 x 11 mm supplies contact assignments

Supply Rail Name Ball(s) Position(s) Remark

NVCC_CLK_JTAG_PVCC_1 L15 Supply for CLK, JTAG interface and Digital I/O
P8 pre-drive

NVCC_DRAM G6, J6, J7, L6, N6, N7, R6 Supply for DRAM interface

NVCC_ECSPI G8 Supply for ECSPI interface

NVCC_ENET_GPIO_SAI2 R12 Supply for ENET, GPIO1, and SAI2 interface

NVCC_I2C_UART G10 Supply for I2C and UART interface

NVCC_SAI3_SAI5 R10 Supply for SAI3 and SAI5 interface

NVCC_SD1_NAND N15 Supply for SD1 and NAND interface

NVCC_SD2 R16 Supply for SD interface

NVCC_SNVS_1P8 G14 Supply for SNVS interface

VDD_ANA1_XTAL_MIPI_US G12 Supply for XTAL, Analog logic, MIPI, and USB
B_1P8 1.8 V

VDD_ANA0_ARM_PLL_1P8 R14 Supply for Analog logic and ARM PLL 1.8 V

VDD_DRAM_PLL_1P8 L7 Supply for DRAM PLL

VDD_MIPI_1P2 F12 Supply for MIPI PHY

VDD_SNVS_0P8 J15 Supply for SNVS logic

VDD_SOC J9, J10, J11, J12, J13, K10, K12, L9, L10, L12, Supply for SOC logic
L13, M10, M12, N9, N10, N11, N12, N13

VDD_USB_3P3 F14 Supply for USB PHY

VSS A1, AA1, E3, G3, J3, L3, N3, R3, U3, C4, W4, —
C6, W6, C8, H8, J8, L8, N8, P8, W8, C10,
H10, P10, W10, K11, M11, C12, H12, P12,
W12, C14, H14, J14, L14, N14, P14, W14,
C16, W16, C18, W18, E19, G19, J19, L19,
N19, R19, U19, B20, A21, AA21

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 95

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78 shows an alpha-sorted list of functional contact assignments for the 11 x 11 mm package.

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

24M_XTALI B21 NVCC_CLK_JTAG ANALOG — — Input

_PVCC_1P8
24M_XTALO C20 NVCC_CLK_JTAG ANALOG — — Output
_PVCC_1P8

BOOT_MODE0 G16 NVCC_CLK_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[0] Input with PD

_PVCC_1P8

BOOT_MODE1 G18 NVCC_CLK_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[1] Input with PD

_PVCC_1P8
BOOT_MODE2 F16 NVCC_CLK_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[2] Input with PD
_PVCC_1P8

BOOT_MODE3 G17 NVCC_CLK_JTAG GPIO ALT0 ccmsrcgpcmix.BOOT_MODE[3] Input with PD

_PVCC_1P8

CLKIN1 E20 NVCC_CLK_JTAG GPIO — — Input without

_PVCC_1P8 PU/PD
CLKIN2 F20 NVCC_CLK_JTAG GPIO — — Input without
_PVCC_1P8 PU/PD

CLKOUT1 E21 NVCC_CLK_JTAG GPIO — — Output low

_PVCC_1P8 without
PU/PD
CLKOUT2 F21 NVCC_CLK_JTAG GPIO — — Output low
_PVCC_1P8 without
PU/PD

DRAM_AC00 P1 NVCC_DRAM DDR — — Output low

DRAM_AC01 N1 NVCC_DRAM DDR — — Output low

DRAM_AC02 N2 NVCC_DRAM DDR — — Input

DRAM_AC03 P2 NVCC_DRAM DDR — — Input

DRAM_AC04 G5 NVCC_DRAM DDR — — Input

DRAM_AC05 G4 NVCC_DRAM DDR — — Input

DRAM_AC06 D4 NVCC_DRAM DDR — — Input

DRAM_AC07 E4 NVCC_DRAM DDR — — Input

DRAM_AC08 R1 NVCC_DRAM DDR — — Input

DRAM_AC09 R2 NVCC_DRAM DDR — — Input

DRAM_AC10 M2 NVCC_DRAM DDR — — Input

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
96 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

DRAM_AC11 L2 NVCC_DRAM DDR — — Input

DRAM_AC12 L1 NVCC_DRAM DDR — — Input

DRAM_AC13 M1 NVCC_DRAM DDR — — Input

DRAM_AC14 Y1 NVCC_DRAM DDR — — Input

DRAM_AC15 L5 NVCC_DRAM DDR — — Input

DRAM_AC16 J4 NVCC_DRAM DDR — — Input

DRAM_AC17 J5 NVCC_DRAM DDR — — Input

DRAM_AC20 T1 NVCC_DRAM DDR — — Output low

DRAM_AC21 T2 NVCC_DRAM DDR — — Output low

DRAM_AC23 R4 NVCC_DRAM DDR — — Input

DRAM_AC24 Y2 NVCC_DRAM DDR — — Input

DRAM_AC25 AA2 NVCC_DRAM DDR — — Input

DRAM_AC26 W2 NVCC_DRAM DDR — — Input

DRAM_AC28 AA3 NVCC_DRAM DDR — — Input

DRAM_AC29 V4 NVCC_DRAM DDR — — Input

DRAM_AC30 W1 NVCC_DRAM DDR — — Input

DRAM_AC31 Y3 NVCC_DRAM DDR — — Input

DRAM_AC32 R5 NVCC_DRAM DDR — — Input

DRAM_AC33 U2 NVCC_DRAM DDR — — Input

DRAM_AC34 V2 NVCC_DRAM DDR — — Input

DRAM_AC35 U4 NVCC_DRAM DDR — — Input

DRAM_AC36 V1 NVCC_DRAM DDR — — Input

DRAM_ALERT_N N5 NVCC_DRAM DDR — — Input

DRAM_DM0 B2 NVCC_DRAM DDR — — Input

DRAM_DM1 H2 NVCC_DRAM DDR — — Input

DRAM_DQ00 B3 NVCC_DRAM DDR — — Input

DRAM_DQ01 A2 NVCC_DRAM DDR — — Input

DRAM_DQ02 A3 NVCC_DRAM DDR — — Input

DRAM_DQ03 B4 NVCC_DRAM DDR — — Input

DRAM_DQ04 E2 NVCC_DRAM DDR — — Input

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 97

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

DRAM_DQ05 D1 NVCC_DRAM DDR — — Input

DRAM_DQ06 C1 NVCC_DRAM DDR — — Input

DRAM_DQ07 D2 NVCC_DRAM DDR — — Input

DRAM_DQ08 G1 NVCC_DRAM DDR — — Input

DRAM_DQ09 H1 NVCC_DRAM DDR — — Input

DRAM_DQ10 J1 NVCC_DRAM DDR — — Input

DRAM_DQ11 J2 NVCC_DRAM DDR — — Input

DRAM_DQ12 K1 NVCC_DRAM DDR — — Input

DRAM_DQ13 K2 NVCC_DRAM DDR — — Input

DRAM_DQ14 F2 NVCC_DRAM DDR — — Input

DRAM_DQ15 E1 NVCC_DRAM DDR — — Input

DRAM_DQS0_N C2 NVCC_DRAM — — — Input

DRAM_DQS0_P B1 NVCC_DRAM DDRCLK — — Input

DRAM_DQS1_N F1 NVCC_DRAM — — — Input

DRAM_DQS1_P G2 NVCC_DRAM DDRCLK — — Input

DRAM_RESET_N N4 NVCC_DRAM DDR — — Output low

DRAM_VREF L4 NVCC_DRAM DDR — — —

DRAM_ZN U1 NVCC_DRAM DDR — — —

ECSPI1_MISO D6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[8] Input with PD

ECSPI1_MOSI F6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[7] Input with PD

ECSPI1_SCLK E6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[6] Input with PD

ECSPI1_SS0 B6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[9] Input with PD

ECSPI2_MISO B5 NVCC_ECSPI GPIO ALT5 GPIO5.IO[12] Input with PD

ECSPI2_MOSI A6 NVCC_ECSPI GPIO ALT5 GPIO5.IO[11] Input with PD

ECSPI2_SCLK A4 NVCC_ECSPI GPIO ALT5 GPIO5.IO[10] Input with PD

ECSPI2_SS0 A5 NVCC_ECSPI GPIO ALT5 GPIO5.IO[13] Input with PD

ENET_MDC Y18 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[16] Input with PD

O_SAI2

ENET_MDIO T16 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[17] Input with PD

O_SAI2

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
98 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

ENET_RD0 AA19 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[26] Input with PD

O_SAI2

ENET_RD1 Y15 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[27] Input with PD

O_SAI2
ENET_RD2 Y16 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[28] Input with PD
O_SAI2

ENET_RD3 AA16 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[29] Input with PD

O_SAI2

ENET_RXC U16 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[25] Input with PD

O_SAI2
ENET_RX_CTL V16 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[24] Input with PD
O_SAI2

ENET_TD0 U18 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[21] Input with PD

O_SAI2

ENET_TD1 AA18 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[20] Input with PD

O_SAI2
ENET_TD2 V18 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[19] Input with PD
O_SAI2

ENET_TD3 AA17 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[18] Input with PD

O_SAI2

ENET_TXC Y19 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[23] Input with PD

O_SAI2
ENET_TX_CTL Y17 NVCC_ENET_GPI GPIO ALT5 GPIO1.IO[22] Input with PD
O_SAI2

GPIO1_IO00 V8 NVCC_ENET_GPI GPIO ALT6 GPIO1.IO[0] Input with PD

O_SAI2
GPIO1_IO01 R8 NVCC_ENET_GPI GPIO ALT6 GPIO1.IO[1] 1

O_SAI2
GPIO1_IO02 AA8 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[2] Input with PU
O_SAI2

GPIO1_IO03 Y9 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[3] Input with PD

O_SAI2

GPIO1_IO04 AA7 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[4] Input with PD

O_SAI2
1
GPIO1_IO05 T8 NVCC_ENET_GPI GPIO ALT6 GPIO1.IO[5]
O_SAI2

GPIO1_IO06 Y8 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[6] Input with PD

O_SAI2

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 99

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

GPIO1_IO07 U8 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[7] Input with PD

O_SAI2

GPIO1_IO08 V10 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[8] Input with PD

O_SAI2
GPIO1_IO09 AA9 NVCC_ENET_GPI GPIO ALT1 GPIO1.IO[9] Input with PD
O_SAI2

GPIO1_IO10 AA10 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[10] Input with PD

O_SAI2

GPIO1_IO11 Y11 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[11] Input with PD

O_SAI2
GPIO1_IO12 U10 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[12] Input with PD
O_SAI2

GPIO1_IO13 T10 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[13] Input with PD

O_SAI2

GPIO1_IO14 Y10 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[14] Input with PD

O_SAI2
GPIO1_IO15 AA11 NVCC_ENET_GPI GPIO ALT0 GPIO1.IO[15] Input with PD
O_SAI2

I2C1_SCL B7 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[14] Input with PD

I2C1_SDA A7 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[15] Input with PD

I2C2_SCL F10 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[16] Input with PD

I2C2_SDA D8 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[17] Input with PD

I2C3_SCL F8 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[18] Input with PD

I2C3_SDA E8 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[19] Input with PD

I2C4_SCL B8 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[20] Input with PD

I2C4_SDA A8 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[21] Input with PD

JTAG_MOD D18 NVCC_CLK_JTAG GPIO ALT0 cjtag_wrapper.MOD Input with PD

_PVCC_1P8

JTAG_TCK D21 NVCC_CLK_JTAG GPIO ALT0 cjtag_wrapper.TCK Input with PU

_PVCC_1P8
JTAG_TDI C21 NVCC_CLK_JTAG GPIO ALT0 cjtag_wrapper.TDI Input with PU
_PVCC_1P8

JTAG_TDO D20 NVCC_CLK_JTAG GPIO ALT0 cjtag_wrapper.TDO Input with PU

_PVCC_1P8
JTAG_TMS2 E18 NVCC_CLK_JTAG GPIO ALT0 cjtag_wrapper.TMS Input with PU
_PVCC_1P8

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
100 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

MIPI_CSI_CLK_N A13 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8

MIPI_CSI_CLK_P B13 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8
MIPI_CSI_D0_N A11 VDD_ANA1_XTAL_ PHY — — Input
MIPI_USB_1P8

MIPI_CSI_D0_P B11 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8

MIPI_CSI_D1_N A12 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8
MIPI_CSI_D1_P B12 VDD_ANA1_XTAL_ PHY — — Input
MIPI_USB_1P8

MIPI_CSI_D2_N A14 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8

MIPI_CSI_D2_P B14 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8
MIPI_CSI_D3_N A15 VDD_ANA1_XTAL_ PHY — — Input
MIPI_USB_1P8

MIPI_CSI_D3_P B15 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8

MIPI_VREG_CAP D12 0.35 - 0.45 V PHY — — Output

NAND_ALE J17 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[0] Input with PD

NAND_CE0_B L21 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[1] Input with PD

NAND_CE1_B H20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[2] Input with PD

NAND_CE2_B L16 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[3] Input with PD

NAND_CE3_B L20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[4] Input with PD

NAND_CLE K20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[5] Input with PD

NAND_DATA00 M21 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[6] Input with PD

NAND_DATA01 J20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[7] Input with PD

NAND_DATA02 M20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[8] Input with PD

NAND_DATA03 K21 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[9] Input with PD

NAND_DATA04 L18 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[10] Input with PD

NAND_DATA05 J18 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[11] Input with PD

NAND_DATA06 N20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[12] Input with PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 101

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

NAND_DATA07 G20 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[13] Input with PD

NAND_DQS H21 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[14] Input with PD

NAND_RE_B G21 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[15] Input with PD

NAND_READY_B L17 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[16] Input with PD

NAND_WE_B J16 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[17] Input with PD

NAND_WP_B J21 NVCC_SD1_NAND GPIO ALT5 GPIO3.IO[18] Input with PD

ONOFF E14 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.ONOFF Input without

PU/PD

PMIC_ON_REQ E16 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.PMIC_ON_REQ Open-drain

output high
with PU
PMIC_STBY_REQ A19 NVCC_SNVS_1P8 GPIO ALT0 ccmsrcgpcmix.PMIC_STBY_RE Output low
Q with PD

POR_B A18 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.POR_B Input without

PU/PD
RTC_XTALI A20 NVCC_SNVS_1P8 ANALOG ALT0 snvsmix.RTC Input

RTC_XTALO B19 NVCC_SNVS_1P8 ANALOG — — Output,

inverted of
RTC_XTALI

RTC_RESET_B B18 NVCC_SNVS_1P8 GPIO ALT0 snvsmix.RTC_POR_B Input without

PU/PD
SAI2_MCLK Y12 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[27] Input with PD
O_SAI2

SAI2_RXC AA15 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[22] Input with PD

O_SAI2
SAI2_RXD0 AA14 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[23] Input with PD
O_SAI2
SAI2_RXFS Y13 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[21] Input with PD
O_SAI2

SAI2_TXC AA13 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[25] Input with PD

O_SAI2

SAI2_TXD0 Y14 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[26] Input with PD

O_SAI2
SAI2_TXFS AA12 NVCC_ENET_GPI GPIO ALT5 GPIO4.IO[24] Input with PD
O_SAI2

SAI3_MCLK AA5 NVCC_SAI3_SAI5 GPIO ALT5 GPIO5.IO[2] Input with PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
102 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

SAI3_RXC Y6 NVCC_SAI3_SAI5 GPIO ALT5 GPIO4.IO[29] Input with PD

SAI3_RXD AA6 NVCC_SAI3_SAI5 GPIO ALT5 GPIO4.IO[30] Input with PD

SAI3_RXFS Y4 NVCC_SAI3_SAI5 GPIO ALT5 GPIO4.IO[28] Input with PD

SAI3_TXC Y5 NVCC_SAI3_SAI5 GPIO ALT5 GPIO5.IO[0] Input with PD

SAI3_TXD AA4 NVCC_SAI3_SAI5 GPIO ALT5 GPIO5.IO[1] Input with PD

SAI3_TXFS Y7 NVCC_SAI3_SAI5 GPIO ALT5 GPIO4.IO[31] Input with PD

3
SAI5_MCLK W11 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[25]

SAI5_RXC V14 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[20] Input with PD

SAI5_RXD0 U12 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[21] Input with PD

SAI5_RXD1 T14 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[22] Input with PD

SAI5_RXD2 V12 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[23] Input with PD

SAI5_RXD3 U14 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[24] Input with PD

SAI5_RXFS T12 NVCC_SAI3_SAI5 GPIO ALT5 GPIO3.IO[19] Input with PD

SD1_CLK R21 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[0] Input with PD

SD1_CMD T21 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[1] Input with PD

SD1_DATA0 N18 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[2] Input with PD

SD1_DATA1 N17 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[3] Input with PD

SD1_DATA2 N21 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[4] Input with PD

SD1_DATA3 P20 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[5] Input with PD

SD1_DATA4 P21 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[6] Input with PD

SD1_DATA5 T20 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[7] Input with PD

SD1_DATA6 R20 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[8] Input with PD

SD1_DATA7 N16 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[9] Input with PD

SD1_RESET_B R18 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[10] Input with PD

SD1_STROBE R17 NVCC_SD1_NAND GPIO ALT5 GPIO2.IO[11] Input with PD

SD2_CD_B U20 NVCC_SD2 GPIO ALT5 GPIO2.IO[12] Input with PD

SD2_CLK Y21 NVCC_SD2 GPIO ALT5 GPIO2.IO[13] Input with PD

SD2_CMD V21 NVCC_SD2 GPIO ALT5 GPIO2.IO[14] Input with PD

SD2_DATA0 AA20 NVCC_SD2 GPIO ALT5 GPIO2.IO[15] Input with PD

SD2_DATA1 U21 NVCC_SD2 GPIO ALT5 GPIO2.IO[16] Input with PD

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 103

Downloaded from Arrow.com.

 Package information and contact assignments

Table 78. i.MX 8M Nano 11 x 11 mm functional contact assignments (continued)

Reset condition

Ball name Ball Power group Ball type Input/

Default
Default function Output
mode
status

SD2_DATA2 W20 NVCC_SD2 GPIO ALT5 GPIO2.IO[17] Input with PD

SD2_DATA3 V20 NVCC_SD2 GPIO ALT5 GPIO2.IO[18] Input with PD

SD2_RESET_B Y20 NVCC_SD2 GPIO ALT5 GPIO2.IO[19] Input with PD

SD2_WP W21 NVCC_SD2 GPIO ALT5 GPIO2.IO[20] Input with PD

SPDIF_EXT_CLK T6 NVCC_SAI3_SAI5 GPIO ALT5 GPIO5.IO[5] Input with PD

SPDIF_RX U6 NVCC_SAI3_SAI5 GPIO ALT5 GPIO5.IO[4] Input with PD

SPDIF_TX V6 NVCC_SAI3_SAI5 GPIO ALT5 GPIO5.IO[3] Input with PD

TSENSOR_RES_E D16 VDD_ANA1_XTAL_ ANALOG — — —

XT MIPI_USB_1P8

UART1_RXD A9 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[22] Input with PD

UART1_TXD E10 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[23] Input with PD

UART2_RXD B9 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[24] Input with PD

UART2_TXD C11 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[25] Input with PD

UART3_RXD B10 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[26] Input with PD

UART3_TXD E12 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[27] Input with PD

UART4_RXD A10 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[28] Input with PD

UART4_TXD D10 NVCC_I2C_UART GPIO ALT5 GPIO5.IO[29] Input with PD

USB1_DN A17 VDD_USB_3P3 PHY — — Input

USB1_DP B17 VDD_USB_3P3 PHY — — Input

USB1_ID D14 VDD_ANA1_XTAL_ PHY — — Input

MIPI_USB_1P8
USB1_TXRTUNE B16 VDD_ANA1_XTAL_ PHY — — —
MIPI_USB_1P8

USB1_VBUS A16 VDD_USB_3P3 PHY — — —

1
During reset: output high without PU/PD; After reset: input with PU
2 Mandatory requirement: JTAG_TMS pin must be connected with a 50 ohm serial resistor near the component.
3 During reset: input without PU/PD; After reset: input with PD

5.2.3 i.MX 8M Nano 11 x 11 mm 0.5 mm pitch ball map

Table 79 shows the i.MX 8M Nano 11 x 11 mm 0.5 mm pitch ball map.

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
104 NXP Semiconductors

Downloaded from Arrow.com.

 F E D C B A

DRAM_DQS1_N DRAM_DQ15 DRAM_DQ05 DRAM_DQ06 DRAM_DQS0_P VSS

1

Downloaded from Arrow.com.

DRAM_DQ14 DRAM_DQ04 DRAM_DQ07 DRAM_DQS0_N DRAM_DM0 DRAM_DQ01
2

VSS DRAM_DQ00 DRAM_DQ02

NXP Semiconductors
3

DRAM_AC07 DRAM_AC06 VSS DRAM_DQ03 ECSPI2_SCLK

4

ECSPI2_MISO ECSPI2_SS0
5

ECSPI1_MOSI ECSPI1_SCLK ECSPI1_MISO VSS ECSPI1_SS0 ECSPI2_MOSI

6

I2C1_SCL I2C1_SDA
7

I2C3_SCL I2C3_SDA I2C2_SDA VSS I2C4_SCL I2C4_SDA

8

UART2_RXD UART1_RXD
9

I2C2_SCL UART1_TXD UART4_TXD VSS UART3_RXD UART4_RXD

10

UART2_TXD MIPI_CSI_D0_P MIPI_CSI_D0_N

11

VDD_MIPI_1P2 UART3_TXD MIPI_VREG_CAP VSS MIPI_CSI_D1_P MIPI_CSI_D1_N

12

MIPI_CSI_CLK_P MIPI_CSI_CLK_N
13

VDD_USB_3P3 ONOFF USB1_ID VSS MIPI_CSI_D2_P MIPI_CSI_D2_N

14
Table 79. 11 x 11 mm, 0.5 mm pitch ball map

MIPI_CSI_D3_P MIPI_CSI_D3_N
15

BOOT_MODE2 PMIC_ON_REQ TSENSOR_RES_EXT VSS USB1_TXRTUNE USB1_VBUS

16

USB1_DP USB1_DN
17

JTAG_TMS JTAG_MOD VSS RTC_RESET_B POR_B

18

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
VSS RTC_XTALO PMIC_STBY_REQ
19

CLKIN2 CLKIN1 JTAG_TDO 24M_XTALO VSS RTC_XTALI

20

CLKOUT2 CLKOUT1 JTAG_TCK JTAG_TDI 24M_XTALI VSS

21
Package information and contact assignments

105
 106
M L K J H G

DRAM_AC13 DRAM_AC12 DRAM_DQ12 DRAM_DQ10 DRAM_DQ09 DRAM_DQ08 1

Downloaded from Arrow.com.

DRAM_AC10 DRAM_AC11 DRAM_DQ13 DRAM_DQ11 DRAM_DM1 DRAM_DQS1_P
2

VSS VSS VSS

3

DRAM_VREF DRAM_AC16 DRAM_AC05

4

DRAM_AC15 DRAM_AC17 DRAM_AC04

5

NVCC_DRAM NVCC_DRAM NVCC_DRAM

6

VDD_DRAM_PLL_1P8 NVCC_DRAM
7

VSS VSS VSS NVCC_ECSPI

Package information and contact assignments

VDD_SOC VDD_SOC
9

VDD_SOC VDD_SOC VDD_SOC VDD_SOC VSS NVCC_I2C_UART

10

VSS VSS VDD_SOC

11

VDD_SOC VDD_SOC VDD_SOC VDD_SOC VSS VDD_ANA1_XTAL_MIPI_USB_1P8

12

VDD_SOC VDD_SOC
13

VSS VSS VSS NVCC_SNVS_1P8

14

NVCC_CLK_JTAG_PVCC_1P8 VDD_SNVS_0P8
15

NAND_CE2_B NAND_WE_B BOOT_MODE0

16
Table 79. 11 x 11 mm, 0.5 mm pitch ball map (continued)

NAND_READY_B NAND_ALE BOOT_MODE3

17

NAND_DATA04 NAND_DATA05 BOOT_MODE1

18

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
VSS VSS VSS
19

NAND_DATA02 NAND_CE3_B NAND_CLE NAND_DATA01 NAND_CE1_B NAND_DATA07

20

NAND_DATA00 NAND_CE0_B NAND_DATA03 NAND_WP_B NAND_DQS NAND_RE_B

21

NXP Semiconductors
 W V U T R P N

DRAM_AC30 DRAM_AC36 DRAM_ZN DRAM_AC20 DRAM_AC08 DRAM_AC00 DRAM_AC01 1

Downloaded from Arrow.com.

DRAM_AC26 DRAM_AC34 DRAM_AC33 DRAM_AC21 DRAM_AC09 DRAM_AC03 DRAM_AC02
2

VSS VSS VSS

NXP Semiconductors
3

VSS DRAM_AC29 DRAM_AC35 DRAM_AC23 DRAM_RESET_N

4

DRAM_AC32 DRAM_ALERT_N
5

VSS SPDIF_TX SPDIF_RX SPDIF_EXT_CLK NVCC_DRAM NVCC_DRAM

6

NVCC_DRAM
7

VSS GPIO1_IO00 GPIO1_IO07 GPIO1_IO05 GPIO1_IO01 VSS VSS

8

VDD_SOC
9

VSS GPIO1_IO08 GPIO1_IO12 GPIO1_IO13 NVCC_SAI3_SAI5 VSS VDD_SOC

10

SAI5_MCLK VDD_SOC
11

VSS SAI5_RXD2 SAI5_RXD0 SAI5_RXFS NVCC_ENET_GPIO_SAI2 VSS VDD_SOC

12

VDD_SOC
13

VSS SAI5_RXC SAI5_RXD3 SAI5_RXD1 VDD_ANA0_ARM_PLL_1P8 VSS VSS

14

NVCC_SD1_NAND
15

VSS ENET_RX_CTL ENET_RXC ENET_MDIO NVCC_SD2 SD1_DATA7

16
Table 79. 11 x 11 mm, 0.5 mm pitch ball map (continued)

SD1_STROBE SD1_DATA1
17

VSS ENET_TD2 ENET_TD0 SD1_RESET_B SD1_DATA0

18

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
VSS VSS VSS
19

SD2_DATA2 SD2_DATA3 SD2_CD_B SD1_DATA5 SD1_DATA6 SD1_DATA3 NAND_DATA06

20

SD2_WP SD2_CMD SD2_DATA1 SD1_CMD SD1_CLK SD1_DATA4 SD1_DATA2

21
Package information and contact assignments

107
 Package information and contact assignments

Table 79. 11 x 11 mm, 0.5 mm pitch ball map (continued)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

SD2_DATA0 SD2_RESET_B
ENET_TX_CTL
DRAM_AC14

DRAM_AC24

DRAM_AC31

GPIO1_IO06

GPIO1_IO03

GPIO1_IO14

GPIO1_IO11

SAI2_MCLK

ENET_MDC
SAI3_RXFS

SAI2_RXFS

SAI2_TXD0
SAI3_TXFS

ENET_TXC
ENET_RD1

ENET_RD2
SAI3_RXC
SAI3_TXC

SD2_CLK
Y

DRAM_AC25

DRAM_AC28

GPIO1_IO04

GPIO1_IO02

GPIO1_IO09

GPIO1_IO10

GPIO1_IO15
SAI3_MCLK

SAI2_RXD0
SAI2_TXFS

ENET_RD3

ENET_RD0
ENET_TD3

ENET_TD1
SAI3_RXD

SAI2_RXC
SAI3_TXD

SAI2_TXC
VSS

VSS
AA

5.3 DDR pin function list

Table 80 shows the DDR pin function list.
Table 80. DDR pin function list

Ball name LPDDR4 DDR4 DDR3/3L

DRAM_DQS0_P DQS0_t_A DQSL_t_A DQSL_A

DRAM_DQS0_N DQS0_c_A DQSL_c_A DQSL#_A

DRAM_DM0 DMI0_A DML_n_A / DBIL_n_A DML_A

DRAM_DQ00 DQ0_A DQL0_A DQL0_A

DRAM_DQ01 DQ1_A DQL1_A DQL1_A

DRAM_DQ02 DQ2_A DQL2_A DQL2_A

DRAM_DQ03 DQ3_A DQL3_A DQL3_A

DRAM_DQ04 DQ4_A DQL4_A DQL4_A

DRAM_DQ05 DQ5_A DQL5_A DQL5_A

DRAM_DQ06 DQ6_A DQL6_A DQL6_A

DRAM_DQ07 DQ7_A DQL7_A DQL7_A

DRAM_DQS1_P DQS1_t_A DQSU_t_A DQSU_A

DRAM_DQS1_N DQS1_c_A DQSU_c_A DQSU#_A

DRAM_DM1 DMI1_A DMU_n_A / DBIU_n_A DMU_A

DRAM_DQ08 DQ08_A DQU0_A DQU0_A

DRAM_DQ09 DQ09_A DQU1_A DQU1_A

DRAM_DQ10 DQ10_A DQU2_A DQU2_A

DRAM_DQ11 DQ11_A DQU3_A DQU3_A

DRAM_DQ12 DQ12_A DQU4_A DQU4_A

DRAM_DQ13 DQ13_A DQU5_A DQU5_A

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
108 NXP Semiconductors

Downloaded from Arrow.com.

 Package information and contact assignments

Table 80. DDR pin function list (continued)

DRAM_DQ14 DQ14_A DQU6_A DQU6_A

DRAM_DQ15 DQ15_A DQU7_A DQU7_A

DRAM_RESET_N RESET_N RESET_n RESET#

DRAM_ALERT_N MTEST1 ALERT_n / MTEST1 MTEST1

DRAM_AC00 CKE0_A CKE0 CKE0

DRAM_AC01 CKE1_A CKE1 CKE1

DRAM_AC02 CS0_A CS0_n CS0#

DRAM_AC03 CS1_A C0 —

DRAM_AC04 CK_t_A BG0 BA2

DRAM_AC05 CK_c_A BG1 A14

DRAM_AC06 — ACT_n A15

DRAM_AC07 — A9 A9

DRAM_AC08 CA0_A A12 A12 / BC#

DRAM_AC09 CA1_A A11 A11

DRAM_AC10 CA2_A A7 A7

DRAM_AC11 CA3_A A8 A8

DRAM_AC12 CA4_A A6 A6

DRAM_AC13 CA5_A A5 A5

DRAM_AC14 — A4 A4

DRAM_AC15 — A3 A3

DRAM_AC16 — CK_t_A CK_A

DRAM_AC17 — CK_c_A CK#_A

DRAM_AC19 MTEST MTEST MTEST

DRAM_AC20 CKE0_B CK_t_B CK_B

DRAM_AC21 CKE1_B CK_c_B CK#_B

DRAM_AC22 CS1_B — —

DRAM_AC23 CS0_B — —

DRAM_AC24 CK_t_B A2 A2

DRAM_AC25 CK_c_B A1 A1

DRAM_AC26 — BA1 BA1

DRAM_AC27 — PARITY —

DRAM_AC28 CA0_B A13 A13

DRAM_AC29 CA1_B BA0 BA0

DRAM_AC30 CA2_B A10 / AP A10 / AP

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 109

Downloaded from Arrow.com.

 Package information and contact assignments

Table 80. DDR pin function list (continued)

DRAM_AC31 CA3_B A0 A0

DRAM_AC32 CA4_B C2 —

DRAM_AC33 CA5_B CAS_n / A15 CAS#

DRAM_AC34 — WE_n / A14 WE#

DRAM_AC35 — RAS_n / A16 RAS#

DRAM_AC36 — ODT0 ODT0

DRAM_AC37 — ODT1 ODT1

DRAM_AC38 — CS1_n CS1#

DRAM_ZN ZQ ZQ ZQ

DRAM_VREF VREF VREF VREF

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
110 NXP Semiconductors

Downloaded from Arrow.com.

 Revision history

6 Revision history
Table 81 provides a revision history for this data sheet.
Table 81. Revision history

Rev.number Date Substantive change(s)

Rev. 1 03/2021 • Added a note for the Figure 1, "i.MX 8M Nano system block diagram" and Table 2,
"Modules supported"
• Added part numbers for 11 x 11 mm package and descriptions in the Table 3, "Orderable
part numbers"
• Updated the package type and part differentiator in the Figure 2, "Part number
nomenclature—i.MX 8M Nano family of processors"
• Updated the LCDIF descriptions in the Table 4, "i.MX 8M Nano modules list"
• Updated the Section 2.1, Recommended connections for unused input/output
• Updated the title and the maximum values of VDD_ARM_PLL_0P8 and VDD_USB_0P8
in the Table 10, "Absolute maximum ratings for 14 x 14 mm package"
• Added the Table 11, "Absolute maximum ratings for 11 x 11 mm package"
• Updated the title of Table 13, "14 x 14 mm package thermal resistance data"
• Added the new Section 3.1.2.2, 11 x 11 mm FCBGA package thermal resistance
• Updated the VDD_ANA_0P8, VDD_ARM_PLL_0P8, VDD_MIPI_0P8, VDD_USB_0P8,
VDD_DRAM_PLL_0P8, and USB1_VBUS in the Table 15, "Operating ranges for 14 x 14
mm package"
• Added the Table 16, "Operating ranges for 11 x11 mm package"
• Updated the title of Table 19, "Estimated power supply maximum currents for 14 x 14 mm
package"
• Added the Table 20, "Estimated power supply maximum currents for 11 x 11 mm package"
• Updated and added Low-V suspend mode data in the Table 21, "Chip power in different LP
mode for 14 x 14 mm package"
• Added the Table 22, "Chip power in different LP mode for 11 x 11 mm package"
• Updated and added a foot note in the Table 23, "The power supply states for 14 x 14 mm
package"
• Added the Table 25, "The power supply states for 11 x 11 mm package"
• Updated POR_B and added a note for Figure 3, "The power-up sequence for 14 x 14 mm
package"
• Updated the T13 descriptions in the Table 26, "Power-up sequence for 14 x 14 mm
package"
• Added the Figure 4, "The power-up sequence for 11 x 11 mm package" and Table 27,
"Power-up sequence for 11 x 11 mm package"
• Updated the titles of Figure 5, "The power-down sequence for 14 x 14 mm package" and
Table 28, "Power-down sequence for 14 x 14 mm package"
• Added the Figure 6, "The power-down sequence for 11 x 11 mm package" and Table 29,
"Power-down sequence for 11 x 11 mm package"
• Removed the Section, Power supplies constraints
• Updated the lock time and GPU values in the Table 30, "PLL electrical parameters"; added
the M7_ALT_PLL in the Table 30, "PLL electrical parameters"
• Fixed a typo in the Table 74, "i.MX 8M Nano 14 x 14 mm supplies contact assignments"
• Changed the name of TSENSOR_RES_EXT in the Table 75, "i.MX 8M Nano 14 x 14 mm
functional contact assignments"; updated the input/out status of GPIO1_IO07,
NAND_CE0_B, and NAND_RE_B in the Table 75, "i.MX 8M Nano 14 x 14 mm functional
contact assignments"
• Updated the names of H10, M1, and W22 in the Table 76, "14 x 14 mm, 0.5 mm pitch ball
map"
• Added the Section 5.2, 11 x 11 mm package information
• Updated LPDDR4 information of DRAM_AC14 and DRAMAC34 in the Table 80, "DDR pin
function list"

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
NXP Semiconductors 111

Downloaded from Arrow.com.

 Revision history

Table 81. Revision history (continued)

Rev.number Date Substantive change(s)

Rev. 0.1 03/2020 • Updated the Table, “Power supplies constraints”

Rev. 0 10/2019 • Initial version

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 1, 03/2021
112 NXP Semiconductors

Downloaded from Arrow.com.

 How To Reach Us Limited warranty and liability — Information in this document is believed to be accurate and reliable. However,
NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or
Home Page:
completeness of such information and shall have no liability for the consequences of use of such information. NXP
nxp.com Semiconductors takes no responsibility for the content in this document if provided by an information source outside
Web Support: of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special
or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related
nxp.com/support
to the removal or replacement of any products or rework charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate
and cumulative liability towards customer for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this
document, including without limitation specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the publication hereof.

Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities.
Customer is responsible for the design and operation of its applications and products throughout their lifecycles to
reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also
extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications.
NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow
up appropriately.

Customer shall select products with security features that best meet rules, regulations, and standards of the intended
application and make the ultimate design decisions regarding its products and is solely responsible for compliance
with all legal, regulatory, and security related requirements concerning its products, regardless of any information or
support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of
NXP products.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use
in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of
an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property
or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors
products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit
for the customer’s applications and products planned, as well as for the planned application and use of customer’s
third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on
any weakness or default in the customer’s applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using
NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V
may appear when operating this product, depending on settings and application. Customers incorporating or otherwise

Table continues on the next page...

Downloaded from Arrow.com.

 using these products in applications where such high voltages may appear during operation, assembly, test etc. of such
application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting
from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60
950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages.

Evaluation products —This product is provided on an “as is” and “with all faults” basis for evaluation purposes only.
NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or
statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a
particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with
customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special,
indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business,
business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the
product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.

Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all
damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates
and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred
by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product
or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent
permitted by applicable law, even if any remedy fails of its essential purpose.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail
in case of any discrepancy between the translated and English versions.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,EMBRACE,
GREENCHIP, HITAG, ICODE, JCOP, LIFE, VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE
PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX,
SMARTMX, STARPLUG, TOPFET, TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, CodeWarrior,
ColdFire, ColdFire+, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV, mobileGT, PEG, PowerQUICC,
Processor Expert, QorIQ, QorIQ Qonverge, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa,
Vybrid, Airfast, BeeKit, BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, Tower, TurboLink,
EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP B.V. All other product or service names
are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE,
Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP,
RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision,
Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The
related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved.
Oracle and Java are registered trademarks of Oracle and/or its affiliates. M, M Mobileye and other Mobileye trademarks
or logos appearing herein are trademarks of Mobileye Vision Technologies Ltd. in the United States, the EU and/or
other jurisdictions.

© NXP B.V. 2021. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: April, 2021

Document identifier: IMX8MNCEC

Downloaded from Arrow.com.