ISSN: 2277-3754

ISO 9001:2008 Certified

Modelling of Cuk Rectifier for Power Factor

Abstract— Cuk converter is a dc-dc converter; it can use for The analysis assumes that the converter is operating at a
step up and step down of voltage by varying duty ratio. cuk steady state in addition to the following assumptions: pure
converter have low ripples in output. cuk converter can use for sinusoidal input voltage, ideal lossless components, and all
power factor correction applications by operating discontinuous capacitors are large enough such that their switching voltage
mode, there switching occurs in zero values of current
ripples are negligible during the switching period Ts
.discontinuous means current approaches to zero, when supply
.Moreover, the output filter capacitor Co (Co 1 and Co 2 for
voltage and current are in phase ,power factor changes to unity. if
load is capacitive, output voltage have to buck still supply voltage topology 2) has a large capacitance such that the voltage
and current are In phase, that is unity power factor. across it is constant over the entire line period. During the
positive half cycle of line voltage, the first dc–dc Cuk circuit,
Index Terms— Bridgeless rectifier, Cuk converter, power L1–Q1–C1–Lo 1–Do 1 , is active through diode Dp which
factor correction (PFC), Discontinuous conduction mode connects the input ac source to the output. During the negative
(DCM). half cycle of line voltage, the second dc–dc Cuk circuit, L2–Q2
-C2–Lo 2–Do 2, is active through diode Dn , which connects the
I. INTRODUCTION input ac source to the output. The average voltage across
capacitor C1 during the line cycle can be expressed as follows:
Power supplies with active power factor correction (PFC)
techniques are becoming necessary for many types of
electronic equipment to meet harmonic regulations and
standards. Most of the PFC rectifiers utilize a boost converter
at their front end. Efficiency of conventional PFC scheme was
less due to significant losses in the diode bridge. Significant
conduction loss, caused by the forward voltage drop across
the bridge diode, considerably reduces the converter’s
efficiency, especially at a low line input voltage. In order to
maximize the power supply efficiency, research efforts are
directed towards designing of bridgeless PFC circuits, where
losses due to large number of semiconductors is reduced by
essentially eliminating the full bridge input diode rectifier. A Fig.1. Proposed Cuk Converter [1]
bridgeless PFC rectifier allows the current to flow through a
minimum number of switching devices compared to the
conventional PFC rectifier. Accordingly, the converter
conduction losses can be significantly reduced and higher
efficiency can be obtained, as well as cost savings. Recently,
several bridgeless PFC rectifiers have been introduced to Due to the symmetry of the circuit, analysis is carried out
improve the rectifier power density and/or reduce noise during the positive half cycle of the input voltage. Moreover,
emissions via soft-switching techniques or coupled magnetic the proposed rectifiers operation in Fig. 1 will be described
topologies. A bridgeless buck PFC rectifier was proposed in assuming that the three inductors are operating in DCM.
for many step-down applications. But, the input line current Operating the rectifier in DCM, have several advantages. The
cannot follow the input voltage around the zero crossings of main advantages includes natural near-unity power factor, the
the input line voltage; besides, the output to input voltage switches are turn ON at zero current, and the output diodes
ratio is limited to half. Also, buck PFC converter results in an (Do1 and Do2) are turned OFF at zero current. Thus, the
increased total harmonic distortion. turn-ON switching losses and the reverse recovery of the
output diodes are considerably reduced. Conversely, DCM
II. PROPOSED BRIDGELESS CUK PFC RECTIFIERS operation significantly increases the conduction losses due to
the increased current stress through circuit components. As a
Cuk converter is a dc-dc converter; it can step up and step result, this leads to one disadvantage of the DCM operation,
down the voltage according to the variation in duty ratio, which limits its use to low-power applications (<300 W).
= . Similar to the conventional Cuk converter, the circuit
operation in DCM can be divided into three distinct operating

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 ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 3, Issue 2, August 2013
stages during one switching period Ts. The topological stages and body diode of Q2 appear in parallel configuration to share
of cuk rectifier over a switching cycle can be briefly described the return current. A large portion of the return current will
as follows, Stage 1[t0, t1 ], [Fig. 2(a)]: This stage starts when pass through the diode that has a lower voltage drop. The
the switch Q1 is turned ON. Diode Dp is forward biased by the efficiency of the proposed converter can improved by using
inductor current iL 1 . As a result, the diode Dn is reverse biased synchronous rectification to turn ON the switch Q2 during the
by the input voltage. The output diode Do 1 is reverse biased positive half cycle of the input voltage, which eliminates its
by the reverse voltage (vac + Vo), while Do 2 is reverse biased body-diode conduction.
by the output voltage Vo . In this stage, the currents through
inductors L1 and Lo 1 increase linearly with the input voltage,
but the current flowing through inductor Lo 2 is zero due to the
constant voltage across C2 . The inductor currents of L1 and
Lo1 during this stage are given by,
diLn/dt = vac/Ln………….(1)
Accordingly, the peak current through the active switch Q1
is given by,
IQ1,pk = (Vm/Le )D1TS………………..(2)
Fig. 2. Topological stages over one switching period Ts[1]
Where Vm is the peak amplitude of the input voltage vac , D1 The Cuk converter offers several advantages in PFC
is the switch duty cycle, and Le is the parallel combination of applications, such as it is easy to implement in transformer
inductors L1 and Lo 1. Stage 2[t1, t2 ] [Fig. 2(b)]: This stage isolation, protection against inrush current occurring at
starts when the switch Q1 is turned OFF and the diode Do1 is start-up or overload current, lower input current ripple, and
turned ON simultaneously providing a path for the inductor less electromagnetic interference (EMI) associated with the
currents iL 1 and iLo1 . The diode Dp remains conducting to discontinuous conduction mode (DCM) topology.
provide a path for iL 1 . Diode Do 2 remains reverse biased .
during this interval. This interval ends when iDo1 reaches zero III. CONVERTER DESIGN
and Do 1 becomes reverse biased. Note that the diode Do 1 is Let,
switched OFF at zero current. The current through inductor Input voltage, Vac= 100Vrms,
L1 and Lo 1 during this stage can be, Output V0=48V,
represented as follows: Power, P=150W
P=V×I……………….. (5)
(diLn/dt)= − Vo/Ln,………….(3) 150=48×I
Therefore, output current I=3.125A
Stage 3[t2, t3 ] [Fig. 2(c)]: During this interval, only the V0=I×R,………………(6)
diode Dp conducts to provide a path for iL 1 . Accordingly, 48=3.125×R,
the inductors in this interval behave as constant current R=15.34 Ω
sources. Hence, the voltage across the three inductors is zero. Select Switching frequency, F=4 kHz
The capacitor C1 is being charged by the inductor current iL 1 Output voltage ripple should be <1%
This period ends when Q1 is turned ON. By applying inductor ∆iL1<10%IL1
volt-second across L1 and Lo 1 , the normalized length of the ∆Vc1<5%Vc1
second stage period can be expressed as follows:
∆iL1= ………………. (7)
D2 = (D1/M) sin ωt ……………..(4)
∆iL2= (1-D) Vo/ (F.L2)……………….(8)
where ω is the line voltage angular frequency, and M is ∆Vc1 = (D.Vd id) / (Vo.C.F)…………..(9)
defined at the voltage conversion ratio (M = Vo /Vm). Since From equation (7) ,(8) and (9) gives the values of
the diode Dp conducts throughout the entire switching period, inductance and capacitance,
the average voltage across C2 is equal to the output voltage L1= L2=1mH
Vo . Due to this, a negligible ac current will flow through C2 L01=L02=22μH
and Lo 2 . The current flowing through L2 during the positive C1=C2=1μF
half cycle of the input voltage is equal to the negative current
through the body diode of Q2 . It should be noted that the Cout=12000μF
body diode of the inactive switch Q2 is always conducting Basic block diagram of cuk converter for power factor
current during the positive half cycle of the input voltage. The correction is shown in fig.3. The block diagram comprises,
reason is due to the low impedance of the input inductors (L1 rectifier, cuk converter, inverter for converting dc into ac
and L2 ) at the line frequency. Therefore, the input diode Dp before fed into loads. A PFC controller is used to sense the

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 ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 3, Issue 2, August 2013
load voltage and current variations and control the switching
pulses to cuk accordingly.

Fig 6.Output voltage and current waveform

Fig.3. Block diagram for power factor correction

IV. SIMULATION MODEL AND RESULTS

Fig.7. (a) source voltage and current, (b) Vc1 & VC2,
(c) VQ1& VQ2, (d) IL1 & IL2, (e) IL01 & IL02

V. CONCLUSION
The single-phase ac–dc bridgeless rectifiers based on Cuk
topology are presented and discussed. The validity and
Fig.4.Simulation model performance of the proposed topology was verified by
Simulated waveforms of proposed converter is shown in Simulation. Since conduction and switching losses are less,
figures. Waveforms shown below are corresponds to the the proposed topology can further improve the conversion
converter when operating in discontinuous mode of operation. efficiency when compared with the conventional Cuk PFC
rectifier.

VI. ACKNOWLEDGMENT
We would like to thank the management, principal, HOD
(EEE) and other staff members of federal institute of science
and technology, Angamaly for their support and guidance in
carrying out this project work.

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Fig.5.Input voltage and Current Waveforms

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 ISSN: 2277-3754
ISO 9001:2008 Certified
International Journal of Engineering and Innovative Technology (IJEIT)
Volume 3, Issue 2, August 2013
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