HUF75545P3, HUF75545S3S

Data Sheet October 2013

N-Channel UltraFET Power MOSFET

80 V, 75 A, 10 mΩ
Packaging Features
JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance
SOURCE DRAIN - rDS(ON) = 0.010Ω, VGS = 10V
DRAIN (FLANGE)
GATE • Simulation Models
- Temperature Compensated PSPICE® and SABER™
GATE
Electrical Models
SOURCE
- Spice and SABER Thermal Impedance Models
DRAIN - www.fairchildsemi.com
(FLANGE)
HUF75545P3 HUF75545S3ST • Peak Current vs Pulse Width Curve
• UIS Rating Curve

Symbol Ordering Information

D
PART NUMBER PACKAGE BRAND
HUF75545P3 TO-220AB 75545P
G HUF75545S3ST TO-263AB 75545S

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified

HUF75545P3,
HUF75545S3ST UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 80 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 80 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Drain Current
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 75 A
Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 73 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Figure 4
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 270 W
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 80 - - V

Zero Gate Voltage Drain Current IDSS VDS = 75V, VGS = 0V - - 1 µA

VDS = 70V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V

Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 0.0082 0.010 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case RθJC TO-220 and TO-263 - - 0.55 oC/W

Thermal Resistance Junction to RθJA - - 62 oC/W

Ambient

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time tON VDD = 40V, ID = 75A - - 210 ns

VGS = 10V,
Turn-On Delay Time td(ON) RGS = 2.5Ω - 14 - ns

Rise Time tr - 125 - ns

Turn-Off Delay Time td(OFF) - 40 - ns

Fall Time tf - 90 - ns

Turn-Off Time tOFF - - 195 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 40V, - 195 235 nC
ID = 75A,
Gate Charge at 10V Qg(10) VGS = 0V to 10V Ig(REF) = 1.0mA - 105 125 nC
(Figure 13)
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 6.8 8.2 nC

Gate to Source Gate Charge Qgs - 15 - nC

Gate to Drain “Miller” Charge Qgd - 43 - nC

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V, - 3750 - pF

f = 1MHz
Output Capacitance COSS (Figure 12) - 1100 - pF

Reverse Transfer Capacitance CRSS - 350 - pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 75A - - 1.25 V

ISD = 35A - - 1.00 V

Reverse Recovery Time trr ISD = 75A, dISD/dt = 100A/µs - - 100 ns

Reverse Recovered Charge QRR ISD = 75A, dISD/dt = 100A/µs - - 300 nC

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

Typical Performance Curves

1.2 80
POWER DISSIPATION MULTIPLIER

1.0

ID, DRAIN CURRENT (A)

60
0.8
VGS = 10V
0.6 40

0.4
20
0.2

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
THERMAL IMPEDANCE

0.05
ZθJC, NORMALIZED

0.02
0.01

PDM
0.1

t1
t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

2000
TC = 25oC
FOR TEMPERATURES
1000 ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)

CURRENT AS FOLLOWS:

I = I25 175 - TC
150
VGS = 10V

100 TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

Typical Performance Curves (Continued)

600 600
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

IAS, AVALANCHE CURRENT (A)

If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
ID, DRAIN CURRENT (A)

100
100µs
STARTING TJ = 25oC
100

OPERATION IN THIS 1ms

10 AREA MAY BE
LIMITED BY rDS(ON)
10ms STARTING TJ = 150oC
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1 10
1 10 100 200 0.001 0.01 0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY

150 150
PULSE DURATION = 80µs VGS = 20V VGS = 7V
DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 6V
120 VDD = 15V
120
ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A)

90 90 VGS =5V

60 60
TJ = 175oC

30 30 PULSE DURATION = 80µs

TJ = 25oC TJ = -55oC DUTY CYCLE = 0.5% MAX
TC = 25oC
0 0
2 3 4 5 6 0 1 2 3 4
VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

2.5 1.2
PULSE DURATION = 80µs VGS = 10V, ID = 75A VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE

DUTY CYCLE = 0.5% MAX

THRESHOLD VOLTAGE

2.0 1.0
NORMALIZED GATE
ON RESISTANCE

1.5 0.8

1.0 0.6

0.5 0.4
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
RESISTANCE vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

Typical Performance Curves (Continued)

1.2 10000
NORMALIZED DRAIN TO SOURCE

ID = 250µA
CISS = CGS + CGD
BREAKDOWN VOLTAGE

C, CAPACITANCE (pF)
1.1
COSS ≅ CDS + CGD

1.0 1000

0.9
CRSS = CGD

VGS = 0V, f = 1MHz

0.8 100
-80 -40 0 40 80 120 160 200 0.1 1 10 80
TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

10
VGS , GATE TO SOURCE VOLTAGE (V)

VDD = 40V

WAVEFORMS IN
2 DESCENDING ORDER:
ID = 75A
ID = 35A
0
0 30 60 90 120
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+ VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0
0.01Ω
tAV

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

VDS
RL VDD Qg(TOT)

VDS
VGS = 20V

VGS Qg(10)
+
VDD
VGS VGS = 10V
-

DUT VGS = 2V
Ig(REF) 0
Qg(TH)
Qgs Qgd

Ig(REF)
0

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD 10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

PSPICE Electrical Model

.SUBCKT HUF75545 2 1 3 ; rev 21 May 1999

CA 12 8 5.4e-9
CB 15 14 5.3e-9
CIN 6 8 3.4e-9

DBODY 7 5 DBODYMOD
LDRAIN
DBREAK 5 11 DBREAKMOD DPLCAP 5 DRAIN
DPLCAP 10 5 DPLCAPMOD 2
10
RLDRAIN
EBREAK 11 7 17 18 87.4 RSLC1
51 DBREAK
EDS 14 8 5 8 1 +
EGS 13 8 6 8 1 RSLC2
5
ESG 6 10 6 8 1 51
ESLC 11
EVTHRES 6 21 19 8 1 -
EVTEMP 20 6 18 22 1 50 +
-
RDRAIN 17 DBODY
6 EBREAK 18
ESG 8
IT 8 17 1
+ EVTHRES 16
-
+ 19 - 21
LDRAIN 2 5 1.0e-9 LGATE EVTEMP MWEAK
8
LGATE 1 9 5.1e-9 GATE RGATE +
18 - 6
LSOURCE 3 7 4.4e-9 1 22 MMED
9 20
RLGATE MSTRO
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD LSOURCE
CIN SOURCE
MWEAK 16 21 8 8 MWEAKMOD 8 7 3
RBREAK 17 18 RBREAKMOD 1 RSOURCE
RDRAIN 50 16 RDRAINMOD 4.80e-3 RLSOURCE
RGATE 9 20 0.87 S1A S2A
12 RBREAK
RLDRAIN 2 5 10 13 14 15
17 18
RLGATE 1 9 51 8 13
RLSOURCE 3 7 44
S1B S2B RVTEMP
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3 13 CB 19
CA
RSOURCE 8 7 RSOURCEMOD 1.6e-3 + + 14 IT -
RVTHRES 22 8 RVTHRESMOD 1 6 5 VBAT
RVTEMP 18 19 RVTEMPMOD 1 EGS EDS +
8 8
- - 8
S1A 6 12 13 8 S1AMOD 22
S1B 13 12 13 8 S1BMOD RVTHRES
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320),3))}

.MODEL DBODYMOD D (IS = 3.6e-12 RS = 2.1e-3 TRS1 = 1.5e-3 TRS2 = 5.1e-6 CJO = 4.6e-9 TT = 3.3e-8 M = 0.55)
.MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 0 TRS2 = -1.8e-5)
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10 VJ = 1 M = 0.8)
.MODEL MMEDMOD NMOS (VTO = 3.04 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.87)
.MODEL MSTROMOD NMOS (VTO = 3.5 KP = 105 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.7 )
.MODEL RBREAKMOD RES (TC1 = 1.3e-3 TC2 = -1e-6)
.MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2.8e-5)
.MODEL RSLCMOD RES (TC1 = 1.53e-3 TC2 = 2e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.5)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

SABER Electrical Model

REV 21 may 1999
template huf75545 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 3.6e-12, cjo = 4.6e-9, tt = 3.3e-8, m = 0.55)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 4.8e-9, is = 1e-30, vj=1.0, m = 0.8 )
m..model mmedmod = (type=_n, vto = 3.04, kp = 6, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1) LDRAIN
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3) DPLCAP 5 DRAIN
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5) 2
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0.5) RLDRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.5) RSLC1
51 RDBREAK
c.ca n12 n8 = 5.4e-9 RSLC2
72 RDBODY
c.cb n15 n14 = 5.3e-9 ISCL
c.cin n6 n8 = 3.4e-9
50 DBREAK
-
d.dbody n7 n71 = model=dbodymod RDRAIN 71
6
d.dbreak n72 n11 = model=dbreakmod ESG 8 11
d.dplcap n10 n5 = model=dplcapmod + EVTHRES 16
+ 19 - 21
LGATE EVTEMP MWEAK
i.it n8 n17 = 1 8 DBODY
GATE RGATE + 18 - 6
1 MMED EBREAK
l.ldrain n2 n5 = 1e-9 9 20
22 +
l.lgate n1 n9 = 5.1e-9 RLGATE MSTRO 17
l.lsource n3 n7 = 4.4e-9 18 LSOURCE
CIN
8
- SOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u 7 3
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u RSOURCE
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RLSOURCE
S1A S2A
res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -1e-6 12 RBREAK
13 14 15
res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6 17 18
8 13
res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5
S1B S2B RVTEMP
res.rdrain n50 n16 = 4.8e-3, tc1 = 9e-3, tc2 = 2.8e-5
res.rgate n9 n20 = 0.87 13 CB 19
CA
res.rldrain n2 n5 = 10 + + 14 IT -
res.rlgate n1 n9 = 51 6 5 VBAT
res.rlsource n3 n7 = 44 EGS EDS +
8 8
res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 2e-5 - - 8
res.rslc2 n5 n50 = 1e3 22
res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e-6 RVTHRES
res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7
res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5

spe.ebreak n11 n7 n17 n18 = 87.4

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3))
}
}

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

SPICE Thermal Model th JUNCTION

REV 21 May 1999

HUF75545T

CTHERM1 th 6 6.4e-3 RTHERM1 CTHERM1

CTHERM2 6 5 3.0e-2
CTHERM3 5 4 1.4e-2
CTHERM4 4 3 1.6e-2 6
CTHERM5 3 2 5.5e-2
CTHERM6 2 tl 1.5

RTHERM1 th 6 3.2e-3 RTHERM2 CTHERM2

RTHERM2 6 5 8.1e-3
RTHERM3 5 4 2.3e-2
RTHERM4 4 3 1.3e-1 5
RTHERM5 3 2 1.8e-1
RTHERM6 2 tl 3.8e-2

RTHERM3 CTHERM3

SABER Thermal Model

SABER thermal model HUF75545T
4
template thermal_model th tl
thermal_c th, tl
{
RTHERM4 CTHERM4
ctherm.ctherm1 th 6 = 6.4e-3
ctherm.ctherm2 6 5 = 3.0e-2
ctherm.ctherm3 5 4 = 1.4e-2
ctherm.ctherm4 4 3 = 1.6e-2 3
ctherm.ctherm5 3 2 = 5.5e-2
ctherm.ctherm6 2 tl = 1.5
RTHERM5 CTHERM5
rtherm.rtherm1 th 6 = 3.2e-3
rtherm.rtherm2 6 5 = 8.1e-3
rtherm.rtherm3 5 4 = 2.3e-2
rtherm.rtherm4 4 3 = 1.3e-1 2
rtherm.rtherm5 3 2 = 1.8e-1
rtherm.rtherm6 2 tl = 3.8e-2
} RTHERM6 CTHERM6

tl CASE

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1

 HUF75545P3, HUF75545S3S

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FETBench™
SyncFET™ VoltagePlus™
FPS™
XS™

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are 2. A critical component in any component of a life support, device, or
intended for surgical implant into the body or (b) support or sustain life, system whose failure to perform can be reasonably expected to cause
and (c) whose failure to perform when properly used in accordance with the failure of the life support device or system, or to affect its safety or
instructions for use provided in the labeling, can be reasonably effectiveness.
expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is
committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.

PRODUCT STATUS DEFINITIONS

Definition of Terms
Datasheet Identification Product Status Definition
Datasheet contains the design specifications for product development. Specifications
Advance Information Formative / In Design
may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later

Preliminary First Production date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to

No Identification Needed Full Production
make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild

Obsolete Not In Production Semiconductor. The datasheet is for reference information only.
Rev. I66

©2002 Fairchild Semiconductor Corporation HUF75545P3 / HUF75545S3S Rev. C1