Fig. 5.24 Driv area, Moreo’ an inverter to meet this need oc ae ihe minimum and since length Z cannot be reduced below mice capaci Lx W becomes significant and. cot vole which can take place at ca tio of chang cele stage by a width factor fas shown in Fig, 524 (Show eee ae Clearly, as the width factor increases, 5° the capacitive seat thea e increases, and the area occupied increases al80. Equally cle mae = whic increases (that is, the value of f) will influence the number NV of s oe aa to drive a particular value of C,. Thus, an optimum solution must ght ase treatment is attributed to Mead and Conway). ‘i s With large f, N decreases but delay per stage increases. For 4:1 nMOS im dela ef etoe at where AV, indicates logic 0 to, ” ae ioe *|ransion and W/iy indicates or=4/tfor VVin cupies a | logic | to 0 transition of Vin Therefore, total delay per nMOS pair = 5+. A similar treatment yields delay per Now let = op Oc, ‘A so that the choice of f and N are interdependent. st ‘We now need to determine the value of f, whi. ill minimize verall , which will i 7 value of y and from the definition of y ee i In(y) = N In(f) » That is: dee 0) cian _a p . Gate Level Design O 9 | delay = > SIT=25NFE hogy re! Say ps inal case M{CMos) delay “Nt no) ng)! be shown that total delay jg Ren Y is minim fs , cach stage gh al ity uns); that iS, CAH stage should je ima umes wales to CMOS as well as nMOg inv oxiiate 2.7% he ale © (base of natural loge. hus, assuming that f= e, we faye animes Number Of stages y= Ing) i overall delay fy Neven: ty=2.5enq (2Mos) SF 3SeNe “" (CMos) a= [25(v—1)4 Jet (aos) 4 =[35(W-1)42]ee (euco8 or \ =[25(W=1)+4]et(nMos) ta =[35(N-1) +5]er et ia $3.2 Super Buffers 1 2 The asymmetry of the conventional inverter is clearly undesirable, and gives rise to significant delay problems when an inverter is used to drive more significant capacitive loads. A common approach used in nMOS technology to alleviate this effect is to make use of ‘Soper buffers as in Figs. 5.25 and 5.26. An inverting type is shown in Fig. 5.25; considering a positive going logic transition Vin ithe input, it will be seen that the inverter formed by 7; and 7; is turned on and, thus, ihe gate of 7; is pulled down toward 0 volt with a small delay. Thus, 73 is cut off while Ti(the gate of which is also connected to Vix) is tuned on and the output is pulled down ‘Mickly, 2160 © VLSIDesign mas Fig. 5.25 Inverting type nMOS buffer. ob ay ; rc: Mn 7 se Vn A Fae ES aOR TN Fig. 5.26 Non-inverting type nMOS super butter. ‘Now consider the opposite transition: when to rise quickly to Vpp, Thus, as T; is also Yn drops to 0 volt, then the gate tumed off by Vin, Ts is made toc Vs will increase the current and thus rei output, so that more symmetrical transitions are achieved, The corresponding non-inverting nMOS super buffer circuit is given at Fi ‘matters in perspective, the structures shown When realized in 5 um technol » May be used, but here only briefly, ner and are mentioned3 picMOS Drivers Gite Level Design 464 3 availability of bipolar transistors in Bic) Bac transistor bet 88 the output stage tna logy presents the Possibility of using bP that bipolar transistors haye Lansconductance et 4 logic gate circuits, We already greatly superior to those of Mog. devices, aE, a cutrenUarca 1/4 characteristics that ei areas in aad - ONS Hah Chrent drive capabilities for jar transistors have an’ ¢x, ne Bipol 3 to emitter voltage 7, TE oe dependence of ‘he ‘output! current 1, on the out voltae ayinaies MOS trang tH device can be ose ‘with much Glas transistors have a re tet mee sii switch relatively ‘arge currents, pe smaller input voltage swings, Only q small bake eae 2) peared sgching 2 2 9 one point to consider is the possible effect Of temperature 7: on the required input voltage fe Although Vie is logarithmically dependent on base width Wp, doping level Nj, electron apilty Hw and collector current J. it Only linearly dependent en T: This mea that there iso difficult in matching 1, Values 8eTOSs a circuit, spread Over an area on chip, as the tem- jure differences across a chip Will not be sufficient to cause more than a few millivolts of giference in Vbe between any two bipolar transistors, The switching performance of a transistor dri ving a capacitive load may be visualized ini- jally from the simple model given in Fig. 5.27, r Note: The time necessary to change the Output voltage by an amount that is equal to the {nput change is given by At=Cy/gm where gm = device transconductance, Yoo R Vou Fig, 5.27 Diving abit Blas sills ~EE 62 ViSTDesiOn may be shows that the time 4 ‘equal to the input voltage Vn '® given” by 3 oy where gy is the transconductance of the bi Clearly, since the bipolar A more exacting appraisal components: 1, Ty — an initial tit of the bi me mecessary 1° chat the Bic! transistor. Typically, for zi in the region of 2 08 similar eS a BIC Id reveal @ fc Be pea 5 matter of interest, 2 compat GaAs driver is around 50— i i crane 2. 7 — the time taken to charge the output load capacitance Ct ® it will factor of Rj where Hye is the bipo time ig less forthe bipolar driver by ® Although the bipolar transistor has @ higher value of Zim 7, is smaller beca charging rate as discussed. iM The combined effect of Th, and 7, is represented in Fig. 5.28 and it will be is a critical value of load capacitance Cryer) below which the BiCMOS driver comparable CMOS driver. é CMOS slope = Vig \ T, ¢, Leriy Load capacitance C, Ei Fig. 5.28 Delay estimation, _—_—_ ii” g lengths of polysilicon sho, 10n8 ively highiRy Value of the ed oni ne rel Polyg; ico yap oF Fs other than fOr very g a pp? 6, MAN digg ih these restrictions in ming egy Wi s sransistors are much higher than eS PSTaly th. wi Janger of any problem due Gate Level Design QO 2s ¥ afer care fy) Consideration because of yer, Polysiticon 18 Unsuitable for routing, 6 that the Fesistan ted te stances associate 10 voltage dette Witing resistance, 4o that there is no ; effects between wiring and transistor {s must also be Gi acitive 4 6 Carefully cone: + Care vired and Particularly in relation ies Mirticularly where fast signal lines we. Diffusion (or ActiVe) areas hay, eee of Ay © Foltvely gr Pe having relatively high vee, ire harder to drive jn Consequence, Char High Values. of Capacitance to substrate cael architectures and © shating fam © Catefil ye MY Als0 cause problems in cen t re | regions, the signal on a Wire on tated ag gms Over small equipoten- ti region the dclay age With signal propaga # etca at all points. Witea ys and with signal delays in gy Scare is small in comparison with gate SSMS connected by the wires, d the wires in a MOS system cag be m he z ‘odelled as simple capacitors, This concept leads to lishment of electrical rules (Buidetines) fo, i Es a Communication paths (wires) as given in w = factors Sct out in Tables 5,2 and 5.3 help to put Matters in. perspectives, Table §.2 Electrical tules = Maximumn length of communication wire Dambels-tated (5) Nea (oy jim-based (1.2 jm) Layet * Chip wide Chip wide Chip wide peal 2,0002, ONA NA a oan 400 um aus eisilico ia um fess (active) 202 100 um Taking account of peripheral and area capacitances. NA = not applicable Ming 8 Table 5.3 Choice of layers Layer E S a — capability without large voltage drop ... Mel Low eu use for power distribution and global signals. long wires are pos- st RC product. Reasonably wee Es Low He Ee ie ae MMOS Drogtate?. g ge ‘oduct is moderate; high IR i High aa ay hivilicon ‘high C. Hence, hard to drive. i Moderate IR drop but high Difusion (active) Moderate HighGate Level Design 455 — | [ta 1OkQR, 4 Fig. 5.21 Minimum ste cos \nverter pair delay. 3 AMore Formal Estimation of CMOS Inverter Delay 2. {0S inverter, in general, either charges or disch ACM atBes @ capacitive load C,, and rise-time |-time fy can be estimated from the following simple analysis, orf Estimation : . Ae we assume that the p-device stays in saturati b ee d capacitor C,. The circuit may then be modelled ee p-transistor is given by ion for the entire charging period as in Fig. 5.22. The saturation cur- for ot B, (Ves Wolf Tasp = ee ee tude is approximately constant, we have This current charges C, and, since its a pe 4 ono 4 ‘ # . *¢ x tituting for Jas and rearranging, we have 3 ‘ Subst “ ; = — % Bp (Yas -Yol) Po YY + py $0 that : % wg = 1, when Vou = + Vop, ‘We now assume that ¢ = f, w1 A : ‘ ee ye Bp (Yoo -\'ol) With |V,|= 0.27 pp, then - ra Bp Yoo156 DVIS Design Vow a | G sme — Vss Fig. 9.22 pise-time model. This result compares reasonably well with a more detailed analysis in which | is divided, more correctly, into two parts: (1) saturation and (2) resistive Fegion Fall-Time Estimation ‘ Similar reasoning can be applied to the discharge of Cz through the n-transistor, 5.23. Making similar assumptions, we model in this case is given as Fig. 7p : es ae 0 Te fall-time: ss, , gh a on G 2 ‘. fs Fig. §.23 Fall-ime model.