CHAPTER 2 and 3

CMOS NAND Gate

A B Y
0 0
0 1 Y
1 0 A
1 1
B
CMOS NAND Gate

A B Y
0 0 1 ON ON
0 1 Y=1
1 0
A=0 OFF
1 1
B=0 OFF
CMOS NAND Gate

A B Y
0 0 1 OFF ON
0 1 1 Y=1
1 0
A=0 OFF
1 1
B=1 ON
CMOS NAND Gate

A B Y
0 0 1 ON OFF
0 1 1 Y=1
1 0 1
A=1 ON
1 1
B=0 OFF
CMOS NAND Gate

A B Y
0 0 1 OFF OFF
0 1 1 Y=0
1 0 1
A=1 ON
1 1 0
B=1 ON
CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate
 Y is pulled low if ALL inputs are 1
 Y is pulled high if ANY input is 0

Y
A
B
C
CMOS Gate Design
 A 4-input CMOS NOR gate

A
B
C
D
Y
Complementary CMOS
 Complementary CMOS logic gates

nMOS pull-down network

pMOS pull-up network pMOS
pull-up

a.k.a. static CMOS

network
inputs
output

nMOS
pull-down
network

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)
 Series and Parallel

a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

a a a a

 nMOS: 1 = ON
a
0 0 1 1
g1
g2
0 1 0 1

 pMOS: 0 = ON (b)
b b
ON OFF
b
OFF
b
OFF
b

 Series: both must be ON a a a a a

g1 g2 0 0 0 1 1 0 1 1

 Parallel: either can be ON b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
 Conduction Complement
 Complementary CMOS gates always produce 0 or 1

 Ex: NAND gate

 Series nMOS: Y=0 when both inputs are 1
 Thus Y=1 when either input is 0
 Requires parallel pMOS Y
A
B

 Rule of Conduction Complements

 Pull-up network is complement of pull-down
 Parallel -> series, series -> parallel
Compound Gates

 Compound gates can do any inverting

function
Y = ( A • B) + (C • D)
 Ex: AND-AND-OR-INV (AOI22)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
Example: O3AI


Y = ( A + B + C) • D
Example: O3AI


Y = ( A + B + C) • D

A
B
C D
Y
D
A B C
We must first complement this equation, and then apply
DeMorgan’s Theorem (several times!).

Y=A+B+AC
Y=A+B+AC

(
= A+B AC )( )
= (A + B )(A + C )

= (A + B )(A + C )
= AA + AC + BA + BC
= A (A + B + C ) + BC
= A + BC

Logically, this result says:

Y is low if A is high, OR
if both B AND C are high.

We can thus realize this logic with the following NMOS PDN:
 Y

A B

PDN C

Y = A + BC

Step2: Design the PUN

First, we must rewrite the Boolean function as:

(
Y = f A, B,C )
In other words, write the un-complemented output in terms
of complemented inputs.
Again, using DeMorgan’s Theorem:

Y = A + B + AC
= AB + A C

(
= A B+ C )
Logically, this result says:

Y is high if A is low AND

either B OR C are low.

We can thus realize this logic with the following PMOS PUN:
 VDD

B C

PUN Y

(
Y = A B+ C )

Thus, the entire CMOS realization is:

 VDD

B C

Y=A+B+AC

A B

C
11/14/2004 Example Another CMOS Logic Gate Synthesis.doc 1/4

Example: Another CMOS

Logic Gate Synthesis
Now let’s design a gate that realizes this Boolean algebraic
expression:
(
Y = A+ B C )
Step 1: Design PDN

First, let’s rewrite Boolean expression as Y = f (A,B,C):

( )
Y = A +B C

Y = (A +B)C

( )
Y = A+B +C

Y = AB +C

Q: Yikes! We cannot write this expression explicitly in terms

of uncomplemented inputs A, B, and C ! The input C appears as
C in the expression. What do we do now?

A: An easy problem to solve! We can essentially make a

substitution of variables:
C= C
11/14/24

And thus:
Y = AB+ C

Therefore, the inputs to this logic gate should be A, B, and C’

(i.e, A, B, and the complement of C ).

Note that this Boolean expression “says” that:

“The ouput is low if either,A AND B are both high, OR C’ is

high”

Of course another way of “saying” this is:

“The output is low if either A AND B are both high, OR C is

low”

The PDN is therefore:

Y
Y = AB + C 
= AB + C

C = C
B
Step 2: Design the PUN

Note we have as similar problem as before—the expression

for Y cannot explicitly be written in terms of complemented
inputs A, B, and C:
(
Y = A+ B C )
Note we can again solve this problem by using the same
substitution of variable C:

C= C
C= C

Therefore:
( )
Y = A + B C

= (A + B)C

This expression “says” that:

“The output will be high if, either A OR B are low, AND C’ is

low”

Which is equivalent to saying:

“The output will be high if, either A OR B are low, AND C is

high”

The CMOS digital logic device is therefore:

 VDD

A B

( )
Y = A+ B C 

C = C = (A + B )C

= (A + B )C
Y

C = C
B
MOS Capacitor
Example with an NMOS capacitor

 Gate and body form MOS capacitor

 Operating modes
polysilicon gate
Vg < 0
silicon dioxide insulator
+
- p-type body
 Accumulation
(a)

0 < V g < Vt
depletion region
+
-
 Depletion
(b)

V g > Vt
inversion region
+
- depletion region

 Inversion
(c)
Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs

Vg
 Vgs = Vg – Vs
+ +
 Vgd = Vg – Vd Vgs Vgd
- -
 Vds = Vd – Vs = Vgs – Vgd
Vs Vd
- +
Vds
 Source and drain are symmetric diffusion terminals
 However, Vds  0

 NMOS body is grounded. First assume source may be grounded or may

be at a voltage above ground.
 Three regions of operation
 Cutoff

 Linear

 Saturation
SIMPLIFIED MOSFET I-V EQUATIONS

Cut-off: VGS< VT
ID = IS = 0

Triode: VGS>VT and VDS < VGS-VT

ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS2]

Saturation: VGS>VT and VDS > VGS-VT

ID = 1/2kn’(W/L)(VGS-VT)2

where kn’= (electron mobility)x(gate capacitance)

= n(ox/tox) …electron velocity = nE

and VT depends on the doping concentration and gate

material used.
 MOSFET Scaling
 Packing Density of MOSFETs in the chip should be as high as possible,
the sizes of the transistors are as small as possible.
 The reduction of the sizes is commonly referred as Scaling
 The operational characteristics of the MOS will change with the
reduction of its dimensions.
 There are two basic types of size-reduction strategies: full scaling (also
called constant-field scaling) and constant voltage scaling.
 The scaling reduces the total silicon area, thereby increasing the
overall functional density of the chip.
 To describe device scaling, we introduce a constant scaling factor S >
1. All horizontal and vertical dimensions of the large-size transistor are
then divided by this scaling factor to obtain the scaled device.
 Table below shows the recent history of reducing feature sizes for the
typical CMOS gate-array process.
MOSFET Scaling
It is easy to recognize that the scaling
of all dimensions by a factor of S > 1
leads to the reduction of the area
occupied by the transistor by a factor
of S2
Full Scaling (Constant-Field
Scaling
This scaling option attempts to preserve the
magnitude of internal electric fields in the
MOSFET, while the dimensions are scaled
down by a factor of S. To achieve this goal,
all potentials must be scaled down
proportionally, by the same scaling factor.
Note that this potential scaling also affects
the threshold voltage
 While the full scaling strategy dictates that the
Constant-Voltage Scaling
power supply voltage and all terminal voltages
be scaled down proportionally with the device
dimensions, the scaling of voltages may not be
very practical in many cases. In particular, the
peripheral and interface circuitry may require
certain voltage levels for all input and output
voltages, which in turn would necessitate
multiple power supply voltages and
complicated level shifter arrangements. For
these reasons, constant-voltage scaling is
usually preferred over full scaling.
Constant field scaling Constant Voltage scaling
 nMOS Operation
Slide
31
Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

Vgsn = Vin
VDD

Vdsn = Vout Idsp

Vin Vout
Idsn
 pMOS Operation
Slide
39 Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vdsp > Vgsp – Vtp
Vout < Vin - Vtp VDD
Vout > Vin - Vtp
Idsp
Vin Vout
Idsn
Vgsp = Vin - VDD Vtp < 0

Vdsp = Vout - VDD

 Operating Regions
Slide
41  Revisit transistor operating regions

Region nMOS pMOS

A Cutoff Linear
VDD

B Saturation Linear A B

Vout
C Saturation Saturation C

D Linear Saturation
E Linear Cutoff D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin
 Operating Regions
Slide
42
 Operating Regions
Slide
43
 Operating Regions
Slide
44
 Operating Regions
Slide
45
 Operating Regions
Slide
46
 Noise Margins
Slide
47
 How much noise can a gate input see before it does not
recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND
 Delay-Time Definitions
 The propagation delay times and determine the input-to-output signal delay during the high-
to-low and low-to-high transitions of the output, respectively.
 By definition, is the time delay between the V50% -transition of the rising input voltage and the V50% -
transition of the falling output voltage.
 Similarly , is defined as the time delay between the V50% -transition of the falling input voltage
 and the V50%- transition of the rising output voltage.

 To simplify the analysis becomes the time required for

 the output voltage to fall from VOH to the V50% level.
 becomes the time required for the output voltage to
 rise from VOL to the V50% level. The voltage point V50%
 is defined as follows

 ….(2)
 Continue….
 Thus, the propagation delay times …..(3)

 The average propagation delay of the inverter characterizes the average time required for the input
signal to propagate through the inverter.
 …..(4)

 The rise time is defined here as the time required

 for the output voltage to rise from the V10% level to V90%
 level.
 The fall time is defined here as the time
 required for the output voltage to drop from
 the V90% level to V10% level.

 …(5)
 Propagation Delay: First-Order Analysis
 One way to compute the propagation delay of the inverter is to integrate the capacitor (dis)charge current.
with i is the (dis)charging current, V the voltage over the capacitor, and v1 and v2 the
 Initial and final voltage. ….(9)

 An exact computation of this equation is intractable, as both CL(v) and i(v) are nonlinear functions of V.
 An expression for the average on-resistance of the MOS transistor.
 This scenario is plotted in for the case of an NMOS discharging a capacitor from VDD to VDD/2.

Rohit Lorenzo, VIT-AP

 Continue……
 we can derive the value of the equivalent resistance, which averages the resistance of the device over the
interval
 …..(10)

 Deriving the propagation delay of the resulting circuit is now straightforward, and is nothing more than the
analysis of a first-order linear RC-network. the propagation delay of such a network for a voltage step at the
input is proportional to the time-constant of the network.
 …..(11)
 Similarly, we can obtain the propagation delay for the low-to-high transition
 …..(12)
 Reqp and Reqn the equivalent on-resistance of the PMOS and NMOS transistor. The overall propagation
delay of the inverter is defined as the average of the two values.
 …..(13)
 Continue……
 Combining Eq. (10) and Eq. (11), and assuming for the time being that the channel- length modulation factor
l is ignorable, yields the following expression for tpHL .
 ……(14)

 In the majority of designs, the supply voltage is chosen high enough so that VDD>>VTn+VDSATn/2 . Under
these conditions, the delay becomes virtually independent of the supply voltage .
 ……(15)

 From the above analysis we can plot the propagation delay

 of the inverter as a function of the supply voltage.
 Problem 2
 Q ) For a supply voltage of 2.5 V, the normalized on-resistances of NMOS and PMOS transistors equal
13kΩ and 31kΩ, respectively. From the layout, we determine the (W/L) ratios of the transistors to be 1.5 for
the NMOS, and 4.5 for the PMOS. capacitor 6.1 fF (nmos) and 6.0 fF (PMOS). Calculate delay?

 Solution

 Propagation Delay from a Design Perspective
 We deduce that the propagation delay of a gate can be minimized in the following ways
 Reduce CL : Remember that three major factors contribute to the load capacitance: the internal diffusion
capacitance of the gate itself, the interconnect capacitance, and the fanout. Careful layout helps to reduce
the diffusion and interconnect capacitances. Good design practice requires keeping the drain diffusion areas
as small as possible.
 Increase the W/L ratio of the transistors : Increasing the transistor size also raises the diffusion
capacitance and hence CL . In fact, once the intrinsic capacitance (i.e. the diffusion capacitance) starts to
dominate the extrinsic load formed by wiring and fanout, increasing the gate size does not longer help in
reducing the delay. In addition, wide transistors have a larger gate capacitance, which increases the fan-out
factor of the driving gate and adversely affects its speed.
 Increase VDD : The delay of a gate can be modulated by modifying the supply voltage. This flexibility allows
the designer to trade-off energy dissipation for performance. However, increasing the supply voltage above
a certain level yields only very minimal improvement. Also, reliability concerns (oxide breakdown, hot-
electron effects)enforce firm upper-bounds on the supply voltage in deep sub-micron processes
 1. Sheet Resistance,

• A uniform slab of semi-conducting material is shown in fig with the dimensions and
the resistance of the slab is given by
Which can be L

• Where is resistivity of the oxide layer

• t; is the oxide thickness t
• L; is length oxide slab
• W; is the width of slab
• is the sheet resistance in Ω/ W
• Here the sheet resistance Rs depends on only resistivity
and thickness of the oxide layer but not on length and width of the slab
• On resistance of a slab or MOSFET is given by with Z as aspect ratio of
pull up or pull down device
9
 Sheet Resistance and area dependence,

• The resistances of layers shown in below two figures are equal because of equal thickness and
same value of resistivity
W W W

t t
L

resistances of two layers ? L

5/15/2023 VLSI Design Unit IV P Bujjibabu, Assistant Professor, Dept.of ECE 10

 Rs concept applied to MOS transistors and Inverters
• Consider the two transistor layout structures as shown in below fig. with corresponding
dimensions

Fig. a Fig. b
L=2ʎ
L=8ʎ

W=2ʎ

Therefore, Rb =4 Ra

11