Instruction set

architecture of a CPU

• Computer Registers
• Instruction Execution Cycle
• RTL representation of Instructions
• Addressing modes
• Instruction set
• Outlining instruction sets of some common CPUs
 Register Transfer Language

▪ A digital system is an interconnection of digital hardware modules that

accomplish a specific information-processing task.
▪ Microoperations : The operations executed on data stored in registers.
▪ The internal hardware organization of a digital computer is specified by:
✓ set of registers
✓ The sequence of microoperations
✓ The control
▪ Register Transfer Language(RTL) : The symbolic notation used to
describe the microoperation transfers among registers.

2
 Register Transfer
▪ Types of Registers:
✓Memory Address Register(MAR)
✓Program Counter (PC)
✓IR (Instruction Register)
✓R1(Processor Register) and
✓General Purpose Register so on ..
▪ Registers Representation:

3
 Register Transfer
▪ Register Transfer: Information transfer from one register to
another is designated in symbolic form by means of replacement
operator .
R2 ← R1
▪ Condition Control: if –then
▪ A control function separate the control variable from register
transfer operation.
▪ A control function is a Boolean variable (equal to 0 or 1). It is
terminated with a colon(:)

4
Register Transfer Operation

Timing diagram

5
Register Transfer Notation

6
 Preliminary Definitions

▪ Program: It is a set of instructions that specify operations,

operands and other sequence by which processing has to occur
▪ Computer Instruction: It is a binary code that specify sequence
of micro-operations for the computer

7
 Instruction Code

▪ Instruction Code: An instruction code is a group of bits that

instructs the computer to perform a specific operation.

▪ I = 0: Direct Address I = 1: Indirect Address

▪ It is usually divided into 2 parts:
□ Operation Code (Opcode)
□ Address

8
 Instruction Code

▪ Opcode: An operation code of an instruction is a group of bits

that defines operations such as add, subtract, multiply, shift etc.
□ Number of bits required for operation of an instruction depends on the total
number of operations available in the computer
□ Operations must be performed on some data stored in processor register or in
a memory
□ An opcode is sometimes called as macro-operation because it specifies a set
of micro-operations
▪ Operand: It specifies the registers or the memory words on which
the operation is carried out.
▪ Control Unit: It receives the instructions from memory and
interprets the operation code bits. Generates required control
signal to initiate micro-operations in internal computer register
9
 Stored Program Organization
▪ The Simplest way to organize computer is to have one processor
register and an instruction format with two parts: One part
specifies operation to be performed and Second part specifies
address.

10
 Addressing Types
▪ Immediate Instruction: When the second part of an instruction
code specifies an operand, the instruction is said to have an
immediate operand
▪ Direct Address: When the second part specifies the address of an
operand, the instruction is said to have a direct address
▪ Indirect Address: When the second part specifies the address of
memory word which contains the operand, the instruction is said
to have a Indirect address.
▪ Effective Address: It is defined as the address of the operand in
a computation type instruction or the target address in a branch
instruction.
11
Direct vs Indirect Addressing

12
Computer Registers

13
Common Bus System

14
Three control lines, S2, S1, and S0 control which register the bus selects as its input

Either one of the registers will have its load signal activated, or the memory will have
its read signal activated
Will determine where the data from the bus gets loaded
The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit
positions
When the 8-bit register OUTR is loaded from the bus, the data comes from the low
order 8 bits on the bus

15
 Computer Instructions
▪ Three basic computer instruction code formats are:
➢ i Memory reference Instruction
➢ ii Register reference Instruction
➢ iii Input Output Instruction
▪ Each format has 16-bits. The Opcode will be 3-bits and remaining
13-bits depends on the operation code encountered
▪ A Memory reference Instruction uses 12 bits to specify an
address and 1-bit to specify the addressing mode I. I = 0 for Direct
address and I = 1 for Indirect address
▪ The Register reference Instruction are recognized by the
operation code 111 with a 0 in the left most bit (bit 15) of the
instruction. The other 12-bit are used to specify operation or test
to be executed
 Computer Instructions
▪ An Input-Output instruction does not need a reference to
memory and is recognized by the operation code 111 with a 1 in
the left most bit of the instruction. The remaining 12 bits are used
to specify the type of Input Output operation or test performed.
▪ The type of instruction is recognized by the computer control from
the 4 bits in positions 12 to 15 of the instruction
Computer Instructions
Overall Computer Instructions
 Timing & Control
▪ The timing for all registers in the computer is controlled by a
master clock generator
▪ The clock pulses are applied to all flip-flop and registers in the
system and control unit
▪ Control signals are generated in the control unit. They provide
control inputs for
□ Multiplexers in the common bus
□ Control inputs in processor registers
□ Micro operations for the accumulator

20
 Types of Control Design

▪ Control Design is classified into:

i. Hardwired Control.
ii. Microprogrammed Control.
▪ Hardwired Control: In this, the control logic is implemented with
gates, flip-flops, decoders and other digital circuits.
□ Advantage: Fast mode of operation
□ Disadvantage: Difficult to incorporate the change.
▪ Microprogrammed Control: The control information is stored in
a control memory. The control memory is programmed to initiate
the required sequence of micro-operations.
□ Advantage: Easy to incorporate the change.
□ Disadvantage: Slow operation.
21
Hardwired Control Design

22
Example for Timing Control

23
 Instruction Cycle - phases

▪ Instruction Cycle: Each instruction of program completes its

execution in Cycle of steps namely “Instruction Cycle”.
▪ Phases of Instruction Cycle:
□ Fetch the Instruction
□ Decode the Instruction
□ Read the effective address, if Indirect Address present
□ Execute the Instruction.
▪ Upon the completion of step 4, the control goes back to step 1 to
fetch, decode and execute the next instruction
▪ This process continues indefinitely unless a HALT instruction is
encountered
24
 Fetch & Decode
▪ The micro operations for the fetch and decode phase can be specified by
the following register transfer statements
T0 : AR ← PC
T1: IR ← M [AR], PC ← PC + 1
T2: D0...D7← Decode IR(12-14), AR ← IR(0-11), I ← IR (15)
▪ During Clock T0, the address has to be transferred from program counter
PC to Address Register AR, as AR is connected to address input of
memory
▪ During Clock signal T1, the instruction read from memory is placed in the
instruction register IR and PC is incremented by one
▪ During clock signal T2, the opcode in IR (Instruction Register) is decoded,
indirect bit is transferred to flip-flop I and address part of instruction is
transferred to AR
▪ Then SC is incremented after each clock pulse to produce T0,T1 and T2 25
 Register Transfer for Fetch Phase
▪ Fetch Operation involves
T0 : AR ← PC
T1: IR ← M [AR], PC ← PC + 1
▪ Implementation of Micro Operations during T0:
1. Place the content of PC onto the bus by making the bus selection
inputs S2S1S0 equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR
▪ Implementation of Micro Operations during T1:
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making S2S1S0 = 111.
3. Transfer the content of the bus to IR by enabling the LD input of IR.
4. Increment PC by enabling the INR input of PC .

26
Register Transfer for Fetch Phase

27
 Determining the type of Instruction
▪ The timing signal that is active after the decoding is T3. During time T3,
the control unit determines the type of instruction that was just read from
memory .
▪ The 3 possible instruction types in basic computer are
i. Memory-Reference Instruction (Opcode = 000 - 110)
ii. Register-Reference Instruction (Opcode = 111, I = 0)
iii. Input-Output Instruction (Opcode = 111, I = 1)
▪ The following shows the flow chart shows how the control unit determines
the instruction type after decoding.
▪ The 3 instruction types are subdivided into 4. The selected operation is
activated with the clock transition signal T3
i. D7' I T3 : AR ← M [AR]
ii. D7' I' T3 : Nothing
iii. D7 I' T3 : Execute a Register-Reference Instruction
iv. D7 I T3 : Execute an Input-Output Instruction 28
Determining the type of Instruction

29
 Register Reference Instructions
▪ Register-Reference instructions are recognized by the control when D7 = 1 and I = 0
▪ These instructions use bits 0 through 11 of the instruction code to specify one of 12
instructions. These 12 bits are available in IR (0-11)
▪ These instructions are executed with timing variable T3
▪ The first 7 Register-Reference instructions perform clear, complement, circular shift
and increment micro-operations on the AC and E bit.
▪ The next 4 instructions cause a skip of next instruction in sequence when a stated
condition is satisfied
▪ Skipping of instruction is achieved by incrementing PC
▪ The AC is positive when its sign bit AC(15) = 0 and is negative when AC(15) = 1
▪ The content of AC is zero (AC =0) if all flip-flops of register = 0
▪ HLT, clears the start-stop flip-flop 'S' and stops timing sequence

30
Register Reference Instructions

31
Memory reference Instructions

32
 Memory reference Instructions

▪ AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

▪ ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store
carry in E

33
 Memory reference Instructions
▪ LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

▪ STA: Store AC
D3T4: M[AR]  AC, SC  0

▪ BUN: Branch Unconditionally

D4T4: PC  AR, SC  0

▪ BSA: Branch and Save Return Address

M[AR]  PC, PC  AR + 1 34
 Memory reference Instructions

▪ BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

▪ ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC
0
35
Memory reference Instructions – Branch & Save Return
Address Example

36
Control Flow for all Memory reference Instructions

37
Input – Output Configuration

38
 Input – Output Configuration

▪ Information transfer from Input device to AC

1. Initially, FGI is cleared i.e., Flag, FGI =0
2. When a key is pressed, an 8-bit corresponding alphanumeric code is
shifted into INPR
3. Input flag FGI is set to 1
4. The computer checks the flag bit. If 1, then information from INPR is
transferred in parallel into PC
5. Then FGI is cleared to 0.Only when FGI =0, new information will be
shifted into INPR by pressing another key

39
 Input – Output Configuration

▪ Information transfer from Accumulator to Output device

1. Initially, the flag FGO is set to 1
2. The computer checks the flag bit. If FGO = 1, the information
from AC is transferred in parallel into OUTR
3. Then FGO is cleared to 0
4. The output device accepts the coded information, and the
print operation is completed
5. Then FGO is set to 1. Only after the flag is set to 1, a new
character can be loaded into OUTR

40
 Input – Output Instructions

▪ Input-Output Instructions are needed for:

□ Transferring information to and from AC
□ Checking the flag bits
□ Controlling the interrupt facility
▪ These instructions have an Opcode 1111 and are recognized when
D7 = 1 and I = 1
▪ The remaining bits of the instruction specify particular operation
▪ These instructions are executed when timing signal is T3
▪ Control function is distinguished by one of the bits in IR (from 6th
bit to 11th bit).

41
Input – Output Instructions

42
 Program Interrupt
▪ Interrupt driven I/O is an alternative and efficient technique to Programmed driven
I/O.
▪ Rather than checking and waiting for status flags of I/O devices, the computer will
be executing other program and gets interrupted when the I/O devices are ready.
▪ To do this, it require Interrupt Enable Flag (IEN). When lEN is cleared to 0 the flags
cannot interrupt the computer. When lEN is set to 1, the computer can be
interrupted.
▪ Interrupt Cycle: An interrupt flip-flop R is included in computer.
1. When R=0, the computer goes through instruction cycle
2. During the execution phase of instruction cycle, IEN is checked by the control. If
IEN =0, program does not use interrupt so that control continues with next
instruction cycle
3. If IEN=1, control checks any one of the flag bit =1, then if R is set to 1, control
goes to an interrupt cycle instead of instruction cycle

43
Program Interrupt – Flow Chart

44
Program Interrupt – Example

45
 Program Interrupt - continued

▪ The interrupt cycle is initiated after the last execute phase if the
interrupt flip-flop R=1.
▪ This flip-flop is set to 1 if IEN=1 and either FGI or FGO =1.
▪ This can happen with any clock transition except when timing
signals T0, T1 or T2 are active which can be shown as:
T0' T1' T2' (IEN)(FGI + FGO): R ← 1
▪ The symbol + between FGI and FGO indicates logic OR operation.
This is ANDed with IEN and T0', T1' T2'
▪ After the instruction is executed and SC is cleared to 0, the
control will go through a fetch a phase only if R = 0. Otherwise, if
R=1, the control will go through an interrupt cycle.
46
 Micro Operations during Interrupt Cycle
▪ The interrupt cycle
□ Stores the return address into memory location 0
□ Branches to memory location 1
□ clears IEN, R and SC to 0
▪ This is done with following sequence of microoperations:
□ RT0 : AR ← 0, TR ← PC
□ RT1: M[AR] ← TR, PC ← 0
□ RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
▪ During the first timing signal AR is cleared to 0, and the content of PC is
transferred to the temporary register TR.
▪ With second timing signal, the return address is stored in memory at
location 0 and PC is cleared to 0.
▪ The third timing signal increments PC to 1, clears IEN and R, and control
goes back to T0 by clearing SC to 0 47
Complete Computer Description

48
Thank You

49