INDERPRASTHA ENGINEERING COLLEGE,GHAZIABAD

Question Bank- Unit 3- part-1

Subject Name : COA Code KCS 302

1. What is control Unit

 It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units.

 It interprets instructions.

 It controls data flow inside the processor.

 It receives external instructions or commands to which it converts to sequence of

control signals.

 It controls many execution units(i.e. ALU, data buffers and registers) contained
within a CPU.

 It also handles multiple tasks, such as fetching, decoding, execution handling and
storing results.

2. Differentiate between hardwired and microprogrammed control unit

Ans Control units are implemented in one of two ways

• Hardwired Control

– CU is made up of sequential and combinational circuits to generate the control

signals

– Hardwired control units are generally faster than microprogrammed designs

– Difficult to modify as the control signals that need to be generated are hard wired

– More costlier as everything has to be realized in terms of logic gates

– RISC based computer

• Microprogrammed Control

– A control memory on the processor contains microprograms that activate the

necessary control signals
 – This is slower than the other as micro instructions are used for generating signals
here

– Easy to modify as the modification need to be done only at the instruction level

– Less costlier than hardwired control as only micro instructions are used for
generating control signals

– CISC based computer

3. Explain each component of hardwired control unit organization

Ans
Timing and control
TIMING AND CONTROL
Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
signals
logic
T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

o A Hard-wired Control consists of two decoders, a sequence counter, and a number of

logic gates.

o An instruction fetched from the memory unit is placed in the instruction register (IR).

o The component of an instruction register includes; I bit, the operation code, and bits 0
through 11.

o The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.

o The outputs of the decoder are designated by the symbols D0 through D7.

o The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.

o The operation codes from Bits 0 through 11 are applied to the control logic gates.

o The Sequence counter (SC) can count in binary from 0 through 15.
4. Explain the organization of microprogrammed control unit.

Ans.

5. What is a Instruction Code?

o A group of bits that instruct the computer to perform specific operation is known as
instruction code. Instruction code is usually divided into two parts: Opcode and
address(operand). Opcodes specify the operation for specific instructions. An address
determines the registers or the areas that can be used for that operation. Operands are
definite elements of computer instruction that show what information is to be operated
on.
6. Draw the instruction word format for a computer uses memory unit size 256K×32
Instruction code stored in one word memory has four parts: an indirect bit, an
opcode , a register code to specify 64 registers and an address part. How many bits
are in each part?

Ans 256 K = 28 × 210 = 218 64 = 26

(a) Address: 18 bits

Register code: 6 bits

Indirect bit: 1 bit

25 32 – 25 = 7 bits for opcode.

(b) 1 7 6 18 = 32 bits

I Opcode Register Address

(c) Data; 32 bits; address: 18 bits.

7. Explain and draw the timing diagram of control unit

Timing and control
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

D3T4: SC 
T0 0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

8. What is instruction cycle ? Draw the flowchart of instruction cycle

A program residing in the memory unit of the computer consists of a sequence of

instructions. The program is executed in the computer by going through a cycle for each
instruction. Each instruction cycle in turn is subdivided into a sequence of subcycles or
phases. In the basic computer each instruction cycle consists of the following phases:

1. Fetch an instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory if the instruction has an indirect

address.

4. Execute the instruction.

Fetch and Decode

Initially, the program counter PC is loaded with the address of the first instruction in the
program.The sequence counter SC is cleared to 0, providing a decoded timing signal T0.
After each clock pulse, SC is incremented by one, so that the timing signals go through a
sequence T0, T1, T2, and so on.The microoperations for the fetch and decode phases can
be specified by the following register transfer statements.

T0: AR ← PC

T1: IR ← M[AR], PC ← PC + 1

T2: D0, .... , D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

Since only AR is connected to the address inputs of memory, it is necessary to transfer the
address from PC to AR during the clock transition associated with timing signal T0. The
instruction read from memory is then placed in the instruction register IR with the clock
transition associated with timing signal T1. At the same time, PC is incremented by one to
prepare it for the address of the next instruction in the program. At time T2, the operation
code in IR is decoded, the indirect bit is transferred to flip-flop I, and the address part of the
instruction is transferred to AR
 Instrction Cycle

Start
SC  

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR  M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.

9. Explain the different types of reference instructions

Instructions

COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

Memory Reference Instruction-Memory reference instructions are those commands or

instructions which are in the custom to generate a reference to the memory

Register Reference Instruction-The Register-reference instructions are represented by the

Opcode 111 with a 0 in the leftmost bit (bit 15) of the instruction.A Register-reference
instruction specifies an operation on or a test of the AC (Accumulator) register.

Input/Output Instructions-Just like the Register-reference instruction, an Input-Output

instruction does not need a reference to memory and is recognized by the operation code 111
 with a 1 in the leftmost bit of the instruction. The remaining 12 bits are used to specify the type
of the input-output operation or test performed.

10. Explain different types of processor registers and their connection with common
bus system

A processor has many registers to hold instructions, addresses, data, etc

The processor has a register, the Program Counter (PC) that holds the memory address
of the next instruction to get .Since the memory in the Basic Computer only has 4096

locations, the PC only needs 12 bits .In a direct or indirect addressing, the processor
needs to keep track of what locations in memory it is addressing: The Address Register
(AR) is used for this .The AR is a 12 bit register in the Basic Computer When an
operand is found, using either direct or indirect addressing, it is placed in the Data
Register (DR). The processor then uses this value as data for its operation .The Basic
Computer has a single general purpose register – the Accumulator (AC)

Registers
COMPUTER REGISTERS
Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR or MDR 16 Data Register Holds memory operand
AR or MAR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds the data read from i/p device
OUTR 8 Output Register Holds the data to be sent to the o/p device
 Registers
COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2 S2 S1 S0 Register
LD INR CLR 0 0 0 x
0 0 1 AR
DR 3 0 1 0 PC
0 1 1 DR
LD INR CLR
1 0 0 AC
E 1 0 1 IR
ALU AC 4 1 1 0 TR
1 1 1 Memory
LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

Registers
COMMON BUS SYSTEM
• Three control lines, S2, S1, and S0 control which register
the bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal activated,
or the memory will have its read signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the
bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus

11. What is micro program sequencer

Ans. Microprogram Sequencer is a combination of hardware for selecting the next micro-
instruction address. The micro-instruction in control memory contains a set of bits to initiate
micro operations in computer registers and other bits to specify the method by which the
address is obtained.
Control Address Register(CAR) :
Control address register receives the address from four different paths. For receiving
the addresses from four different paths, Multiplexer is used.

Multiplexer :
Multiplexer is a combinational circuit which contains many data inputs and single data
output depending on control or select inputs.

Branching :
Branching is achieved by specifying the branch address in one of the fields of the micro
instruction. Conditional branching is obtained by using part of the micro-instruction to
select a specific status bit in order to determine its condition.

Mapping Logic :
An external address is transferred into control memory via a mapping logic circuit.

Incrementer :
Incrementer increments the content of the control address register by one, to select
the next micro-instruction in sequence.

Subroutine Register (SBR) :

The return address for a subroutine is stored in a special register called Subroutine
Register whose value is then used when the micro-program wishes to return from the
subroutine.

Control Memory :
Control memory is a type of memory which contains addressable storage registers.
Data is temporarily stored in control memory. Control memory can be accessed quicker
than main memory.
 12. Define micro-operation, microinstruction, microprogram, micro code

• Ans. Micro operation - an elementary digital computer operation. Micro instruction - an

instruction stored in control memory. Micro program - a sequence of microinstructions.
Micro code - same as microprogram

13. What is address Sequencing

Ans

14. What is pipelining

Ans. Pipelining is a technique of decomposing a sequential process into suboperations, with

each subprocess being executed in a special dedicated segment that operates concurrently
with all other segments.

Advantages of pipelining:
 Instruction throughput increases.
 Increase in the number of pipeline stages increases the number of instructions executed simultaneously.
 Faster ALU can be designed when pipelining is used.
 Pipelined CPU’s works at higher clock frequencies than the RAM.
 Pipelining increases the overall performance of the CPU.
15. Draw a space time diagram for a six segment pipeline showing the time it takes to
process 8 tasks

Ans

16. The number of clock cycles that it takes to process 200 tasks in a six segment pipeline is
205

Ans

Let there be 'n' tasks to be performed in the 'pipelined processor'.

The first instruction will be taking 'k' segment pipeline 'cycles' to exit out of the
'pipeline' but the other 'n - 1' instructions will take only '1' 'cycle' each, i.e, a total of 'n -
1' 'cycles'.

So, to perform 'n' 'instructions' in a 'pipelined processor' time taken is k + (n - 1) cycles.

So, in our case number of clock cycles = 6 + (200 -1) = 205

17. A non pipeline system takes 50 ns to process a task. The same task can be processed in
a 6 segment pipeline with a clock cycle of 10 ns. Determine the speed up ratio of the
pipeline for 100 tasks. What is the maximum speed up that can be achieved.

Ans. Total Number of tasks "n" = 100

Time taken by non pipeline "Tn" = 50 ns

Time period of 100 tasks = ntn

= 100 x 50 = 5000 ns

Number of segment pipeline "K" = 6

Time period of 1 clock cycle = 10 ns

Total time required = ( k + n - 1)tp

= ( 6 + 100 - 1)10

= 1050 ns
 Speed up ratio " S" = 5000/1050

= 4.76

Maximum Speed up ratio= k= 6

18. What is address sequencing?

Ans. The process of selecting the address of the microinstruction which will be
executed next in control unit is called as address sequencing. There are four ways
through which a control unit chooses the next address : Mapping, Subroutine call,
Incrementing the previous address, Conditional or unconditional branching

19. How pipeline performance can be measured? Discuss. Give a space time diagram for visualizing
the pipeline behavior for a four stage pipeline

Ans. Pipeline performance can be measured using some parameters like speed up ,
throughput, efficiency

In non-pipelined architecture, The instructions execute one after the other.The execution of a
new instruction begins only after the previous instruction has executed completely. So,
number of clock cycles taken by each instruction = k clock cycles . If there are n tasks/
instructions

Non-pipelined execution time

= Total number of instructions x Time taken to execute one instruction

= n x k clock cycles

Calculating Pipelined Execution Time-

In pipelined architecture,Multiple instructions execute parallely. Number of clock cycles

taken by the first instruction = k clock cycles. After first instruction has completely
executed, one instruction comes out per clock cycle.
Pipelined execution time
= Time taken to execute first instruction + Time taken to execute remaining instructions
= 1 x k clock cycles + (n-1) x 1 clock cycle
= (k + n – 1) clock cycles
Speed up
= Non-pipelined execution time / Pipelined execution time
= n x k clock cycles / (k + n – 1) clock cycles
= n x k / (k + n – 1)
= n x k / n + (k – 1)
= k / { 1 + (k – 1)/n }

 For very large number of instructions, n→∞. Thus, speed up = k.

 Practically, total number of instructions never tend to infinity.
 Therefore, speed up is always less than number of stages in pipeline.
 Space time diagram for 4 stage pipeline is shown below with 6 tasks

19. Define the role of MIMD in computer architecture

Ans. MIMD stands for 'Multiple Instruction and Multiple Data Stream'. In this
organization, all processors in a parallel computer can execute different instructions and
operate on various data at the same time. In MIMD, each processor has a separate program
and an instruction stream is generated from each program.