AN-1388

APPLICATION NOTE
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Coherent Sampling for Power Quality Measurements Using the AD7779 24-Bit
Simultaneous Sampling Sigma-Delta ADC
by Anthony O’Shaughnessy and Petre Minciunescu

INTRODUCTION specifies a frequency tracking resolution vs. power quality

With the evolution of smart grids, utility companies are product classification. Class A devices must track 0.01 Hz changes
requiring additional visibility and more automation for power in the line frequency, Class S devices must track 0.05 Hz changes
grids. Increased automation within the grid infrastructure in the line frequency, and the manufacturer determines the
increases the grid efficiency by using dynamic load adjustment tracking specification for Class B devices. Class B devices may be
to meet the demand. This increased visibility and automation removed from future editions of the IEC 61000-4-30 standard.
requires an increase in the monitoring capabilities of the nodes The method for measuring voltage harmonics used by the
on the grid. Consumers of transmission and distribution (T&D) IEC 61000-4-30 standard is defined in the IEC 61000-4-7: a
products require cost effective products with multiple functions discrete Fourier transform (DFT) is performed digitally over a
to meet the smart grid requirements. These functions include group of samples using a rectangular window. The DFT windowing
protection, measurement, and quality monitoring. T&D device techniques are not recommended because the DFT window profile
manufacturers are developing integrated hardware/platform (Hamming, Blackman, or so on) changes the magnitude of the
solutions to meet these requirements. The consolidation of harmonics; if each manufacturer uses a different fast Fourier
functionality into a single hardware/platform solution requires transform (FFT) windowing technique, the harmonic analysis
an analog-to-digital converter (ADC) with the following results differ from one product supplier to another. Therefore,
characteristics: the IEC 61000-4-30 Class A power quality devices cannot use
the DFT windowing techniques to achieve coherent sampling.
• An 8-/4-channel simultaneous sampling 24-bit ADC
• A high dynamic range (114 dB at 8 kSPS) EXISTING SOLUTIONS TO ACHIEVING COHERENT
• A fast settling ADC (low group delay) SAMPLING
• Fine adjustment of the ADC output data rate (ODR) to Customers currently use one of the following options to
facilitate coherent sampling to within 0.01 Hz of the line maintain coherency with the line frequency:
frequency
• Use a phase-locked loop (PLL) to adjust the ADC clock
The AD7779 is a 24-bit simultaneous sampling Σ-Δ ADC that dynamically.
meets all of these requirements. This application note presents • Sample the ADC and perform the DFT using a Goertzel
ways to achieve coherent sampling with the line frequency algorithm.
using the AD7779 and compares them against alternative • Oversample the ADC by at least 4 times, interpolate the
techniques. waveform samples, and perform the DFT using a regular
COHERENT SAMPLING SPECIFICATIONS fast Fourier transform (FFT) algorithm.

To achieve the required accuracy on the harmonic data and The PLL is implemented in either analog or digital domains.
metering parameters in power metering and power quality It provides an output signal with a frequency equal to the
devices, ensure coherency between the ADC sampling rate and fundamental frequency of the input signal. The signal dynamically
the power line frequency. adjusts the ADC clock and achieves the coherency of the ADC
sampling with the fundamental frequency of the line. The problem
The power line frequency can vary 50 Hz ± 15% or 60 Hz ± 15%.
with the PLL is its response time; that is, the time from the
In countries where the grid is well established and controlled,
moment the line frequency changes to the moment the PLL
the rate of change of the power line frequency is low. In countries
output settles.
where the grid is under development, the power line frequency
varies significantly. Power quality standard IEC 61000-4-30

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AN-1388 Application Note

TABLE OF CONTENTS
Introduction ...................................................................................... 1  Programming the Decimation Factor N into the Sample Rate
Coherent Sampling Specifications.................................................. 1  Converter ........................................................................................4 

Existing Solutions to Achieving Coherent Sampling ................... 1  Loading the Decimation Factor N into the Sample Rate
Converter ........................................................................................5 
Revision History ............................................................................... 2 
Latency in Transitioning to New ODR .......................................6 
Sample Rate ....................................................................................... 4 
Frequency .......................................................................................6 
Sample Rate Converter (SRC)..................................................... 4 

REVISION HISTORY
2/16—Initial Version: Revision 0

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Application Note AN-1388
Figure 1 shows a block diagram of a protective relay and interpolation can be linear or of a higher degree, with the latter
measurement system composed of the AD7779 and a digital yielding more accurate results. The DSP must have increased
signal processor (DSP) that calculates the voltage harmonics bandwidth to accommodate this additional computational load.
and then uses them in the protection algorithms. The Goertzel Note that the interpolation introduces spurious harmonics into
DFT algorithm practically adjusts the Fourier transform the measurement band.
coefficients’ function of the number of waveform samples Each existing solution has disadvantages such as increased power
acquired during an integer number of line cycles. These consumption (due to the increased DSP calculation bandwidth
coefficients are sine and cosine; therefore, the DSP must requirement) and additional cost. The sample rate converter (SRC)
have increased bandwidth to accommodate this load. of the AD7779 allows users to achieve a Class A power quality
As an alternative to the Goertzel algorithm, use the interpolation device by having sufficient resolution in the AD7779 ODR to track
approach. Set the AD7779 to an output rate of 32 kSPS, 4 times 0.01 Hz changes in the power line frequency. The SRC eliminates
larger than the 8 kSPS normally used. The DSP interpolates the the need for the interpolation block shown in Figure 1.
waveform samples to maintain the same number of samples
over the line cycle independent of the line frequency. The

DSP
PROTECTION
ALGORITHMS

INTERPOLATION DFT/FFT
ANALOG SIGNALS:
LINE CURENTS, SERIAL COMMUNICATIONS
PHASE VOLTAGES, AD7779
AND CONTROL
AND SO ON DFT/FFT/ HARMONIC
FUNDAMENTAL ANALYSIS
FREQUENCY

13855-001
TRACKING

Figure 1. Block Diagram of a Protective Relay and Measurement System

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AN-1388 Application Note

SAMPLE RATE
SAMPLE RATE CONVERTER (SRC) For example, for the AD7779, elect to use the sinc3 filter with
The Σ-Δ ADCs include a low-pass sinc filter to remove the the device set to LP mode.
noise from the modulator efficiently. The sinc filter also reduces Sample the voltage 64 times over one line period to use the
the output data rate by some integer value relative to the modulator ADC output samples into a 64-point DFT. If the line frequency
clock rate, a process called decimation. Usually the decimation is exactly 50.00 Hz, the output data rate is then ODR = 50.00 ×
is restricted to a set number of integer values. The sinc filter on 64 = 3.200 kHz. The sampling clock of the modulator is
the AD7779 is implemented with a synchronous sample rate
MCLK 4096
converter (SRC) to allow decimation by a non-integer value. f MOD = = = 512 kHz .
M 8
The user can vary this value over time while still using the
efficient and proven sinc filter architecture. The decimation factor N is then
For the SRC to be available, the AD7779 must be in the SPI control f MOD 512
N= = = 160 .
mode. During the power-up procedure, select this mode by ODR 3.2
tying the FORMAT0 pin and the FORMAT1 pin directly to If the line frequency becomes 50.01 Hz, still sample it 64 times.
IOVDD, the input/output digital LDO supply. The output data rate is then ODR = 50.01 × 64 = 3.20064 kHz.
The AD7779 is intended specifically for applications that monitor The decimation factor N is then
ac voltages and currents in mains electrical power line networks.
Two of the main characteristics measured in these applications f MOD 512
N= = = 159.968006 .
are the transmission line frequency and the power. Determine ODR 3.20064
these by performing an FFT on the outputs generated by an ADC. Use the AD7770/AD7771/AD7779 Filter Model to calculate the
The AD7779 can maintain coherent sampling over the line decimation factor and the sinc filter response in any condition.
frequency by allowing a user to program specific output data PROGRAMMING THE DECIMATION FACTOR N
rates. The user programs a decimation factor (N) for the sinc INTO THE SAMPLE RATE CONVERTER
filter with the SPI interface. The formula for the output data
Program the decimation factor N to the memory map before
rate (ODR) is
loading it into the SRC. The decimation factor is composed of
MCLK f an integer and a fractional number. There are four memory
ODR = = MOD (1)
M ×N N map registers used to program the decimation factor.
where: Two registers are used to program the integer, allowing a range
MCLK is the AD7779 clock frequency. of programmable values from the minimum specified value (see
M is equal to 4 when the AD7779 device is set to high Table 2) to 4095.
resolution (HR) mode, and 8 when the AD7779 device is set to • Register 0x60, the SRC_N_MSB bits, Bits[3:0]
low power (LP) mode.
• Register 0x61, the SRC_N_LSB bits, Bits[7:0]
fMOD = MCLK/M, which is the sampling clock of the modulator.
Two registers are used to program the fractional number, also
The procedure for calculating the decimation factor, N, follows:
called the interpolation factor, allowing a 16-bit decimal
1. Connect the FORMAT0 pin and the FORMAT1 pin to representation of the fractional number to be programmed.
IOVDD to put the AD7779 in the SPI control mode.
2. Select the sinc filter, the decimation rate, the power mode, • Register 0x62, the SRC_IF_MSB bits, Bits[7:0]
the PGA gain, and the internal/external voltage reference • Register 0x63, the SRC_IF_LSB bits, Bits[7:0]
by writing to the relevant memory map registers using the Table 2 details the maximum and minimum values for the
SPI interface. Note that the AD7779 has a sinc3 filter only. decimation factor N based on the filter type.
3. Select the output data rate (ODR) of the ADCs in between
the minimum and maximum rates detailed in Table 1. Table 2. Maximum and Minimum Decimation Factor N Values
4. Calculate the sampling clock of the modulator by fMOD = Filter Type Minimum N Maximum N
MCLK/M. Sinc3 (HR Mode) 128 4095
5. Calculate the decimation factor by N = fMOD/ODR. Sinc3 (LP Mode) 64 4095

Table 1. Minimum and Maximum Output Data Rates (ODRs)

Mode Minimum ODR (kHz) Maximum ODR (kHz)
HR 0.500000001 16
LP 0.125000001 8

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Application Note AN-1388
In the example from the Sample Rate Converter (SRC) section, If multiple AD7779 devices must be loaded with the same
N = 159.968006. The integer is 159 and the fractional number is synchronized SRC load signal, connect the MODE1/GPIO1 pin
0.968006. SRC_N_MSB = 0x00 and SRC_N_LSB = 0x9F. of one device to the MODE0/GPIO0 pins of the other devices.
To calculate the value of the SRC_IF_MSB and SRC_IF_LSB Note this synchronization method requires the use of a common
registers, MCLK (see Figure 2).

1. Multiply the fractional number by 216: ASYNCHRONOUS PULSE

0.968006 × 216 = 63,439.24.

AD7779
2. Take the integer and convert it to hexadecimal format:
GPIO2/MODE2
63,439 = 0xF7CF.
XTAL2/MCLK GPIO1/MODE1
3. Write 0xF7 into the SRC_IF_MSB register and 0xCF into SYNCHRONIZATION
LOGIC
the SRC_IF_LSB register.
The AD7770/AD7771/AD7779 Filter Model calculates the DIGITAL FILTER

register values for every calculated decimation factor N for the

GPIO0/MODE0
SRC_N_MSB, SRC_N_LSB, SRC_IF_MSB, and SRC_IF_LSB
registers.
LOADING THE DECIMATION FACTOR N INTO THE AD7779

SAMPLE RATE CONVERTER START

XTAL2/MCLK SYNCHRONIZATION GPIO1/MODE1

The SRC_N_MSB, SRC_N_LSB, SRC_IF_MSB, and SRC_IF_LSB MCLK
LOGIC
registers only store the decimation factor. They must be loaded
to the DSP via an SRC load operation. The decimation factor DIGITAL FILTER

can be loaded by software or by hardware, depending on Bit 7

GPIO0/MODE0
(SRC_LOAD_SOURCE) in the SRC_UPDATE register
(Register 0x64):
• Bit 0 = SRC_LOAD_UPDATE AD7779

•
START
Bit 7 = SRC_LOAD_SOURCE
SYNCHRONIZATION GPIO1/MODE1
If Bit 7, SRC_LOAD_SOURCE, has a default value of 0, XTAL2/MCLK LOGIC

perform the load by setting SRC_LOAD_UPDATE bit to 1.

Wait at least two MCLK periods and then clear the DIGITAL FILTER

SRC_LOAD_UPDATE bit to 0. The bit must be cleared to 0

13855-002
GPIO0/MODE0
before any attempt to execute a new load.
If Bit 7, SRC_LOAD_SOURCE, is set to 1, the ODR is Figure 2. Synchronization of Multiple AD7779 Devices
controlled in hardware. To execute the load,
1. Connect the MODE0/GPIO0 pin to the MODE1/GPIO1 pin.
2. Set the MODE2/GPIO2 pin high for two MCLK periods in
LP mode and for one MCLK period in HR mode. Then set
the MODE2/GPIO2 pin low.

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AN-1388 Application Note
LATENCY IN TRANSITIONING TO THE NEW ODR If the decimation factor N is a non-integer number, the period
After the SRC has been loaded with the new decimation factor, of the DRDY oscillates between the periods determined by the
there is a latency in transitioning to the new ODR. The latency integers obtained rounding up or down the decimation factor.
arises because the SRC enters a transition sequence: it finishes The average of the periods is equal to the expected ODR. The
calculating the filter outputs at the previous ODR and then starts periods, however, are always calculated at the ODR
calculating outputs at the new ODR. The ODR is determined by programmed to the AD7779.
monitoring the period of the signal at the DRDY pin (Pin 30). For example, if N = 159.968006, the DRDY period oscillates
The DRDY pin stays high for at least one DCLK pulse to between the period determined by N = 159 (310.547 μs) and
indicate the latest conversion has completed and the data is N = 160 (312.5 μs) in such a way to average N/fMOD =
about to be provided at the DOUT pin. 159.968006/512000 = 312.438 μs.
There is a latency from when the decimation factor is loaded to To verify that the ODR period is the expected one, measure the
when the new ODR is seen at the DRDY pin. The new ODR is time between the number of DRDY pulses indicated by the
seen after three or four DRDY pulses (see Figure 3). The exact following expressions. They provide a good approximation of
latency is not fixed because it depends on when the SRC is the time it takes to obtain the expected ODR.
loaded relative to the DRDY pulses. When IF is ≤0.5,
During the transition sequence, do not load a new decimation ((1/IF) + 1) pulses
factor into the SRC. Any attempt is ignored.
When IF is >0.5,
FREQUENCY ((1/(1 − IF)) + 1) pulses
The DRDY pin can be used to measure the ODR of the AD7779. where IF is the fractional number of N.
When the decimation factor is an integer, the period of the
DRDY pin is always constant and equal to 1/ODR Round up the result to the nearest integer whenever the number
of DRDY pulses is not an exact integer.
If, for example, N = 160, ODR = fMOD/N = 512/160 = 3.2 kHz
and the period between DRDY pulses is 1/3200 = 312.5 μs. If For example, if N = 159.968006, IF = 0.968006. The number of
DRDY pulses that must be counted to calculate the expected
N = 159, ODR = 512/159 = 3.220126 kHz and the period
between DRDY pulses is 1/3220.126 = 310.547 μs. ODR period is the following:
1/(1 − 0.968006) + 1 = 32.35  33 DRDY pulses

SRC GENERATES THE NEW ODR PERIOD

AFTER 3 OR 4 DRDY PULSES

DRDY
13855-003

NEW DECIMATION FACTOR DRDY PULSE GENERATED AFTER

LOADED INTO SRC THE FIRST NEW ODR PERIOD

Figure 3. New Output Data Rate Latency

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AN13855-0-2/16(0)

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