446 Input-Output Organization

(
The initial and final operations listed above are referred to I
operations or housekeeping chores. They are not part of the serv~ ove,-he ·
. . ice Pro .
proper but are essential for processmg mterrupts. All overhead 0 gr
can be implemented by software. This is done by inserting the pro P:ratio ·.
1
tions at the beginning and at the end of each service routine SPer nstru
• · orne
overhead operations can be done automatically by the hardwar Th oft
tents of processor registers can be pushed into a stack by the harde. e co
· . 0th ... 1 d Ware be"1 ~
branching to the service routme. er lllltla an final operaf 0
. . .bl ions ca
assigned to the hardware. In thi s way, 1t 1s poss1 e to reduce the tirn n
receipt of an interrupt and the execution of the instructions that e b:twe ·
service
interrupt source. t

12.6 Direct Memory Access (OMA)

The transfer of data between a fast storage device such as magnetic d. k
memory is often limited by the speed of the CPU. Removing the CP~ 0 ft ,
the path and letting the peripheral device manage the memory buses d.
·
would improve the speed o f ~ans fier. Th.1s trans tier technique
· is called rrec
dir ·
memory access (OMA). During OMA transfer, the CPU is idle and has ·
control of the memory buses. A OMA controller takes over the buses tom ,
age the transfer directly between the 1/0 device and memory. l
The CPU may be placed in an idle state in a variety of ways.
common method extensively used in microprocessors is to disable the bu •
through special control signals. Figure 12.16 shows two control signals in '
1
bus request CPU that facilitate the OMA transfer. The bus request (BR) input is used
the OMA controller to request the CPU to relinquish control of the bus '
When this input is active, the CPU terminates the execution of the curr •
instruction and places the address bus, the data bus, and the read and wri
lines into a high-impedance state. The high-impedance state behaves like •
open circuit, which means that the output is disconnected and does not havd
bus grant logic significance (see Sec. 4.3). The CPU activates the bus grant (BG) outp'
to inform the external OMA that the buses are in the high-impedance sta
The OMA that originated the bus request can now take control of the bu l
to conduct memory transfers without processor intervention. When the D ,
terminates the transfer, it disables the bus request line. The CPU disables 1
bus grant, takes control of the buses, and returns to its normal operation.

Bus request BR

CPU
DBUS

ABUS

RD
A-ssh"'
Data bus

Read
I High-impedence
(disable)
whenBG 1s
enabled
Bus grant BG
WR Write

FIGURE 12.16 CPU bus signals for OMA tran 5 fer.

 12.6 Direct Memory Access (OMA) 447

contr01ler and the ~rocessor use the BR and BG signals to

the uansfer of data with the memory. The one (processor or OMA '
I
us~IPO
.. a the bus
Th b
to carry out transfer of data with the memory •
. .. IS
bUS JJ18Ster. e us master 1mttates the transfer. The other device
in the transfer (memory in this case) is called slave. Thus we
by incorporating the bus arbitration mechanism, two bus ma;ters
DMA controller) can transfer data over the same bus without any
operations.
the OMA takes control of the bus system, it communicates
the memory. The transfer can be made in several ways. In OMA
, a block sequence consisting of a number of memory words burst transfer
in a continuous burst while the OMA controller is master of
buses. This mode of transfer is needed for fast devices such as
, where data transmission cannot be stopped or slowed down
cycle stealing
block is transferred. An alternative technique called cycle
the OMA controller to transfer one data word at a time, after
return control of the buses to the CPU. The CPU merely delays
for one memory cycle to allow the direct memory 1/0 transfer
emory cycle.

an
Iler needs the usual circuits of interface to communicate
1/0 device. In addition, it needs an address register, a word
a set of address lines. The address register and address
or direct communication with the memory. The word count
the number of words that must be transferred. The data
ne directly between the device and me~ory under control

l.7 shows the block diagram of a typical DMA c?ntroller.

· tes with the CPU via the data bus and control lmes. The
are selected by the CPU through the address bus by
tdA select) and RS (register select) inputs. The 1:-D (r~ad)
uts are bidirectional. When the BG (bus grant) mput is O,
·cate with the DMA registers through the data bus_to
to the OMA registers. When BG = l, the _CPU has rehn-
the OMA can communicate directly wi th th e memory
· t· the RD or WR
ss in the address bus and activa mg th
mmunicates with the external peripheral throug: e
e lines by using a prescribed handshakffi:g proce ur~
ddress register a wor
troller has three registers: an a . ' address
ntrol register The address regiS ter contams: h bus
location in ~emory. The address
. . bits go t after
mented oug eac h
s bus. The address register is ~ere holds the number
to memory. The word count regtS ter
... 1'1)Ul-0ulpul OtpilZatlon

Mdral•

Dalabus
buff'cn

OMA.elect DS
]

l
Repter .elect RS

Read RD
Control
Write WR logic
Bmrequest BR
Bus put 80
Interrupt DMArequest
Interrupt
DMA Acknowledge to 1/Q device

FIGURE 12.17 Block diagram of DMA controller.

of words to be transferred. This register is decremented by one after ea b

word transfer and internally tested for zero. The control register specifies~
mode of transfer. All registers in the DMA appear to the CPU as 1/0 interfac:
registers. Thus the CPU can read from or write into the DMA registers under
program control via the data bus.
The DMA is first initialized by the CPU. After that, the DMA starts
and continues to transfer data between memory and peripheral unit until
an entire block is transferred. The initialization process is essentially apro-
gram consisting of 1/0 instructions that include the address for selecting
particular DMA registers. The CPU initializes the DMA by sending the fol-
lowing information through the data bus:
l. The starting address of the memory block where data are available (for
read) or where data are to be stored (for write)
2. The word count, which is the number of words in the memory block
3. Control to specify the mode of transfer such as read or write
4. A control to start the DMA transfer
Th tartin addre
es g . stored m
ss 1s . the address register.
. The wo rd count is stored
. ter
·m the word count register, and the control information· _m· th. e control
. th DMA·
regis
Once the DMA is initialized, the CPU stops commumcatmg Wt th ewords
unless it receives an interrupt signal or if it wants to check how manY
have been transferred.

OMA Transfer
• aconi-
The position of the DMA controller among the other components
. atesUlwith tbt
puter system is illustrated in Fig. 12.18. The CPU communtc
 12.8 Direct Memof'y Access (OMA) 449

1n1erruPt
CPU Random-access
BO memory {RAM)
BR

RD WR Address Data RD WR Address Data

Read control

Write control

Data bus

Address bus

RD WR Address Data
DMA acknowledge
DS

RS Direct memory 1/0

access (DMA) Peripheral
BR controller device
DMArequest
BG
Interrupt

FIGURE 12.18 DMA transfer in a computer system.

the address and data buses as with any interface unit. The
own a,ddress, which activates the DS and RS lines. The CPU
DMA through the data bus. Once the DMA receives the start
d, it can start the transfer between the peripheral device and -

e peripheral device sends a DMA request, the DMA controller

BR line, informing the CPU to relinquish the buses. The CPU
its BG line, informing the D MA that its buses are disabled. The
the current value of its address register into the address bus,
or WR signal, and sends a DMA acknowledge to the periph-
.ote that the RD and WR lines in the OMA controller are bidirec-
·on of transfer depends on the status of the BG line. When
and WR are input lines allowing the CPU to communicate
DMA. registers. When BG= I, the RD and WR are output
1npu1-0utpUt Otga..tzatk>n
. the DMA controller to the random-access memory to specif
Imes from ...... data. Yth
·te ....wontion ,or .....
read or wn vr-·- .
When the penpoc;1u
L-• device receives a OMA acknowledge .
· rd fro ' It Puts
. da bus (for write) or receives a wo . m the data b
word ID the thetaDMA controls the read or wnte ' operations
' and sup I'
Us (ft
read). Thus the .-..nn"1 The pen'pberal unit can then corrunnn: p les th
address for ....,..._. .,. ....ucate .
the data bus for direct transfer between the two units W11
memory tbrough . . ed %ii
the CPU is momentanly disabl · .
rd that is transferred, the OMA mcrements its d
For eacb WO . If h a dre
. d decrements its word count register. t e word count d s
register an 1 . . fi oes no
the DMA checks the request me com.mg rom the Peri h
reacb zero, . .11 b t· P era!
For a high-speed device, the hne w1 fi e. ach 1ve . as. .soon as the previou
.
transfier is completed. A second trans
.
er 1s t en m1tiated, and the
fi d If h proces
continues until the entire Hock is trans erre . t e peripheral speed i
slower, the DMA request line 1;11ay come somewhat later. In this case th
DMA disables the bus request hne so that the CPU can continue to execut
its program. When the peripheral requests a transfer, the DMA requests th
buses again. .
If the word count register reaches zero, the DMA stops any furth
transfer and removes its bus request. It also informs the CPU of the te~ .
nation by means of an interrupt. When th~ CPU responds to the interrupt
it reads the content of the word count register. The zero value of this reg
ister indicates that all the words were transferred successfully. The CP .
can read this register at any time to check the number of words alread
transferred.
A DMA controller may have more than one channel. In this case
each channel has a request and acknowledge pair of control signals whic~
J are connected to separate peripheral devices. Each channel also has its own
address register and word count register within the DMA controller. A prior-
ity among the channels may be established so that channels with high priority
are serviced before channels with lower priority.
DMA transfer is very useful in many applications. It is used for fast
transfer of information between magnetic disks and memory. It is also useful
for updating the display in an interactive terminal. Typically, an image of the
screen display of the terminal is kept in memory which can be updated under
program control. The contents of the memory can be transferred to the screen
periodically by means of DMA transfer.

12.7 Input-Output Processor (IOP)

I
.
Instead of havmg · U mputer maY
each interface communicate with the CP , a co fco!ll·
·mcorporate one or more external processors and assign
• them the task 0 (IOP)
municating directly with all 1/0 devices. An input-output procesbs~l~ty (hat
• capa 11
may be classified as a processor with direct memory access t r syste!ll
,communicates with 1/0 devices. In this configuration, the compu e
 12.7 Input-Output Processor QOP) 451

,nernory unit, and a number of processors comprised

jfJfO or 1110re IOPs. Each IOP takes care of input and output
8

-CPU frotn the housekeeping chores involved in 1/0 trans-

diethat cotnlllumca
. tes WI.th remote termmals
.
over telephone
·cation media in a serial fashion is called a data commu-
,;..n~
(l)CP)·to a CPU except that 1t. 1s. designed to handle the
ii siJnilar 1/0 processing
~jog. Unlike the OMA controller_ that mu_st be set up
c,U, the IOP can ~etch and ~~te its own mstructions.
are specifically design~ to fac1htate 1/0 transfers. In addi-
perfonn o!11er processmg tasks, such as arithmetic, logic,
code translation. . . .
k diagram of a computer with two processors 1s shown in
Jllemory unit occupies a central position and can com-
each processor by means of direct memory access. The
ible for processing data needed in the solution of computa-
e IOP provides a path for transfer of data between various
·ces and the memory unit. The CPU is usually assigned the
the 1/0 program. From then on the IOP operates inde-
CPU and continues to transfer data from external devices

formats of peripheral devices differ from memory and CPU

IOP must structure data words from many different sources.
may be necessary to take four bytes from an input device and
one 32-bit word before the transfer to memory. Data are gath-
at the device rate and bit capacity while the CPU is-executing
After the input data are assembled into a memory word,
from IOP directly into memory by "stealing" one mem-
the CPU. Similarly, an output word transferred from memory
from the IOP to the output device at the device rate and

_ __, Central processing ·

unit(CPU)

Peripheral devices

PD PD PD PD

Input-output
processor (IOP) 1/0bus

Block diagram of a computer with VO processor.