EC806 DDFPGA

Review of Digital System Design - Timing

Sequential circuit

inputs outputs
NSD
&
OD
Present
next
state
state

FF

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Dept of E&C, NITK Surathkal 1

 EC806 DDFPGA

Moore example

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Mealy waveform

Spikes in output – can cause cct misbehaviour

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 EC806 DDFPGA

Mealy machine

Unnecessary long paths (max clk period)

Combinational feedback loops

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Registered output
Avoiding long paths and uncertain timing

With one additional clock period

Without additional clock period (Mealy)

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 EC806 DDFPGA

Registered output - 1

One clock period delay between STATE and

output changes.
Danger of unmeant values

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Registered output - 2

No delay between STATE and output changes.

"Spikes" of original Mealy machine are gone!

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Dept of E&C, NITK Surathkal 4

 EC806 DDFPGA

Hazards
 Momentary glitches in circuits during input transitions
 Caused by non-uniform path delays in combinatorial
circuits
 Static hazard
 Single glitch in a circuit during an input transition

 Dynamic hazards
 Multiple glitches in the output during a single input
transition

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Static hazards
 Static – 1 Hazard  Static – 0 Hazard
 Output is 1  Output is 0
 Change in one of the  Change in one of the
inputs inputs
 Momentary transition in  Momentary transition to
output to 0 1 in output
 For SOP circuits  For POS circuits

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 EC806 DDFPGA

Dynamic hazards
 Caused by multiple path delays
 Multiple transitions in output during input changes
 This could be a 0 or 1 hazard.
 Avoid static hazard to avoid dynamic hazards
 Does not occur in 2 level SOP & POS but can occur in multi level
ccts

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Example

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 EC806 DDFPGA

Avoiding Hazards
Use K map effectively
• Consider all combinations that have outputs
• Add redundant prime implications

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Dynamic Hazards
0
W 0
0 slow
X

0 0
Y 1 1
1 1

1
1
1 1
Z

slower

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 EC806 DDFPGA

Dynamic Hazards
0
W 0 1
0 1 slow
X

0 0 10
Y 10 1 0 1
10 1 0 0

10
1
1 1
Z

slower A dynamic hazard occurs when

oscilation may occur when a single
transition is expected.
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Understanding data sheets

• Features
 Features like voltage, current, access time, bus width, clock
speed, special I/O etc. will be listed
• Absolute maximum ratings
 Limiting operational and environmental conditions; putting
the IC above these ratings will affect the reliability &
performance
• Capacitance
 Input, output & in-out capacitance specified along with
temp, load
 Useful to define trace width, trace length, operating
frequency in PCB
 Determine the rise and fall time of the signals
• Recommended operating conditions
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 EC806 DDFPGA

Understanding data sheets

• DC Characteristic
• AC characteristic
 Provide timing data related to signals, clocks,
Inputs, outputs based on the functionality of the
chip
 Timing waveforms used to explain certain
parameters.
• Pin diagrams
• Mechanical diagram
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Rise and Fall time

Caused by stray capacitances
Rise time tr
• Time taken for Low to High transition
Fall time tf
• Time taken for High to Low transition

tr tf

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 EC806 DDFPGA

Input capacitance
• Input capacitance becomes
critical in
• High speed circuits
• Bus loading
• Capacitance get added in
parallel connection
• Increases the rise time and
fall time
• Has impact on the source
and sink current of driver

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clock

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 EC806 DDFPGA

Clock jitter
 The deviations in a clock’s  Cycle-cycle jitter
output transitions from their  is the difference in a clock’s
ideal positions. period from one cycle to the
 The deviation can either be next.
leading or lagging the ideal  Period jitter, short-term jitter,
position.
 is a change in a clock’s output
 Hence, jitter is expressed in transition from its ideal
ns. position over consecutive
clock edges.
 Three types:  Long-term jitter
 is a change in a clock’s output
 cycle-cycle jitter, transition from its ideal
position, over “many” cycles.
 Period jitter,
 “many” is relative to
 long-term jitter. application

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Jitter

CYCLE JITTER

LONG TERM JITTER

SHORT TERM JITTER
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 EC806 DDFPGA

Causes of jitter
 Power supply noise
 The internal PLL of the synthesizer
 Random thermal noise from crystal, or any other
resonating device.
 Random mechanical noise from vibrations of the crystal
 Impact on systems
 affects almost all high-speed synchronous systems.

 graphics cards, and communications equipment.

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Clock skew

 Difference in arrival time of two signals specified to arrive in sync

 Skew can be caused by
 The output skew of the driving device
 Driver buffer could introduce skew due to different propagation delay Or
due to output loading
 Skew in PLL-based devices can be very small since a PLL-based device
can be adjusted to compensate for differences in output loading.
 Board design skew caused by layout variation of board traces
 Causes of Skew
 Trace length of PCB
 Capacitive load
 Threshold difference
 Line termination
 Clock skew becomes critical in high speed designs , making systems
unreliable

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 EC806 DDFPGA

Clock Skew

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Set up and hold time

 Setup time  Hold time

 Describes the length of  Describes the length of
time that the data must time that the data must
be available and stable remain available and
at the flip flop input, stable at the flip flop input,
before the active clock after the active clock
edge edge.
 Limits the maximum  Positive hold time can
clock -rate of a system cause malfunction at any
clock rate.

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 EC806 DDFPGA

Set up and hold time

tsumax = tmin-(tpmax+tdmax) tmin = tsumax+tpmax+tdmax

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Max clock frequency

 Measure of performance of a synchronous sequential
circuit
 Maximum frequency at which the circuit may operate
 Inverse of the minimum clock period tmin.
 The minimum time between successive clock transitions is
tmin > = tpmax+ tdmax+ tsumax
 tp is the propagation delay through the flip flop.
 td is the delay through the combinational logic.
 tsu is the set up time requirements of the flip flop
 th – hold time
 Time difference between the possible change in data with
respect to the slowest clock
th = tpmin + tdmin

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Dept of E&C, NITK Surathkal 14

 EC806 DDFPGA

Clock skew & jitter

 Skew  Jitter
 Clock is expected to reach all ◦ It is the cycle to cycle variation in
FF at the same time. clock arrival
 However there could be delays ◦ Jitter could be due to
due  Inaccurate crystal oscillator
 Placement of FF  Drift in PLL
 Routing (wire delay)  Cross talk between clock and
 Combinational logic .. other signals
 Clock skew is the difference in
clock arrival time of related FF
 Tpmin > tskewmax
+thmax
 Clock distribution trees used to
minimize clock skew

Maximum clock tmin => tpmax + tsumax + tdmax + tskewmax + tjittermax

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