CMOS DIGITAL VLSI DESIGN

CLOCKING STRATEGIES FOR SEQUENTIAL DESIGN - III

SUDEB DASGUPTA
DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

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 Positive Clock Skew
Tclk + δ

Register 1 Register 2 Tclk

Combinational
In D Q D Q out
Block
CLK1

δ
tclk1 tclk2

Clock CLK2
tc _ q tlogic
tc _ q ,cd tlog ic _ cd
δ + th
tsu , t hold

Timing diagram to study the impact of positive clock skew on performance and functionality.

The rising clock edge is delayed by a positive δ at the second register.

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 Positive Clock Skew
• If the clock skew is positive, the time available for
Tclk + δ signal to propagate from R1 to R2 is increased by
the skew δ.
Tclk
• The constraint on the minimum clock period can
then be derived as:
1 3
CLK1 T    tc _ q  tlogic  tsu
δ
• if the minimum delay of the combinational logic
2 4
block is small, the inputs to R2 may change
CLK2
before the clock edge 2, resulting in incorrect
evaluation.
δ + th
• The constraint of the minimum propagation
Timing constraint of positive clock skew delay through the register and logic would be

  thold  tc _ q,cd  tlog ic,cd

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 Negative Clock Skew
• The rising edge of CLK2 happens
Tclk + δ before the rising edge of CLK1.
Tclk • Here δ is negative,
• The constraint on the minimum
1 3
clock period becomes more
CLK1
stringent.
δ

T    tc _ q  tlogic  tsu
2 4
CLK2

Timing diagram for negative clock skew (δ < 0).

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 Example scenarios for positive and negative clock skew

During positive clock skew (δ > 0), the main constraint is   t

hold  tc _ q ,cd  tlog ic ,cd
•
• The circuit does malfunction independent of the clock period.
• During negative clock skew (δ < 0), When the clock is routed in the opposite direction of the data.

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Timing issue in Datapath with feedback

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 Clock jitter
• Clock jitter refers to the temporary variation of the clock period at a given point.
means the clock period can reduce or expand on a cycle-by-cycle basis.
• Cycle-to-cycle jitter refers to time varying deviation of a single clock period,
• At given location i,
Tjitter ,i (n)  Ti ,n 1  Ti ,n  TCLK

Where, Ti,n is the clock period for period n,

Ti, n+1 is clock period for period n+1,
TCLK is the nominal clock period.

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 Circuit performance under clock jitter

• Jitter directly impacts the

performance of a
sequential system.
• The total time available to
complete the operation is
reduced by 2 tjiiter in the
worst case.

Tclk  2t jitter  tc _ q  tlogic  tsu

Timing diagram of a circuit under clock jitter

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 Impact of Clock Skew and Clock Jitter
• A static skew δ is present in two clock
signals (CLK1 and CLK2). (δ >0).
• CLK1 has jitter of tjitter1.
• CLK2 has jitter of tjitter2.
• The constraint on the minimum clock
period -

TCLK    t jitter1  t jitter 2  tc _ q  tlogic  tsu

or
T  tc _ q  tlogic  tsu    t jitter1  t jitter 2
Circuit performance under skew (δ >0). and jitter
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 Source of Skew and Jitter
• A ideal clock signal can not be achieved because of the variety of the process and environmental
variations.
• Off chip or on-chip generated clock signal is distributed through multiple “matched” path.
• Errors can be classified in to two categories :

• 1) Systematic Error
• Predictable.
• Identical in chip to chip 4. Power Supply
• Modeled and corrected at design time. 3. Interconnect

6 . Capacitive load
2. Device
7 . Coupling to Adjacent line

• 2) Random Error 1 . Clock Generation 5. Temperature

• Manufacturing variations
• Difficult to model and eliminate
• e.g., dopant fluctuations

various sources of skew and jitter

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 Sources of Skew and Jitter
1. Clock generation
• Source of clock generator itself causes jitter.
• Core of a PLL is a Voltage Control Oscillator- which is very sensitive to the device
noise and supply variation.
• Analog circuits are affected by noisy digital circuits.
• Cycle-to-cycle clock variation due to substrate noise.

2. Manufacturing Device Variations

• Mismatch among the clock buffer circuits in the distributed network.
• Because of the process variations, device parameters in buffer circuits vary –results
static skew error.
• Variation in oxide layer, dopant profile, dimension ratio affect the over all
performance.

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 Sources of Skew and Jitter
3. Mismatch in Interconnects
• The dimension variations in routing causes interconnect capacitance and
resistances to vary – statics skew between different paths.
• Inter-level-thickness variations.
• Variation in polish rate in planarization process.
• Deviation in the width of the wires and line spacing.

4. Environmental variations
• Most significant sources to contribute jitter and skew.
• Temperature gradient because of variation in power dissipation.
• Activity region is chip varying depending on design.
• Variation in temperature is time varying.

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 Sources of Skew and Jitter
5. Power supply variations
• Major source of clock jitter in circuit.
• Delay through buffers is a very strong function of power supply.
• The buffer delay along one path is very different than the buffer delay along another
path.
• Instantaneous IR drops along the power grid due to fluctuations in switching activity.
• Clock signal is modulated on a cycle-by-cycle basis, resulting in jitter.

6. Capacitive coupling
• The variation in capacitive load also contributes to timing uncertainty.
• Coupling between the clock lines and adjacent signal wires.
• Variation in gate capacitance.
• The adjacent signal can transition in arbitrary directions and at arbitrary times, This
results in clock jitter.

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 Design Techniques to Reduce of Skew and Jitter

• A balanced clock paths from a central distribution sources - using H-tree

structures or routed tree structures.
• The use of local clock grids can reduce skew.
• If data flows in one direction, route data and clock in opposite directions.
• Avoid data dependent noise by shielding clock wires from adjacent signal wires.
• Dummy fills are very common and reduce skew by increasing uniformity.
• High frequency power supply variation can be reduced by addition of on-chip
decoupling capacitors.

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 Clock Distribution

H-tree Grid structures

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 Advantages of Synchronous Design

• Ensures that the physical timing constraint are met

• After the system comes in steady state, only the next clock starts.
• Allowed only the legal values for the next computation.
• Always consider the worst case to ensure physical timing constraint.
• Serves as a logical ordering mechanism
• For a global system events.
• All the system events are clearly orchestrated by clock.
• Structured and deterministic approach.

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 Recapitulation

• As a result of process and environmental variations, the clock signal

can have spatial and temporal variations.
• Clock skew and jitter has a major impact on the functionality and
performance of a system.
• Clock skew is caused by static path-length mismatches in the clock load
and by definition skew is constant from cycle to cycle.
• Realize in clock distribution is that the absolute delay through a clock
distribution path is not important; what matters is the relative arrival
time between the output of each path at the register points.

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Thank You

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