CMOS DIGITAL VLSI DESIGN
Sequential Logic Design - IX
SUDEB DASGUPTA
DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
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Outline
• Pipelining: An approach to optimized Sequential Circuit
(a) Latch vs. Register based Pipelines
(b) NORA-CMOS-A Logic Style
• Non-bistable Sequential Circuits
(a) Schmitt Trigger
• Recapitulation
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Pipelining: An approach to optimized Sequential Circuit
• Pipelining is a popular design technique often used to accelerate the
operation of data-paths in digital processors.
• Let’s take an example to calculate log of ‘a’ and ‘b’ where ‘a’ and ‘b’
are stream of numbers-
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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Cont…
• To ensure correct evaluation the minimal clock period Tmin is-
Tmin=tc-q+tpd,logic+tsu
where tc-q and tsu are propagation delay and the setup time of the
register, respectively. tpd,logic is the worst case delay path through
combinational networks.
• The advantage of pipelined operation becomes apparent when
examining the minimum clock period of the modified circuit.
• The combinational network has been partitioned in three sections, so
if we consider that all blocks have approximately same delay then-
Tmin,pipeline=Tmin/3
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Latches vs. register based Pipelines-
• Pipelined circuits can be conducted by using level-sensitive latches
instead of edge-triggered registers.
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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NORA-CMOS-A logic style for pipelined structures
• A C2MOS based pipelined circuit is a race free as long as all the logic
function F (implementing by using static logic) between the latches
are non-inverting.
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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Cont…
• Potential race condition during (0-0) overlap in C2MOS based design.
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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Cont…
• Example of NORA-CMOS modules.
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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Non-bistable Sequential Circuits
The Schmitt Trigger
• The Schmitt Trigger responds to a slowly changing input waveform
with a fast transition time at the output.
• The VTC of the device displays different switching threshold for
positive and negative going input signals.
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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Cont…
• The CMOS implementation of Schmitt Trigger is as follows-
Source: J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuit,” PHI Learning Pvt. Ltd., 2011.
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Recapitulation
• Pipeline is an approach to improve the source utilization and increase
the fundamental throughput.
• The pipeline system is implemented using pass transistor based
positive and negative latches instead of master-slave system.
• A NORA data path consists of a chain of alternating CLK and CLK
modules.
• The Schmitt Trigger is based on positive feedback.
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Thank You
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