M&A Unit 2
M&A Unit 2
CIP-51 Architecture
CIP-51 Architecture
• Reset sources
• Oscillator options
• Memory Organization
• Port structure
• Timers
• Timer programming
• Interrupt handler
Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software.
The WDT may be permanently enabled in software after a power-on reset during MCU
initialization.
Reset sources
SFR: RSTSRC- Reset Source
Oscillator options
Four Oscillator options
• 4x Clock Multiplier.
Oscillator Diagram
Oscillator options
• The internal high-frequency and low-frequency oscillators can be
enabled/disabled and adjusted using the special function registers OSCICN &
OSCLCN
• The system clock (SYSCLK) can be derived from either of the internal
oscillators, the external oscillator circuit, or the 4x Clock Multiplier divided
by 2.
• The USB clock (USBCLK) can be derived from the internal oscillator,
external oscillator, or 4x Clock Multiplier.
SFR: OSCICN - Internal H-F Oscillator Control
SFR: OSCLCN- Internal L-F Oscillator Control
SFR: CLKSEL - Clock Select
• Solution: Pick and choose the peripherals that are necessary for an application, and assign only
those to external pins
• This is the function of the crossbar
• Based on the application, the system designer makes the decision as to which peripherals are
enabled, and which pins are used
• The C8051F340 has a rich set of digital resources like UARTs, system management bus (SMBus),
timer control inputs and interrupts
• These peripherals do not have dedicated pins through which they may be accessed
• They are available through the four lower I/O ports (P0, P1, P2 and P3)
• Each of the pins on P0, P1, P2 and P3 can be defined as a general purpose input/output
(GPIO) pin or can be assigned to a digital peripheral
• Lower ports have dual functionalities
• This flexibility makes the MCU very versatile
Crossbar Pin Assignment and Allocation Priority
• The crossbar has a priority order in which peripherals are assigned to pins
• UART0 has the highest priority and UART1 has the lowest priority
• There are three configuration registers, XBR0, XBR1 and XBR2, which are
programmed to accomplish the pin allocations
• If the corresponding enable bits of the peripheral are set to a logic 1 in the crossbar
registers, then the port pins are assigned to that peripheral
• Pin assignments to associated functions are done in groups
• For example, TX0 and RX0 for UART0 are assigned together
• Example: If the UART0EN bit (XBR0.0) is set to logic 1, the TX0 and RX0 pins will be
mapped to the port pins P0.4 and P0.5, respectively.
• Since UART0 has the highest priority, its pins will always be mapped to P0.4 and
P0.5 when UART0EN is set to logic 1 and will have precedence over any other
peripheral allocation
XBR0, XBR1, XBR2
XBR0 (Crossbar Register 0)
XBR1 (Crossbar Register 1)
XBR2 (Crossbar Register 2)
Port structure
• Designer has complete control over which functions are assigned, limited only by
the number of physical I/O pins.
• The Digital Crossbar allows mapping of internal digital system resources to Port
I/O pins. On-chip counter/timers, serial buses, HW interrupts, comparator
outputs, and other digital signals in the controller can be configured to appear on
the Port I/O pins specified in the Crossbar Control registers. This allows the user
to select the exact mix of general purpose Port I/O and digital resources needed for
the end application.
• This resource assignment flexibility is achieved through the use of a Priority
Crossbar Decoder.
• State of a Port I/O pin can always be read in the corresponding Port latch,
regardless of the Crossbar settings.
• The Crossbar assigns the selected internal digital resources to the I/O pins based
on the Priority Decoder
• The registers XBR0, XBR1, and XBR2 defined in SFR definition
• These SFRs used to select internal digital functions
Port I/O -Functional block diagram
Priority Crossbar Decoder
• The Priority Crossbar Decoder assigns a priority to each I/O function, starting at
the top with UART0. When a digital resource is selected, the least-significant
unassigned Port pin is assigned to that resource (excluding UART0, which is
always at pins 4 and 5).
• If a Port pin is assigned, the Crossbar skips that pin when assigning the next
selected resource. Additionally, the Crossbar will skip Port pins whose associated
bits in the PnSKIP registers are set.
• The PnSKIP registers allow software to skip Port pins that are to be used for
analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral
without use of the Crossbar, its corresponding PnSKIP bit should be set.
The Crossbar must be enabled to use Ports P0, P1, P2, and P3 as standard Port I/O
in output mode. These Port output drivers are disabled while the Crossbar is
disabled.
Port 4 always functions as standard GPIO.
Port I/O Initialization
• Port I/O initialization consists of the following steps:
Step 1. Select the input mode (analog or digital) for all Port pins,
using the Port Input Mode register (PnMDIN).
Step 2. Select the output mode (open-drain or push-pull) for all Port
pins, using the Port Output Mode register (PnMDOUT).
Step 3. Select any pins to be skipped by the I/O Crossbar using the
Port Skip registers (PnSKIP).
Step 4. Assign Port pins to desired peripherals (XBR0, XBR1).
Step 5. Enable the Crossbar (XBARE = ‘1’).
Important points to configure the crossbar
• Analog Input-
Any pins to be used as Comparator or ADC inputs should be configured as an analog
inputs. When a pin is configured as an analog input, its weak pull-up, digital driver,
and digital receiver are disabled. This process saves power and reduces noise on the
analog input.
Additionally, all analog input pins should be configured to be skipped by the Crossbar
(accomplished by setting the associated bits in PnSKIP).
• Digital input-
Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input,
and a ‘0’ indicates an analog input.
All pins default to digital inputs on reset.
General Purpose Port I/O
• Port pins that remain unassigned by the Crossbar and are not used by
analog peripherals can be used for general purpose I/O.
• Ports 3-0 are accessed through corresponding special function registers
(SFRs) that are both byte addressable and bit addressable.
• Port 4 uses an SFR which is byte-addressable.
• When writing to a Port, the value written to the SFR is latched to
maintain the output data value at each pin.
• When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings
Port0 Latch
Port0 Input Mode
Port0 Output Mode
Port0 Skip
Port SFRs
• Port 0 to Port 3
Portx Latch
Portx Input Mode
Portx Output Mode
Portx Skip
• TH0 and TL0 holds the count. When the count in TH0 and TL0
overflows from all ones to 0x00, the timer overflow flag is set. The
count in TH0 and TL0 should be loaded for next iteration.
1
Timer 0 & 1 Mode 2: 8bit Counter/Timer with Auto-Reload
• Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit
counter/timers with automatic reload of the start value.
• TL0 holds the count and TH0 holds the reload value. When the counter
in TL0 overflows from all ones to 0x00, the timer overflow flag TF0
(TCON.5) is set and the counter in TL0 is reloaded from TH0.
•Timer 1 in mode 1
•Timer 1 in mode 2
•Timer 0 in mode 1
•Timer 0 in mode 2
•Timer 1 in mode 2 and Timer 0 in mode 1
Time Delay Calculations – For Mode 1
Time period of 1clock cycle = (1/SystemClock)
• The (sub) program that deals with an interrupt is called an interrupt service
routine (ISR) or interrupt handler
Interrupts
• An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.
Interrupts vs. Polling
• A single microcontroller can serve several devices.
• There are two ways to do that:
• interrupts
• polling.
• The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
Interrupts
• When an interrupt occurs, the main program temporarily suspends execution
and branches to the ISR
• The ISR executes, performs the desired operation, and terminates with a “return
from interrupt” (RETI) instruction
• The RETI instruction is different from the normal “RET” instruction
• Starts to execute the interrupt service routine until RETI (return from interrupt).
• Upon executing the RETI the microcontroller returns to the place where it was
interrupted. Get pop PC from stack
Execution Flow Reset
Push PC
on Stack
Execute Push
Main Code Registers
on Stack
Timer Overflow
Interrupt Occurs
At This Time Execute
ISR Code
Pop
Registers
from Stack
Continue to
Execute Pop PC
Main Code from Stack
Interrupt handler
• Interrupt handler provides 16 interrupt sources into the CIP-51 (as
opposed to 7 for the standard 8051), allowing numerous analog and digital
peripherals to interrupt the controller.
1. Idle
2. Stop.
Power Control Register (PCON)
Power Control Register (PCON) is used to control the CIP-51's
power management modes.
• SFR Definition PCON: Power Control
Idle mode
• Idle mode-
• Halts the CPU
• internal registers and memory maintain their original data
• Peripherals and clocks active.
• Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the
CPU and enter Idle.
• Idle mode is terminated when an enabled interrupt is asserted or a
reset occurs. The assertion of an enabled interrupt will cause the Idle
Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation.
• If enabled, the Watchdog Timer (WDT) will eventually cause an
internal watchdog reset and thereby terminate the Idle mode.
Stop mode
• Stop mode-
• CPU is halted
• All interrupts inactive
• Internal oscillator is stopped
• All digital & analog peripherals stopped
• External oscillator circuit is not affected
• Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon
as the instruction that sets the bit completes execution.
• Stop mode can only be terminated by an internal or external reset.
• If enabled, the Missing Clock Detector will cause an internal reset and there by terminate
the Stop mode.
• The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode
for longer than the MCD timeout of 100 μsec
Reference
Datasheet:
https://www.silabs.com/documents/public/datasheets/C8051F34x.pdf
Timers in C8051F340 Microcontroller
Timers
• Timers are used for: interval timing, event counting or baud rate
generation
• In interval timing applications, a timer is programmed to overflow at a
regular interval and the following:
• Set the timer overflow flag or
• Generate an interrupt
• This can also be used to generate waveforms at set frequencies
• Event counting is used to determine the number of occurrences of an
event, rather than to measure the elapsed time between events. In
this case, the timer functions as a counter.
• An “event” is any external stimulus that provides a high-to-low transition at the
selected input pin
• The timers can also function as the baud rate generators for the
C8051F340’s internal serial ports (UART0 and UART1)
• “Baud rate” is the bit rate of the serial port
(the time period of a bit)
Timers
• CIP51 has four counter/timers: Timer 0, Timer 1,
Timer 2 and Timer 3
• Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation.
• Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality
with auto-reload.
Timer 0 & 1 Mode 1: 16bit Counter/Timer
• TH0 and TL0 holds the count. When the count in TH0 and TL0 overflows
from all ones to 0x00, the timer overflow flag is set. The count in TH0
and TL0 should be loaded for next iteration.
• If Timer 0 interrupts are enabled, an interrupt will occur when the TF0
flag is set. The count in TH0 and TL0 should be loaded for next iteration.
T0 Mode 1 Block Diagram
https://www.youtube.com/watch?v=kaCOTQwo7KY
Timer 0 & 1 Mode 2: 8bit Counter/Timer with Auto-Reload
• TL0 holds the count and TH0 holds the reload value. When the counter in
TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5)
is set and the counter in TL0 is reloaded from TH0.
• If Timer 0 interrupts are enabled, an interrupt will occur when the TF0
flag is set. The reload value in TH0 is not changed. TL0 must be initialized
to the desired value before enabling the timer for the first count to be
correct. When in Mode 2, Timer 1 operates identically to Timer 0.
T0 Mode 2 Block Diagram
Steps to program 8-Bit Auto-Reload Mode
(Mode 2)
• This mode configures Timers 0 (and 1) to operate as 8-bit counter/timers with automatic reload of
the start value
• The timer low byte (TLx) operates as an 8-bit timer while the timer high byte (THx) holds a reload
value
• When the count in TLx overflows from FFH to 00H, the timer flag is set and the value in THx is
automatically loaded into TLx
• Counting continues from the reload value up to the next FFH overflow, and so on
• This mode is convenient for creating regular periodic intervals, as the timer overflows at the same
rate once TMOD and THx are initialized
• TLx must be initialized to the desired value before enabling the timer for the first count to be
correct
• Timer 1 can be used as an 8-bit baud rate generator for UART0 and/or UART1 in mode 2
SFR- CKCON: Clock Control
SFR- CKCON: Clock Control
SFR TMOD: Timer Mode
SFR TMOD: Timer Mode
SFR TCON: Timer Control
SFR TCON: Timer Control
Configure TMOD register for the following:
• Timer 0 in mode 1 - 0x01H
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
0 0 0 0 0 0 0 1
• Timer 1 in mode 2 –?
• Timer 0 in mode 2 –?
• Timer 1 in mode 2 and Timer 0 in mode 2 – ?
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
Configure TMOD register for the following:
• Timer 0
Gate1 C/T1 T1M1 T1M0 Gate0 C/T0 T0M1 T0M0
Delay Required=
3mSec
Procedure for Time to Count Calculation– For Mode 2
Time period of 1clock cycle = (1/SystemClock)