Chapter Four:

Peripheral Interfacing
Study of Architecture and Programming of Interfacing Ics like :

 8255 Programmable Peripheral Interface(PPI) .

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 Interfacing Fundamentals
Interface Definitions
 Interface -A shared boundary between system elements defined by common physical

interconnection characteristics, signal characteristics.

 Interface Device(IDs )-A device that meets the interface specifications on one side of an

interface.

 Interface Specification -A set of technical requirements that must be met at an interface .

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 Components of Interface:

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 Data Transfer Schemes
 The data transfer schemes refers to the method of data transfer

between the processor and peripheral devices.

In a typical microcomputer, data transfer takes place between any two

devices:

 Microprocessor and memory

 Microprocessor and I/O devices
 Memory and I/O devices.
.

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 Cont…
 The data transfer schemes between microprocessor ,memory and peripherals have been
broadly classified into the following two categories.

A. Programmed data transfer.

B. Direct memory access data transfer (DMA)

For effective data transfer between these devices, the timing

parameters of the devices should be matched. But most of the devices
have incompatible timings

slow memories can be interfaced using additional hardware to

introduce wait states in machine cycles

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6 1/2/20
In this scheme, the transfer of data is
PROGRAM CONTROLLED DATA TRANSFER

completely under the control of the

microprocessor program.

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Data transfers can take place synchronously or asynchronously. Synchronous

transfers mean transfers occurring at the same time. The sender and the receiver

are synchronized to operate at the same clock speed.

This is preferred when the speeds of both the sender and the receiver match.

Synchronous transfers are used in high-speed transmission.

Asynchronous transfers mean transfers taking place at irregular intervals. These

are used in low -speed transmission.

Data transfers between the microprocessor and the peripherals are primarily

asynchronous.

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 Synchronous data
transfer scheme
 The synchronous data transfer scheme is the simplest of
all data transfer schemes.
 In this scheme the processor does not check the
readiness of the device
The I/O device or peripheral should have matched timing
parameters.
Asynchronous Data Transfer Schemes
 The asynchronous data transfer scheme is employed
when the speed of
processor and I/O device does not match

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10 1/2/20
 OUTLINEES
Introduction to I/O Interface
Clock Generator (8284A)
 Bus Timing
8255A-PPI

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 Introduction to I/O Interface
There are two different methods of interfacing I/O to the microprocessor:

 1. Isolated I/O

 IN and OUT instruction transfer data b/n the microprocessor’s accumulator or memory and

the I/O device

 Common I/O transfer technique used

 Addresses for isolated I/O devices, called ports, are separate from memory

 Data transferred b/n I/O and the microprocessor must be accessed by the IN, INS, OUT,

and OUTS instructions.

 An 8-bit port address is used to access devices located on the system board

 A 16-bit port is used to access serial and parallel ports as well as video and disk drive

system
2. Memory-mapped I/O
Any instruction that references memory can accomplish the
transfer.
Does not use the IN, INS, OUT, and OUTS instructions
it uses any instruction that transfers data between the
microprocessor and memory
The main advantage of memory-mapped I/O is that any
memory transfer instruction can be used to access the I/O device
The main disadvantage is that a portion of the memory system
is used as the I/O map. This reduces the amount of memory
available to applications.
 The Basics Input Interface
 The basic input device is a set of three-state buffer used to

construct the 8-bit input port

 The circuit below allows the microprocessor to read the contents

of the 8 switches
 Whenever the IN instruction executes, the contents of the

switches are copied into the AL register.

 The I/O port address is decoded to generate the logic 0 on SEL

(neg.) A 0 on the output control inputs (1G (neg.) and 2G(neg.)) of

the 74ALS244 buffer causes the data input connections (A) to be
connected to the data output (Y) connections.
Cont’d…

n t er face
inp ut i
ba sic
t he
 The Basics Output Interface
 Receives data from the microprocessor and must usually hold it
for some external device

 Figure shows how 8 simple LEDs connected to the microprocessor

through a set of 8 latches

 Latches are needed to hold the data because when the microprocessor executes
an OUT instruction, the data are only present on the data bus for less than 1.0
μs.s.
 The data are held until the next OUT instruction executes.
Cont’d…

the basic output interface

 Programmable Peripheral Interface(PPI)

Introduction
 to Programmable Peripheral Interface IC
8255- PPI


The Intel 8255A is a high-performance, general purpose

programmable I/O interfacing device which is designed for

use with all Intel and most other microprocessors.

It
 provides 24 I/O pins which may be individually programmed

in 2 groups of 12 and used in 3 major modes of operation .

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 8255A Pin
Configuration
 Pin diagram:
D0-D7 (Data Bus)
PA0-PA7 (port A)
PB0-PB7 (port B)
PC0-PC7 (port C): two
groups
PCL (PC3-PC0) and PCU
(PC7-PC4)
 (Read)
 (Write)
(Chip Select)
Reset
A0 and A1

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 Block Diagram of 8255

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 1. The Data Bus Buffer

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 1. The Data Bus Buffer

 This tri-state bidirectional buffer is used to interface the internal data

bus of 8255 to the system data bus (8086

 Input/output instructions by 8086 either Read/Write.

 Input/ Output data to/from the CPU to the ports or control register,

are all passed through this buffer.

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 Read/Write Control Logic
This unit accepts control signals ( RD, WR ) and also inputs from address bus and issues

commands to individual group of control blocks ( Group A, Group B).

It has the following pins:

a) CS – Chipselect : A low on this PIN enables the communication between CPU and 8255.

b) RD (Read) :A low on this PIN enables the CPU to read the data in the ports or the status word

through data bus buffer.

c) WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on to the control

register through the data bus buffer.

d) RESET: A high on this pin clears the control register and all ports are set to the input mode

e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins control the

selection of one of the 3 ports.

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 Read/Write Control Logic

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 Group A and Group B
controls
These block receive control from the CPU and issues commands to
their respective ports.
 Group A - PA and PCU ( PC7 –PC4).

Group B – PB and PCL ( PC3 – PC0)

• Control word register can only be written into no read operation of the CW register is
allowed.

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 PORTS
A). Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch.
a) It can be programmed in 3 modes – mode 0, mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It
can be programmed in mode 0, mode1.

c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched
/buffer. This port can be divided into two 4 bit ports and can be used as
control signals for port A and port B. it can be programmed in mode 0.

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 Programming the 8255

 The 8255 can be programmed to operate in three I/O modes of operation and BSR.

 Bit set Reset (BSR)

 Mode 0 Operation (basic input/output):

 Mode 1 Input or output with Handshaking

 Mode 2 Bi directional IO with Handshaking

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 Bit Set Reset Mode (BSR) Mode
In this mode any of the 8-bits of port C can be set or reset
depending on D0 of the control word. The bit to be set or
reset is selected by bit select flags D3, D2 and D1 of the
CWR as given in table.

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 BSR control word has D7 = 0;
 BSR control word does not affect any previously transmitted I/O
control word
with D7 = 1. ;
 BSR CONTROL WORD
 This is shown in fig below. it sets or resets port C bits, one bit at a
time
 Used in ON/OFF Switches

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 Example
Consider the interface circuit shown in fig (a) below
write a BSR control word subroutine to set PC7 , PC6
and PC3 and reset PC7 & PC3 after 10 ms. Assume
that delay routine is available.
BSR CONTROL WORDS for:
D7 D6 D5 D4 D3 D2
D1 D0
i) Setting PC7 0 X X X 1 1
1 1 (OF)H
ii) Setting PC6 0 X X X 0 1
1 1 (O7)H
iii) Resetting PC7 0 X X X 1 1
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 Interfacing Circuit

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 Mode 0
I/O Modes :

Mode 0 ( Basic I/O mode ): This mode is also called as basic input/
output mode.

This mode Provides simple input and output capabilities using each
of the three ports.

Data can be simply read from and written to the input and output
ports respectively, after appropriate initialization.

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 Programmable Peripheral Interface
(8255)

Figure 4-44 shows a diagram of the 8255 and its I/O

and control signals.

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 Programmable Peripheral Interface
(8255)
 Interfacing the 8255

 When the address bus contains one of these four port addresses during an I/O access, ( CS) ̅ will will

be pulled low. The 8255 will internally decode the states of A0 and A1 and determine which port

to access.
 In this example, port A has port address A0H, Ports B and C are accessed through ports A1H and

A2H, respectively, and the control port is at A3H.

 The nicest feature of the 8255 is that different hardware circuits can be connected to ports A, B,

and C, with the direction (input or output) of each port configured with initial programming.
 This allows an 8088/86-based system with an 8255 in it to be used for many different purposes.

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 CONROL WORD

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 Programmable Peripheral Interface
(8255)
 The first is mode 0: basic input/output. In this mode, ports A, B, and C can
be individually programmed as input or output ports. Port C is divided
into two 4-bit halves, directionally independent from each other.

Example 4-5: Find the control (mode) word if PA= out, PB= in, PCO - PC3 =in, and
PC4 - PC7 =out. And program the 8255 to get data from port A and send it to port B. In
addition, data from PCL is sent out to the PCU.

Use port addresses of 300H - 303H for the 8255 chip.

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 Programmable Peripheral Interface
(8255)
Solution: From Figure 4-45 we get the control word of 10000011 in binary or 83H.
From the given address range 300H is port address for PA, 301H for PB, 302H for
PC and 303H for control register.

The program code is as follows:

MOV DX, 303H ; Load control reg. address (303H) to DX
MOV AL, 83H ; Load control byte
OUT DX, AL ; send it to control register
MOV DX, 301H ; load PB address
IN AL, DX ; get the data from PB
MOV DX, 300H ; load PA address
OUT DX, AL ; send it to PA
MOV DX, 302H ; load PC address
IN AL, DX ; get the bits from PCL
AND AL, 0FH ; mask the upper bits
ROL AL, 1
ROL AL, 1 ; shift the bits
ROL AL, 1 ; to upper position
ROL AL, 1
OUT DX, AL ; send it to PCU

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 Programmable Peripheral Interface
(8255)
Example 4-6: The 8255 shown in Figure 4-46 is configured as follows: port A as input,
B as output, and all the bits of port C as output.

(a) Find the port addresses assigned to A, B, C, and the control register.
(b) Find the control byte (word) for this configuration.
(c) Program the ports to input data from port A and send it to both ports B and C.

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 Programmable Peripheral Interface
(8255)
Solution: (a) From decoding NAND gate circuit shown in the figure, the port
addresses are as follows:
ത
ത
𝑺ത
𝑪ത A1 A0 ADDRESS PORT
11 0001 00 0 0 310H Port A
11 0001 00 0 1 311H Port B
11 0001 00 1 0 312H Port C
11 0001 00 1 1 313H Control Register
(b) From Figure 4-45 we get the control word of 1001 0000 in binary or 90H.
(c) Based on the addresses of ports found in (a) we can write the following
program.
MOV AL, 90H ; control byte PA=in, PB=out, PC=out
MOV DX, 313H ; load control reg address
OUT DX, AL ; send it to control register
MOV DX, 310H ; load PA address
IN AL, DX ; get the data from PA
MOV DX, 311H ; load PB address
OUT DX, AL ; send it to PB
MOV DX, 312H ; load PC address
OUT DX, AL ; and to PC
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 Programmable Peripheral Interface
(8255)
 Mode1 Operation:

 In this mode, the 8255 uses port C as a handshaking port.

 Ports A and B can be programmed for input or output.

 Data are latched in both directions.

 If port A is programmed for input, a strobe signal is

needed on PC4 to write data into port A.

 (Strobe Input): A ``low'' on this input loads data into the

input latch.

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 Programmable Peripheral Interface
(8255)
 Mode1 Operation:

 The 8255 will acknowledge the new input data by outputting a 1 on PC5.
PC5 is IBFa, input buffer A full. IBF is cleared when the processor reads
port A.
 IBFa: A ``high'' on this output indicates that the data has been loaded into
the input latch; in essence, an acknowledgement.
 IBF is set by input being low and is reset by the rising edge of the input.

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 Programmable Peripheral Interface
(8255)
 Mode1 Operation:
 Port B operates in the same way, using PC2 and PC1 as handshaking signals.
 Both ports have the capability of causing an interrupt when data is strobed into
them.
 The INTR output will go high when IBF goes high and the internal interrupt-
enable bit is set.
 PC4 and PC2 make up the interrupt-enable bits for ports A and B. Setting PC4
will cause INTRa to go high when data is strobed into port A.
 Reading the input port will clear the interrupt request. This interrupt mechanism
is a useful alternative to using software to constantly poll the input port.

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Mode 1 (Strobed I/O mode)
the handshaking signals control the input or
output action of the specified port
The salient features of mode 1 are listed as:
o Two groups-group A and group B are available for
strobed data transfer.
o Each group contains one 8-bit data I/O port and one 4-
bit control/data port.
o The 8-bit data port can be either used as input or
output port.
o Out of 8-bit port C, PC0-PC2 are used to generate
control signals for port B and PC3-PC5 are used to
generate control signals for port A. The lines PC6, PC7
may be used as independent data lines.
 Programmable Peripheral Interface
(8255)
 Mode1 Operation:

 when the 8255 is configured for output in mode 1, we have output buffer full

() and acknowledge () signals used to handshake with the output circuitry.

 will go low when the processor writes to port A or B.

 This signal will remain low until a low pulse arrives on .

 is used to indicate that the new output data was received. , together with

interrupt-enable, can be used to generate an interrupt with INTR.

 This would interrupt the processor when the new output data has been read

and avoid the need to poll the signal.

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Mode 2 (Strobed bidirectional I/
O)
provides 8255 with additional feature for
communicating with peripheral device on
an 8-bit data bus
Handshaking signals are provided to
maintain proper data flow and
synchronization between the data
transmitter and receiver.
Thus in this mode, 8255 is a bidirectional 8-
bit port with handshake signals
The RD (neg.) and WR (neg.) signals decide
whether the 8255 is going to operate as an
input port or output port.
 Programmable Peripheral Interface
(8255)
 Mode1 Operation:


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Cont’d…
The salient features of mode 2 of 8255
are:
The single 8-bit port in group A is available.
The 8-bit port is bidirectional and
additionally a 5-bit control port is available.
Three I/O lines are available at port C, viz.
PC2-PC0
Inputs and Outputs are both latched.
The 5-bit control port C (PC3-PC7) is used
for generating/accepting handshake signals
for 8-bit data transfer on port A.
 Programmable Peripheral Interface
(8255)

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