University of Gondar Institute of Technology

IoT
Microprocessors and Interfacing
(CoEng4092)

Lecture-06: 8086 Input/Output Interfacing

By Beyene Jember
 Outline
 Basic I/O interface
 Serial and Parallel communication
 Handshaking and Handshaking Signal
 Parallel Data Transfer
 8255A Internal Block Diagram
 Description of 8255A Internal Block Diagram
 Programming Modes of 8255A

1
 Introduction
 A microprocessor is great at solving problems, but, if it can not communicate with the outside
world, it is of little worth.
 The I/O interface permits the microprocessor to communicate with the outside world. e.g. to
control an external device
 The 8086 microprocessor can only access external components (including memory devices) via
the address and data buses.
 The mechanism is similar to the memory interface because the CPU is using the same set of
buses – data and address
 Data transfer still takes place over the multiplexed address/data bus
 M/IO signal is set to 0 to indicate I/O operations (this is the only different between
read/write of an I/O and memory)
I/O and Memory interface
Pin Diagram of 8086 Microprocessor
 I/O and Memory interface…
 To connect to external I/O devices, usually some interface circuits are required which is used
to bridge the microprocessor and the I/O devices.
 Functions of the interface:-
 Select the I/O port (decoding)
 Latch output data
 Adjust the signal levels
 The interface between the CPU and an external device is called an I/O Port.
 I/O port is similar to address location in memory(i.e. each Port has an unique number).
 Only address/data lines from 0-15 are used for interfacing with external I/O devices
 When an I/O device is connected to a CPU the device will occupy an I/O port
 Each port can support 8-bit data (read or write)
 If an external device requires 16-bit data then it will occupy two ports
 Block diagram for IO system

The control signals

are same as those
used in memory
operations

Minimum-mode 8086 system I/O interface

 I/O Ports

 I/O Port addresses (or Port numbers ) are generated by the microprocessor via the ADn
lines and after proper decoding , correct I/O port can be selected.
 The I/O address is stored in register DX as a 16-bit address or in the byte (p8)
immediately following the opcode as an 8-bit address.
 The 8-bit fixed port number appears on address bus connections DA0–DA7 with bits A0–
A15 held at 0.
 The 16-bit variable port number (DX) appears on address connections A15–A0.
 Connections above A15 are undefined for I/O instruction
 The first 256 I/O port addresses (00H–FFH) are accessed by both fixed and variable I/O
instructions.
 I/O address from 0100H to FFFFH is only accessed by the variable I/O address
 I/O ports for a PC
• In a PC computer, all 16 address bus bits are decoded with locations 0000H–03FFH.

• Used for I/O inside the PC on the ISA (industry standard architecture) bus

03FF – 03F8 COM1

02FF – 02F8 COM2
03DF – 03D0 CGA adapter
037F – 0378 LPT1
032F – 0320 Hard disk
0063 - 0060 8255 (PPI)
0043 – 0040 Timer
0023 – 0020 Interrupt controller
000F - 0000 DMA controller
 The I/O Instructions
 How to read/write from/to I/O devices?
• In 8086, IN and OUT are I/O instructions.
 Fixed (direct ) port
• Allows data transfer between AL /AX and an 8-bit I/O port address.
• In this mode the max. port number is 255 (FF) i.e. 256 byte ports
• IN - input from port into AL or AX
• OUT - Output from AL or AX to port
 Variable (indirect) port
• Allows data transfer b/n AL /AX and a 16-bit port address stored in DX.
• This mode of addressing can access 64K ports (WHY?)
• IN - input from DX into AL or AX
• OUT - Output from AL or AX to DX
 The I/O Instructions
Example:
Data are to be read in from two byte-wide input ports at address AA and A9, respectively,
and then output as a word to a word-wide Output port at address B000. Write a sequence
of instructions to Perform this I/O operation.

IN AL, AA ; move data in from port address AA

MOV AH, AL ; move data from AL to AH
IN AL, A9 ; move data from port address A9
MOV DX, B000 ; move port address B000 to DX
OUT DX, AX ; can I do OUT B000, AX instead ???

AH AL
Data from AA Data from A9
 I/O COMMUNICATION METHODS
 Serial communication
 Is the process of sending data one bit at one time, sequentially, over a communication
channel or computer bus.

Examples of serial communication architectures

• RS-232 • Ethernet
• I²C (Inter Integrated Circuit) • Fibre Channel
• SPI (Serial Peripheral Interface) • SATA (Serial Advanced Technology Attachment)
• USB (Universal Serial Bus) • PCI (Peripheral Component Interconnect) Express
• FireWire 12
 I/O COMMUNICATION METHODS

 Parallel communication
• In parallel communication, on the other hand, several bits are sent together on a link
comprising of several wired channels in parallel.

Examples of parallel communication architectures

• Printer port • ATA (Advanced Technology Attachment )

• ISA (Industry Standard Architecture) • SCSI (Small Computer System Interface) 13

• PCI
 Serial vs. Parallel
 Serial circuitry is simple and cheap.
 Parallel circuitry is complex and expensive.
 In parallel communication, you can send many bits at once; however, receive 'at once' is not a
true statement.
 Each bit travels a slightly different path down the cable and to a different pin on the chip .
 The small differences in path length that each bit travels becomes more and more significant
as speed increases.
 Therefore, some sort of buffering and synchronization is necessary.
 In serial communication, no such a problem exists.
 So, after a certain speed and distance threshold, serial communication is superior.

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 Interfacing processors to serial and parallel devices

• Processors use peripheral interface circuits to interface to serial and parallel devices.

• These circuits are either provided as separate integrated circuits or built inside the
processor.

 Examples:

• A UART (Universal asynchronous receiver/transmitter) is used for serial

communications over a computer or peripheral device serial port.

• Intel 8255 chip is used to give the CPU access to programmable parallel I/O.

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 8255A
 The 8255A is a widely used, programmable, parallel I/O device.
 It can be programmed to transfer data under various conditions, from simple I/O to
interrupt I/O.
 It is compatible with all intel and most other microprocessors.
 It is completely TTL compatible.
 It provides three 8-bit ports (Port A, Port B, and Port C) which are arranged in to group
of 12 pins
Pin Configuration of Intel 8225 PPI

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8255A Internal Block Diagram

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 Description of 8255A Internal Block Diagram
 Data Bus Buffer
• This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data
bus.
• Data is transmitted or received by the buffer upon execution of input or output
instructions by the CPU.
• Control words and status information are also transferred through the data bus buffer.
 Read/Write Control Logic
• The function of this block is to manage all of the internal and external transfers of both
Data and Control or Status words.
• It accepts inputs from the CPU address and control buses and, in turn, issues command to
both the control groups.
Chip Select (CS) : A "low" on this input pin enables the communication between the
8255 and the CPU. It is connected to the output of address decode circuitry to select the
device when it is addressed.
 Description of 8255A Internal Block Diagram…

(RD) Read
• A "low" on this input pin enables 8255 to send the data or status information to the CPU
on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write
• A "low" on this input pin enables the CPU to write data or control words into the 8255.
(RESET) Reset
• A "high" on this input initializes the control register to 9Bh and all ports (A, B, C) are
set to the input mode.

(A0 and A1)

• These input signals, control the selection of one
of the three ports or the control word register.
 Description of 8255A Internal Block Diagram…
The basic operation of these control signals is given in the following Table:
 Description of 8255A Internal Block Diagram…
 Group A and Group B Controls
• Each of the Control blocks (Group A and Group B) accepts "commands" from the CPU
as "control word" and configure the ports (Port A, Port B and Port C) accordingly.
• Port A and upper 4 bits of Port C are controlled by Group A
• Port B and lower part of Port C are controlled by Group B

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 Description of 8255A Internal Block Diagram…
 Ports A, B, and C
• The 8255 has three 8 bit I/O ports and each one can be connected to the physical lines of
an external device.
• All can be configured to a wide variety of functional characteristics by the system
software .
• These ports are labeled as
• PA0-PA7 Port A
• PB0-PB7 Port B
• PC0- PC7 Port C

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 Description of 8255A Internal Block Diagram…
 Data I/O Lines
• D0-D7 - These are the data input/output lines for the device.
• All information read from and written to the 8255 occurs via these 8 data lines

 GND (Ground) and Vcc

 Summary of 8255A Pins

 Port Pins: 24 ( Port A = 8, Port B =8, Port C =8)
 Control Pins: 6 (RD, WR, CS, RESET, A1, A0)
 Data Lines: 8
 Power Supply: 2 (VCC, GND)
 Total 40 pins

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 Handshaking
 The making of inter relation between slower peripheral device and microprocessor is called
handshaking.
 Handshaking Signal
 Before making the inter-relation between peripheral device and microprocessor the PPI
send some signals to microprocessor and peripheral device to perform the process,
these signals are called handshaking signal.
 8255-based devices that perform handshaking support following handshaking signals:

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 Handshaking Signal…
 Strobe Input(STB)
 This is an active low input signal for 8255 and output signal for the input device.
 The input device activates this signal to indicate CPU that the data to be read is
already sent on the port lines of 8255 port.
 Upon activation of this signal 8255 loads the data from the input port lines into the
input buffer of that port.
 Input Buffer Full(IBF)
 This is an active high output signal for 8255 and an input signal for input device.
 This signal is generated by 8255 in response to STB signal as an acknowledgment to
input device.
 It also indicates to the input device that the input buffer is full and it is not ready to
accept next byte from the input device.
 Therefore input device sends data on the port lines only when IBF signal is not active.
 The IBF signal is deactivated when CPU reads the data from input buffer of the
respective port by activation of RD signal. 26
 Handshaking Signal…
 INTR (Interrupt Request)
 This is an active high output signal generated by 8255.
 A 'high' on this output can be used to interrupt the CPU when an input device is
requesting service.
 The 8255 sets the lNTR when STB signal 'one', IBF signal is 'one' and INTE is 'one',
indicating CPU that the data from the input device is available in the input buffer.
 This signal is reset by the falling edge of the RD signal i.e. immediately after reading
the data from the input buffer.
 Interrupt Enable (INTE)
 Is a flip-flop that used to enable or disable INTR signal. If INTE flip-flop is set, the
interrupt request is generated depending on the status of STB and IBF signals.
 If INTE flip- flop is reset, the interrupt request is not generated, allowing masking
facility for the interrupt.

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 Handshaking Signal…
 Output Buffer Full (OBF)
 This is an active low output signal for 8255 and input signal for the output device.
 The- 8255 activates this signal to indicate output device that data is available on the
output port.
 Upon activation of OBF signal out put device reads data from the output port and
acknowledges it by ACK signal.
 The OBF signal is activated at the rising edge of the WR signal and de-activated at the
falling edge of the ACK signal.
 Acknowledge Input (ACK)
 This is an active low input signal for 8255 and output signal for the output device.
 The output device generates this signal to indicate 8255 that the data from port A or
Port B has been accepted. 28
 Handshaking Signal…
 Read Operation
 STB goes low indicates that data are loads into port latch.
 IBF becomes high (at high to low transition of STB) indicates that input latch contains
data.
 INTR Becomes high (at low to high transition of STB) uP goes interrupt subroutine to
read data. RD becomes low.
 IBF becomes low when read complete, RD becomes high and IBF goes low.
 IBF low means input latch has no data (Read complete)

2
9
Handshaking Signal…

3
0
 Parallel Data Transfer
 Simple I/O
 This data transfer method is used when the I/O devices need no communication before
the data transfer. Such devices are thermostat, LED. The crossed lines on the wave
form represent the time at which a new data byte becomes valid on the output lines of
the port.

 Simple Strobe I/O

 For example, consider the keyboard. When a key is pressed, it sends out the ASCII Code
for the pressed key on eight parallel data lines, and then sends out a strobe signal (STB)
on another line to indicate that valid data is present to transmit.

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 Parallel Data Transfer…
 Single handshake Data transfer
 The sending device outputs some parallel data and sends an 𝑆𝑇𝐵 signal to the receiving
device. (i.e. sending device says receiving device, “I have some data for you” )
 As a response of 𝑆𝑇𝐵 signal receiver device reads data and send an acknowledge signal
(ACK) to indicate that the data has been read. (i.e. by acknowledge signal receiving device
says to sending device, “your sending data is received and I am ready to get new data”)

3
2
 Parallel Data Transfer…
 Double Handshake Data Transfer
 The sending device asserts its 𝑆𝑇𝐵 line low to ask the receiving device “are you ready?”
 The receiving device raises its ACK line high to say “I am ready”.
 The peripheral device then sends the byte of data and raises its 𝑆𝑇𝐵 line high to say “Here is
some valid data for you”.
 After it has read in the data, the receiving data drops its ACK line low to say “I have the
data”. The receiving device is then ready to be requested for accepting the next data byte.

3
3
 Programming 8255A
 Modes of Operation
 8255 can be configured in two modes
• BSR (Bit Set Reset) Mode
• I/O (Input-Output) Mode: Mode 0, Mode 1 and Mode 2
 Modes are configured by Control Word
 Control Word
 A Control Word is an 8-bit data that stored in control register.
 The contents of this register specify an I/O function for each port.
 This register can be accessed to write a control word when A0 and A1 are at logic 1 .
 The register is not accessible for a Read Operation.
 Control Words are two types:
I. BSR Control Word
II. Mode definition Control Word 34
 Programming 8255A…

 Modes of Operation

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 I/O Mode (Configured by Mode definition CR)
 Bit D7 of the control register specifies either the I/O function or the Bit Set/Reset function
 If bit D7 = 1, bits D6-D0 determine I/O functions in various mode.
 If bit D7 = 0, port C operates in the Bit Set/Reset (BSR) mode.

To communicate with peripherals through the 8255A, three steps are necessary.
1. Determine the addresses of ports A, B & C and of the control register according to the Chip
Select (CS) Logic and Address Lines A0 and A1.
2. Write a control word in the control register.
3. Write I/O instructions to communicate with peripherals through port A, B & C

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I/O Mode (Configured by Mode definition CR)…

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I/O Mode (Configured by Mode definition CR)…
D0 Port C lower 0 Output
1 Input
D1 Group B Port B 0 Output
1 Input
D2 Mode selection 0 Mode 0
1 Mode 1
D3 Port C upper 0 Output
1 Input
D4 Port A 0 Output
Group A 1 Input
D6, D5 Mode selection 00 Mode 0
01 Mode 1
1X Mode 2
D7 Command type 0 Bit set/reset
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1 Mode set
 BSR Mode (Configured by Bit Set-Reset Control Word)
 If bit 7 of control word is a logic 0 then 8255 will be configured as BSR (Bit Set Rest) mode.
 The BSR mode is concerned only with the eight bits of port C, which can be set or reset by
writing an appropriate control word in the control register.
 The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as shown:

BSB Mode: CWR Format

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 BSR Mode (Configured by Bit Set-Reset Control Word)
 BSR control word register format is shown below:-

N.B: Don’t Cares are Generally set as zero.

Problem:
Write a control word to reset PC5
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 I/O Mode (Configured by Mode definition CR)

• If bit 7 of the control word is a

logical 1 then the 8255 will be
configured as I/O mode.
• I/O mode consists of
• Mode0
• Mode1
• Mode2.

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 I/O Mode
 Mode 0
• Port A works as simple input or output without handshaking.
• Port B works as simple input or output without handshaking.
• Port C can be used together as an additional 8 bit port or they can be used
individually as two 4-bit ports.
• When used as outputs, the Port C lines can be individually set or reset by sending a special
control word to the control register address.

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 I/O Mode…

 Mode 1
• In this mode, handshake signals are exchanged between the CPU and peripherals prior to
data transfer.
• Port B is initialized in mode 1 for either input or output, Pins PC0, PC1 and PC2 function
as handshake lines.
• Port A can also be configured as input or output in mode 1. But handshake signal
pins are not same for input and output mode as like Port B.
• If port A is initialized in mode 1 as handshake input port, then pins PC3, PC4 and PC5
function as handshake signals. (PC6 and PC7 are available for using as input lines or output
lines)
• If port A is initialized as handshake output port, then PC3, PC6 and PC7 function as handshake
signals. (PC4 and PC5 are available for using as input or output lines)
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 I/O Mode…

 Mode 1…
Connection of Handshaking lines when Port A and Port B configured as Input in Mode 1
 I/O Mode…

 Mode 1…
 I/O Mode…
 Mode 2
This mode is used primarily in applications such as data transfer between two computers or floppy
disk controller interface.

• Only port A can be initialized in mode 2.

• In mode 2, port A can be used for “bi-directional handshake” data transfer i.e. data can be
input or output on the same eight lines.
• Pins PC3, PC4, PC5, PC6, PC7 used as handshake lines for port A.
• Port B is operating in either mode 0 or mode 1.
• If port B is in mode 0, then PC0, PC1 and PC2 used for I/O.
• If port B is in mode 1, then PC0, PC1 and PC2 used as handshake lines.
46
 I/O Mode…
Handshaking Lines in Mode 2

47
 I/O Mode…
 Mode 2 …

48
 I/O Mode…
8255A modes summarization
Handshake lines for Other Port C pins
Mode 8- Bit Port A 8-Bit Port B
mentioned Mode available for I/O
PC7- PC4 and
0 I/O I/O N/A
PC3- PC0

PC3, PC4, PC5 (Port A)

1 Input I/O PC6, PC7
PC0, PC1, PC2 (Port B)

PC3, PC6, PC7 (Port A)

1 Output I/O PC4, PC5
PC0, PC1, PC2 (Port B)
PC0, PC1, PC2 (If Port
2 Bi-Directional N/A PC3, PC4, PC5, PC6, PC7
B in Mode 0)
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 Port Addresses
 Determining the port addresses for the 8255A
 To determine the port addresses for the 8255A, you need to know the base address
allocated to the chip and how the ports are typically mapped.
 A common approach is to assign a base address, and then derive the individual port
addresses (Port A, Port B, Port C, and the Control register) by incrementing the base
address by 1 for each port.
 Port A: Base Address + 0
 Port B: Base Address + 1
 Port C: Base Address + 2
 Control Register: Base Address + 3.

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 Examples

Problem1: Write a control word to configure port A as input port in mode 0 and port B in
mode 1 as output port.
Solution: D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 1 0 0

The control word is 94H .

N.B. D0 and D3 are low if port C is used as output or if unused.

Problem 2: A control word is given CW=CDH. Explain the conditions of ports of 8255A.
Solution: D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 1 1 0 1

D7=1; I/O Mode.

D6=1 and D5=0; Port A is in Mode 2.
D4=0; Port A is output port
D3=1; Port C (Upper) is input port.
D2=1; Port B is in Mode 1.
D1=0; Port B is output Port. 51
D0=1; Port C (Lower) is input port.
 Examples

Problem 3: Write an 8086 assembly language procedure to read an ASCII character

from a keyboard via PORT A of an 8255 PPI when PORT C bit PC4 is strobed low. Assume a
base address of 20H.
Solution:
PORTA EQU 20H
PORTC EQU 22H
CONTROL EQU 23H
READ PROC NEAR
Port A
MOV AL, 98H ; 1001 1000 D0 to D7
OUT CONTROL, AL ; Initialize PORTS
READ1: 8255 Keyboard
IN AL, PORTC ; Is Strobe PC4 Low?
TEST AL, 10H ; 0001 0000
JNZ READ1 PC4
IN AL, PORTA ; Read ASCII Character 𝑆𝑇𝐵
RET
READ ENDP
22
 Examples
Problem 4: Write an assembly language instruction set to drive the DC motor interfaced with 8086 microprocessor
as shown in figure. The switches SW0 and SW1 control the motor status according to the table.

SW1 SW0 Motor status

OFF OFF No rotation
OFF ON Forward rotation
ON OFF Reverse rotation
ON ON No rotation

Solution:

D7 D6 D5 D4 D3 D2 D1 D0 Control Word

1 0 0 0 0 0 1 0 82H
 Examples
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address of Port

0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 00F8H (Port A)

0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 00F9H (Port B)

0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 00FAH (Port C)

0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 00FBH (CR)

PORTA EQU 00F8H

PORTB EQU 00F9H
CONTR EQU 00FBH
MOV AL, 82H STOP : MOV AL, 00000000B;
OUT CNTRL, AL; Control word sent to CR OUT PORTA, AL;
MAIN : IN AL, PORTB; JMP MAIN;
AND AL, 00000011B; Check switch FORWARD: MOV AL, 00000010
JPE STOP; (JPE=Jump if parity even, p=1) OUT PORTA, AL
; if two switches are on or off, parity will be even JMP MAIN
TEST AL, 00000001B; check whether SW0 is on or off
JZ FORWARD ; if SW0 is on, result becomes zero (Z=1)
MOV AL, 00000001B;
OUT PORTA, AL; motor rotate reverse direction
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JMP MAIN;
 Examples

Example 5: The 8255 shown in the Figure below is configured as follows: port A as input, B as
output, and all the bits of port C as output.
a) Find the port addresses assigned to A, B, C, and the control register.
b) Find the control byte (word) for this configuration.

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 Problems

a) The port addresses are as follows

CS A1 A0 Address Port CS A1 A0 Selects

11000100 0 0 310H Port A 0 0 0 Port A
11000100 0 1 311H Port B 0 0 1 Port B
11000100 1 0 312H Port C 0 1 0 Port C
11000100 1 1 313H Control register
0 1 1 Control Register
1 x x 8255 is not selected

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 Problems

a) The port addresses are as follows

CS A1 A0 Address Port CS A1 A0 Selects

11000100 0 0 310H Port A 0 0 0 Port A
11000100 0 1 311H Port B 0 0 1 Port B
11000100 1 0 312H Port C 0 1 0 Port C
11000100 1 1 313H Control register
0 1 1 Control Register
1 x x 8255 is not selected
b) Find the control byte (word) for this configuration.
Port A as input, B as output, and all the bits of port C as output.
Solution:
The control word is 90H, or 1001 0000.
1 0 0 1 0 0 0 0 = 90H 30
Direct memory Access (DMA)

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Direct memory Access (DMA)

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