UNIT 6 MP

80386DX Signals, Bus Cycles

and
80387 Coprocessor

2nd Year SEM 2

Department of Computer Engineering

 Topics
• 80386DX Signals- Pin Diagram of 80386 and
description.
• 80386DX Bus Cycles- System Clock, Bus States,
Pipelined and Non-pipelined Bus Cycles.

• 80387 NDP-
• CLK2: The input pin provides the basic system
clock timing for the operation of 80386.

• D0 – D31: These 32 lines act as bidirectional data

bus during different access cycles.

• A31 – A2: These are upper 30 bit of the 32- bit

address bus.

• BE0 to BE3: (Active Low) The 32- bit data bus

supported by 80386 and the memory system of
80386 can be viewed as a 4-byte wide memory
access mechanism.
 Bus Control
ADS#: (Address Data Strobe)
Active when issued a valid request.
The address status output pin indicates that the
address bus and Bus Cycle Definition Pins( W/R#,
D/C#, M/IO#, BE0# to BE3# ) are carrying the
respective valid signals.

BS16#: The bus size – 16 input pin allows the

interfacing of 16 bit devices with the 32 bit wide
80386 data bus.
• READY#: The ready signals indicates to the
CPU that the previous bus cycle has
been terminated and the bus is ready
for the next cycle. The signal is used to
insert WAIT states in a bus cycle and is
useful for interfacing of slow devices with
CPU.

• NA#: Gives address of next instruction if

pipelining is enabled. If pipelining is
not enabled, this pin is high, if instruction
is in waiting state.
 Bus Arbitration
• HOLD: The Bus hold input pin enables the
other bus masters to gain control of
the system bus if it is asserted.

• HLDA: The bus hold acknowledge output

indicates that a valid bus hold request
has been received and the bus has
been relinquished by the CPU.
 Interrupts
• INTR: This interrupt pin is a mask-able interrupt,
that can be masked using the IF of the flag
register.

• NMI: A valid request signal at the non-mask-able

interrupt request input pin internally generates a
non- mask-able interrupt of type2.

• RESET: A high at this input pin suspends the

current operation and restart the execution from
the starting location.
 Co-Processor Signaling
• BUSY#: The busy input signal indicates to the
CPU that the coprocessor is busy with the
allocated task.

• ERROR#: The error input pin indicates to the

CPU that the coprocessor has encountered an
error while executing its instruction.

• PEREQ: (Processor extension request)

Output signal indicates to the CPU
to fetch data.
 A bus cycle definition pins
• LOCK#: BUS LOCK is a bus cycle definition pin
that indicates that system have locked
system bus of other peripherals.

• W/R#: WRITE/READ is a bus cycle definition

pin that distinguishes write cycles from
read cycles.
• D/C#: DATA/CONTROL is a bus cycle definition
pin that distinguishes data cycles,
either memory or I/O, from control cycles
which are: interrupt acknowledge, halt, and
instruction fetching.

• M/IO#: MEMORY I/O is a bus cycle definition

pin that distinguishes memory cycles
from input/output cycles.
 Power Connection Pins

• VCC: These are system power supply lines.

• GND:
System Clock
Non-pipelined read & write cycles (No
wait states)
Non-pipelined read & write cycles
(With wait states)
Bus States (Using non-pipelined
address)
• T1: First clock of a non-pipelined bus cycle (Intel386
DX drives new address and asserts ADS#)

• T2: subsequent clocks of a bus cycle when NA# has

not been sampled asserted in the current bus cycle

• Ti: idle state

• Th: Hold acknowledge state (Intel386 DX

asserts HLDA)

• The fastest bus cycle consists of two states: T1

and T2.
Asserting BS16#: No wait states
Asserting BS16#: Wait states
Transitioning to pipelined address
Fast Transitioning to pipelined address
 80387: NDP
• Control Register bits for Coprocessor support

• 80387 Register Stack

• Data Types

• Load and Store Instructions

• Trigonometric and Transcendental Instructions

• Interfacing signals of 80386DX with 80387.

 Features: 80387
• High performance 80-Bit Internal Architecture.

• Implements IEEE standard 754-1985 for Binary

floating-point arithmetic.

• Expands Intel386DX CPU data types to include 32-, 64-,80-bit

floating point, 32-, 64-bit integers and 18-bit BCD operands.

• Extends Intel386DX CPU instruction set to include and

Trigonometric, Logarithmic, Exponential
Arithmetic instructions for all data types.
• Support transcendental operations for SINE,
COSINE, TANGENT, ARCTANGENT and LOGARITHM.

• Built-in Exception handling.

• Operates independently in all modes of 80386.

• Eight 80-bit Numeric registers.

• Available in 68-pin PGA package.

• One version supports 16MHz-33MHz.

Register use of 8087
 Register Set
• Data registers: Eight 80-bit registers.

• Tag Word: The tag word marks the content of

each numeric data register, two bits for
each data register.

• Status word: The 16-bit status word reflects

the overall state of the MCP
(Math Coprocessor).
• Instruction and Data pointers: Two pointer
registers allows identification of the
failing numeric instruction which supply
the address of failing numeric instruction
and the address of its numeric memory
operand.

• Control Word: Several processing options are

selected by loading a control word
from memory into the control register.
MCP Status Word
Control register bits for coprocessor
support
 Control register bits …
• The low-order byte of this control word
configures the MCP error and exception masking.

--------------- X X PM UM OM ZM DM IM
15 - - - - - - - - - - - - - 7 6 5 4 3 2 1 0

5 – Precision mask
4 – Underflow mask
3 – Overflow mask
2 – Zero Divide
mask
1 – Denormalized operand mask
0 – Invalid operation mask
 Control register bits …
• The high-order byte configures operating mode of
MCP, including precision and rounding
------------------ RC PC --------------------
15 - - - - - - - - - - - - - 12 11 10 9 8 7-------------------0

Precision Control (Bits 9,8) Rounding Control (Bits 11, 10)

00 – 24 bits (single precision) 00 – Round to nearest or even
01 – Reserved 01 – Round down (toward -∞)
10 – 53 bits (double precision)
10 – Round up (toward +∞)
11 – 64 bits (extended precision)
11 – Chop (Truncate toward
zero)

• 6 bits are reserved (Bits 6, 7, 12, 13, 14 & 15)

80387 Register Stack
Data Types
 Instruction Set
• Data transfer instructions
• Non-transcendental instructions
• Comparison instructions
• Transcendental instructions
• Constant instructions
• Processor Control instructions
Data transfer instructions
 Non-transcendental instructions
Operation Instructions

Addition FADD, FADDP, FIADD

Subtraction FSUB, FSUBP, FISUB, FSUBR (Reverse Subtract),

FSUBRP, FISUBR
Multiplication FMUL, FMULP, FIMUL

Division FDIV, FDIVP, FIDIV, FDIVR (Reverse Division),

FDIVRP, FIDIVR
Other FSQRT, FSCALE, FPREM (Partial Reminder),
operations FPREM1, FRNDINT (Round to Integer), FXTRACT
(Extract Exponent and Mantissa), FABS (Absolute
Value), FCHS (Change Sign)
Comparison Instructions
Transcendental instructions
Constant Instructions
Processor Control Instructions
 Interfacing Signals of 80386DX with
80386 80387 80387
Pin Pin
M/IO# NPS1#
A31 NPS2
A2 CMD0#
W/R# W/R#
ADS# ADS#
D31-D0 D31-D0
BUSY# BUSY#
ERROR# ERROR#
PEREQ PEREQ
80387 Pin Description