Field-Effect Transistors

Introduction

The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to
a large extent, those of the BJT transistor. JFET transistor is a voltage-controlled device. For the FET the
current ID will be a function of the voltage VGS applied to the input circuit. The FET is a unipolar device
depending solely on either electron (n- channel) or hole ( p- channel) conduction.

The term field effect in the name deserves some explanation. We are all familiar with the ability of a
permanent magnet to draw metal filings to itself without the need for actual contact. The magnetic field of
the permanent magnet envelopes the filings and attract them to the magnet along the shortest path
provided by the magnetic flux lines. For the FET an electric field is established by the charges present,
which controls the conduction path of the output circuit without the need for direct contact between the
controlling and controlled quantities.

FIG 1
voltage-controlled amplifiers.

Comparison of some of the general characteristics of BJT with FET:

One of the most important characteristics of the FET is its high input impedance.
The variation in output current is typically a great deal more for BJTs than for FETs for the same change
in the applied voltage.

FETs are more temperature stable than BJTs, and FETs are usually smaller than BJTs, making them
particularly useful in integrated-circuit (IC) chips.
The construction characteristics of some FETs, however, can make them more sensitive to handling than
BJTs.

Type of FET:

Three types of FETs : the junction field-effect transistor (JFET), the metal–oxide–semiconductor field-
effect transistor (MOSFET), and the metal– semiconductor field-effect transistor (MESFET). The
MOSFET category is further broken down into depletion and enhancement types. The MOSFET
transistor has become one of the most important devices used in the design and construction of integrated
circuits for digital computers. Its thermal stability and other general characteristics make it extremely
popular in computer circuit design.

Construction and Characteristics of JFETs

JFET is a three-terminal device with one terminal capable of controlling the current between the other
two. The major part of the structure is the n-type material, which forms the channel between the
embedded layers of p-type material. In the absence of any applied potentials the
JFET has two p–n junctions under no-bias conditions. The result is a depletion region at each junction, as
shown in Fig. 2 that resembles the same region of a diode under no-bias conditions.

FIG 2
Junction field-effect transistor (JFET).

VG = 0 V, VDS Some Positive Value

A positive voltage VDS is applied across the channel and the gate is connected directly to the source to
establish the condition VGS =0 V .Under the conditions the flow of charge is relatively uninhibited and is
limited solely by the resistance of the n-channel between drain and source.
The depletion region is wider near the top of both type materials. The current I D will establish the voltage
levels through the channel as indicated on the figure. The result is that the upper region of the p-type
material will be reverse-biased by about.

As the voltage VDS is increased from 0 V to a few volts, the current will increase as determined by Ohm’s
law and the plot of ID versus VDS. As VDS increases and approaches a level referred to as VP, the depletion
regions will widen, causing a noticeable reduction in the channel width. The reduced path of conduction
causes the resistance to increase. The more horizontal the curve, the higher the resistance, suggesting that
the resistance is approaching “infinite” ohms in the horizontal region. If V DS is increased to a level where
it appears that the two depletion regions would touch” , a condition referred to as pinch-off will result.
As VDS is increased beyond VP, the region of close encounter between the two depletion regions increases
in length long the channel, but the level of ID remains essentially the same. In essence, therefore, once VDS
7 VP the JFET has the characteristics of a current source. As shown in Fig.5, the current is fixed at I D =
IDSS, but the voltage VDS (for levels 7 VP) is determined by the applied load.
The choice of notation IDSS is derived from the fact that it is the drain-to-source current with a short circuit
connection from gate to source. IDSS is the maximum drain current for a JFET and is defined by the
conditions VGS =0 V and
VDS>| VP |.
VGS < 0 V
The voltage from gate to source, denoted VGS, is the controlling voltage of the JFET. Curves of
ID versus VDS for various levels of VGS can be developed for the JFET. For the n-channel device the
controlling voltage VGS is made more and more negative from its VGS = 0 V level.

The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with
VGS 0 V, but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach
the saturation level at a lower level of VDS, as shown in Fig.6 for VGS = - 1 V. The resulting saturation level
for ID has been reduced and in fact will continue to decrease as VGS is made more and more negative.
Eventually, VGS when VGS = -VP will be sufficiently negative to establish a saturation level that is
essentially 0 mA, and for all practical purposes the device has been “turned off.” In summary:
The level of VGS that results in ID= 0 mA is defined by VGS =VP, with VP being a negative voltage for n-
channel devices and a positive voltage for p-channel JFETs.
 FIG. 6

Application of a negative voltage to the gate of a JFET

Channel JFET characteristics with IDSS = 8 mA and VP = -4 V.

Transfer Characteristics
Derivation
For the BJT transistor the output current and the input controlling current are related by beta,
which was considered constant for the analysis to be performed. In equation form

IC = f (IB) = βIB -(1)

The squared term in the equation results in a nonlinear relationship between ID and VGS,
producing a curve that grows exponentially with decreasing magnitude of VGS.

(
I D =I DSS 1−
VP )
V GS
-(2)

The squared term in the equation results in a nonlinear relationship between ID and VGS,
producing a curve that grows exponentially with decreasing magnitude of VGS.
The transfer characteristics defined by Shockley’s equation are unaffected by the network in
which the device is employed
 FIG. 7

Obtaining the transfer curve from the drain characteristics.

Depletion-Type MOSFET

MOSFETs are further broken down into depletion type and enhancement type. The terms depletion and
enhancement define their basic mode of operation; the name MOSFET stands for metal–oxide–
semiconductor field-effect transistor

Basic Construction:
The basic construction of the n-channel depletion-type MOSFET is provided in Fig. 8. A slab of p-type
material is formed from a silicon base and is referred to as the substrate. It is the foundation on which the
device is constructed. In some cases the substrate is internally connected to the source terminal. The gate
is also connected to a metal contact surface but remains insulated from the n-channel by a very thin
silicon dioxide (SiO2) layer. SiO2 is a type of insulator referred to as a dielectric, which sets up opposing
(as indicated by the prefix di-) electric fields within the dielectric when exposed to an externally applied
field.

Basic Operation:
The gate-to-source voltage is set to 0 V by the direct connection from one terminal to the other, and a
voltage VDD is applied across the drain-to-source terminals. The result is an attraction of the free electrons
of the n-channel for the positive voltage at the drain. The result is a current similar to that flowing in the
channel of the JFET. In fact, the resulting current with VGS 0 V continues to be labeled IDSS.
VGS is set at a negative voltage such as -1 V. The negative potential at the gate will tend to pressure
electrons toward the p-type substrate (like charges repel) and attract holes from the p-type substrate
(opposite charges attract).

Depending on the magnitude of the negative bias established by VGS, a level of recombination between
electrons and holes will occur that will reduce the number of free electrons in the n-channel available for
conduction. The more negative the bias, the higher is the rate of recombination. The resulting level of
drain current is therefore reduced with increasing negative bias for V GS.
 FIG. 8

Enhancement-Type MOSFET

The characteristics of the enhancement-type MOSFET are quite different from depletion type MOSFET.

Basic Construction:
A slab of p-type material is formed from a silicon base and is again referred to as the substrate. As with
the depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal,
whereas in other cases a fourth lead (labeled SS) is made available for external control of its potential
level. The source and drain terminals are again connected through metallic contacts to n-doped regions,
but note in Fig. the absence of a channel between the two n-doped regions. This is the primary difference
between the construction of depletion-type and enhancement-type MOSFETs—the absence of a channel
as a constructed component of the device. In summary, therefore, the construction of an enhancement-
type MOSFET is quite similar to that of the depletion-type MOSFET, except for the absence of
a channel between the drain and source terminals.

Basic Operation:
If VGS is set at 0 V and a voltage applied between the drain and the source of the device of Fig. 9 the
absence of an n-channel (with its generous number of free carriers) will result in a current of effectively 0
A—quite different from the depletion-type MOSFET and JFET, where ID = IDSS. It is not sufficient to
have a large accumulation of carriers (electrons) at the drain and the source (due to the n-doped regions)
if a path fails to exist between the two. With VDS some positive voltage, VGS at 0 V, and terminal SS
directly connected to the source, there are in fact two reverse-biased p–n junctions between the n-doped
regions and the p-substrate to oppose any significant flow between drain and source.
The level of VGS that results in the significant increase in drain current is called the threshold voltage and
is given the symbol VT. On specification sheets it is referred to as V GS(Th), although VT is less unwieldy
and will be used in the analysis to follow. Since the channel is nonexistent with V GS 0 V and “enhanced”
by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-
type MOSFET.

FIG 9

FET Biasing

For the field-effect transistor, the relationship between input and output quantities is nonlinear due to the
squared term in Shockley’s equation. Linear relationships result in straight lines when plotted on a graph
of one variable versus the other, whereas nonlinear functions result in curves as obtained for the transfer
characteristics of a JFET. The nonlinear relationship between I D and VGS can complicate the mathematical
approach to the dc analysis of FET configurations. A graphical approach may limit solutions to tenths-
place accuracy, but it is a quicker method for most FET amplifiers. Since the graphical approach is in
general the most popular, the analysis of this book will have graphical solutions rather than mathematical
solutions.

Fixed Bias Configuration:

The simplest of biasing arrangements for the n-channel JFET appears in Fig.10. Referred to as the fixed-
bias configuration,
 FIG 10
Fixed-bias configuration.

For the dc analysis, VRG = IG RG = (0 A)RG = 0 V, IG = 0 A

The fact that the negative terminal of the battery is connected directly to the defined positive potential of
VGS clearly reveals that the polarity of VGS is directly opposite to that of VGG. Applying Kirchhoff’s voltage
law in the clockwise direction results in

- VGG - VGS = 0
VGS = -VGG
Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the designation
“fixed-bias configuration.”

The drain-to-source voltage of the output section can be determined by applying

Kirchhoff’s voltage law as follows:

VDS = VDD - IDRD

= VDS + = VDS + 0 V,
VD =VDSVG =VGS

Self-Bias Configuration:
The self-bias configuration eliminates the need for two dc supplies. The controlling gate-to-source
voltage is now determined by the voltage across a resistor RS introduced in the source leg of the
configuration.
For the dc analysis, the capacitors can again be replaced by “open circuits” and the resistor RG replaced
by a short-circuit equivalent since

IG = 0 A.
The current through RS is the source current IS,
but IS = ID and VRS = IDRS
VGS = –IDRS

that VGS is a function of the output current ID and not fixed in magnitude as occurred for the fixed-bias
configuration.

Voltage-Divider Biasing
The basic construction is exactly the same, but the dc analysis of each is quite different. IG = 0 A for FET
amplifiers, but the magnitude of IB for common-emitter BJT amplifiers can affect the dc levels of current
and volt- age in both the input and output circuits. Recall that IB provides the link between input and
output circuits for the BJT voltage-divider configuration, whereas VGS does the same for the FET
configuration.

Since IG = 0 A, Kirchhoff’s current law requires that IR1 = IR2, and the series equivalent circuit appearing
to the left of the figure can be used to find the level of VG. The voltage VG, equal to the voltage across R2,
can be found using the voltage-divider rule as follows:

R 1 V DD
V G=
R1 + R2

Applying Kirchhoff’s voltage law

V GS=V G−I D R S