Module – 2

(Online Teaching)

Introduction To
Analog Electronic Circuits

By
Venkata Sridhar .T M.Tech,PhD*,MIETE

Assistant Professor of ETC.

IIIT-Bhubaneswar.
 Module – 2

Biasing of FETs and MOSFETs: Principle and Physical

Operation of FETs and MOSFETs. Fixed Bias Configuration and
Self Bias Configuration, Voltage Divider Bias and Design

Small Signal Analysis of FETs: Small-Signal Equivalent-Circuit

Model, Small Signal Analysis of CS, CD, CG Amplifier with and
without RS. Effect of RSIG and RL on CS Amplifier, Analysis of
Source Follower and Cascaded System using FETs.

2
By T.VenkataSridhar , ETC
 Field Effect Transistors (FET)

3
By T.VenkataSridhar , ETC
 brief…
The field-effect transistor (FET) is a three-terminal device used for a variety of
applications that match, to a large extent, those of the BJT transistor.

Although there are important differences between the two types of devices, there
are also many similarities.
The primary difference between the two types of transistors is the fact that:
The BJT transistor is a current-controlled device as depicted in Fig. 1a, whereas
the JFET transistor is a voltage-controlled device as shown in Fig. 1b.
In other words, the current IC in Fig. 1a is a direct function of the level of IB. For the
FET the current ID will be a function of the voltage VGS applied to the input circuit as
shown in Fig. 1b. In each case the current of the output circuit is controlled by a parameter
of the input circuit—in one case a current level and in the other an applied voltage.

4
By T.VenkataSridhar , ETC
 brief…conti..
Just as there are npn and pnp bipolar transistors, there are n-channel and
p-channel fieldeffect transistors.

However, it is important to keep in mind that the BJT transistor is a bipolar

device—the prefix bi indicates that the conduction level is a function of two
charge carriers, electrons and holes.

The FET is a unipolar device depending solely on either electron

(n-channel) or hole (p-channel) conduction.

For the FET an electric field is established by the charges present, which
controls the conduction path of the output circuit without the need for direct
contact between the controlling and controlled quantities.
❖ One of the most important characteristics of the FET is its high input impedance.
❖ Typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. but
❖ FETs are more temperature stable than BJTs, and FETs are usually smaller than
BJTs, making them particularly useful in integrated-circuit (IC) chips.

5 By T.VenkataSridhar , ETC
FET Types
FETs are available in many types and combinations, few of them are.
N-Channel JFET
JFET P-Channel JFET
PMOS(p-channel)
Enhancement MOSFET
MOSFET NMOS(n-channel)
PMOS(p-channel)
Depletion MOSFET
NMOS(n-channel)
MESFET

CMOS

BiCMOS

VMOS

UMOS
6
By T.VenkataSridhar , ETC
FET Types contd..

Figure 2: JFET symbols: Figure 3: JFET looks in the market

(a) n-channel; (b) p-channel.

7 Figure 4: JFET vs BJT

By T.VenkataSridhar , ETC
FET Types contd..

Figure 6:
Depl. MOFET looks
in the market

Figure 5: symbols for:

(a) n-channel depletion-type MOSFETs and
(b) p-channel depletion-type MOSFETs.

Figure 7: Symbols for:

(a) n-channel
enhancement-type
MOSFETs and
(b) p-channel
enhancement type
MOSFETs.
8
By T.VenkataSridhar , ETC
Construction and Operation of JFETs
JFET is a three-terminal device with one terminal capable of controlling the
current between the other two.
For the JFET transistor the n-channel device will be the prominent device, over a
p-channel JFET.
The basic construction of the n-channel JFET is shown in Fig. 8. Note that
the major part of the structure is the n-type material, which forms the channel
between the embedded layers of p-type material.

The top of the n-type channel is

connected through an ohmic contact to a
terminal referred to as the drain (D),
whereas the lower end of the same
material is connected through an ohmic
contact to a terminal referred to as the
source (S). The two p-type materials are
connected together and to the gate (G)
Figure 8: terminal.
9 Junction field-effect transistor (JFET). By T.VenkataSridhar , ETC
 In Fig. 10, a positive voltage VDS is applied
across the channel and the gate is connected
directly to the source to establish the condition
VGS = 0 V. The result is a gate and a source
terminal at the same potential and a depletion
region in the low end of each p-material similar
Figure 9: Water analogy for the to the distribution of the no-bias conditions of
JFET control mechanism. Fig. 8.

Figure 11: Varying reverse-bias potentials

across the p–n junction of an n-channel
JFET.
10 Figure 10: JFET at VGS = 0 V and VDS > 0 V. By T.VenkataSridhar , ETC
 As the voltage VDS is increased from 0 V to a few volts, the current will
increase as determined by Ohm’s law and the plot of ID versus VDS will appear as
shown in Fig. 12.
The relative straightness of the plot reveals that for the region of low values of
VDS, the resistance is essentially constant. As VDS increases and approaches a level
referred to as VP (Pinch-off) in Fig. 12 and13.

Figure 13: Pinch-off (VGS = 0 V, VDS = VP).

Figure 12: ID versus VDS for VGS = 0 V.
11 By T.VenkataSridhar , ETC
 The voltage from gate to source, denoted VGS, is the controlling voltage of the
JFET. For the n-channel device the controlling voltage VGS is made more and
more negative from its VGS = 0 V level. In other words, the gate terminal will be
set at lower and lower potential levels as compared to the source.

Figure 15: n-Channel JFET characteristics with

12 Figure 14: Application of a negative IDSS = 8 mA and VP = -4 V
voltage to the gate of a JFET. By T.VenkataSridhar , ETC
 The region to the left of the pinch-off locus of Fig. 15 is referred to as the
ohmic or voltage-controlled resistance region. In this region the JFET can
actually be employed as a variable resistor (possibly for an automatic gain control
system) whose resistance is controlled by the applied gate-to-source voltage.

The p-channel JFET is

constructed in exactly the
same manner as the
n-channel device of Fig. 8,
but with a reversal of the p-
and n-type materials as
shown in Fig. 16.
13
Figure 16: p-Channel JFET. By T.VenkataSridhar , ETC
 Figure 17: p-Channel JFET
characteristics with IDSS = 6 mA
and VP = +6 V.

(Rep.)Figure 2: JFET symbols:

(a) n-channel; (b) p-channel.
14 By T.VenkataSridhar , ETC
 Figure 18: n-Channel JFET’s

15 By T.VenkataSridhar , ETC
16 By T.VenkataSridhar , ETC
 Figure 19: Obtaining the transfer curve from the drain characteristics.

17 By T.VenkataSridhar , ETC
 The validity of Eq. (3) as a source of the transfer curve is best demonstrated by
examining a few specific levels of one variable and finding the resulting level of the
other as follows:

18
 Conversely, by using basic algebra we can obtain [from Eq. (3)] an equation for the
resulting level of VGS for a given level of ID. The derivation is quite straightforward and
results in

19 By T.VenkataSridhar , ETC
20 By T.VenkataSridhar , ETC
 Figure 20: Normal operating
region for linear amplifier
design.

21
Construction and Operation of MOSFETs

MOSFETs are further broken down

into depletion type and enhancement type.
The terms depletion and enhancement
define their basic mode of operation; the
depletion type have a connecting layer
between the drain and source which is
called a channel is done in manufacturing
where as in enhancement type it should be
formed by the user. The name MOSFET
stands for metal–oxide–semiconductor
field-effect transistor.

Figure 21: n-Channel depletion-type MOSFET.

22
 In Fig. 22 the gate-to-source
voltage is set to 0 V by the direct
connection from one terminal to
the other, and a voltage VDD is
applied across the drain-to-source
terminals. The result is an
attraction of the free electrons of
the n-channel for the positive
voltage at the drain. The result is a
current similar to that flowing in
the channel of the JFET. In fact,
the resulting current with VGS= 0V
continues to be labelled IDSS, as
shown in Fig. 23.

Figure 22: n-Channel depletion-type MOSFET with

VGS = 0 V and applied voltage VDD.
23 By T.VenkataSridhar , ETC
 Figure 23: Drain and transfer characteristics for an n-channel depletion-type MOSFET.

In Fig. 24, VGS is set at a negative voltage such as -1 V. The negative potential at the gate will
tend to pressure electrons toward the p-type substrate (like charges repel) and attract holes
from the p-type substrate (opposite charges attract) as shown in Fig. 24. Depending on the
magnitude of the negative bias established by VGS, a level of recombination between
electrons and holes will occur that will reduce the number of free electrons in the n-channel
available for conduction.
24 By T.VenkataSridhar , ETC
 Figure 24: Reduction in free
carriers in a channel due to
a negative potential at the gate
terminal.

The construction of a p-channel depletion-type MOSFET is exactly the reverse of that

appearing in Fig. 24. That is, there is now an n-type substrate and a p-type channel, as
shown in Fig. 25a. The terminals remain as identified, but all the voltage polarities and the
current directions are reversed, as shown in the same figure. Transfer characteristics as
25 shown in Fig. 25b and c. By T.VenkataSridhar , ETC
 Figure 25: (a) p-Channel depletion-type MOSFET with (b & c) IDSS = 6 mA and VP = +6 V.

26
By T.VenkataSridhar , ETC
Basics
Although there are some similarities in construction and mode of operation between
depletion type and enhancement-type MOSFETs, the characteristics of the
enhancement-type MOSFET are quite different from anything obtained thus far. The
transfer curve is not defined by Shockley’s equation, and the drain current is now cut off
until the gate-to source voltage reaches a specific magnitude. In particular, current control
in an n-channel device is now effected by a positive gate-to-source voltage rather than the
range of negative voltages encountered for n-channel JFETs and n-channel depletion-type
MOSFETs.
The basic construction of the n-channel
enhancement-type MOSFET is provided in Fig.26.
A slab of p-type material is formed from a silicon
base and is again referred to as the substrate. As
with the depletion-type MOSFET, the substrate is
sometimes internally connected to the source
terminal, whereas in other cases a fourth lead
(labelled SS) is made available for external control
of its potential level. The source and drain
terminals are again connected through metallic
contacts to n-doped regions, but note in Fig.26 the
absence of a channel between the two n-doped
27 regions.
Figure 26: n-Channel enhancement-type MOSFET. By T.VenkataSridhar , ETC
 If VGS is set at 0 V and a voltage applied between the drain and the source of
the device of Fig. 32, the absence of an n-channel (with its generous number of
free carriers) will result in a current of effectively 0 A quite different from the
depletion-type MOSFET and JFET, where ID = IDSS. It is not sufficient to have a
large accumulation of
carriers (electrons) at the
drain and the source (due to
the n-doped regions) if a
path fails to exist between
the two. With VDS some
positive voltage, VGS at 0 V,
and terminal SS directly
connected to the source,
there are in fact two
reverse-biased p–n
junctions between the
n-doped regions and the
p-substrate to oppose any
significant flow between
Figure 27: Channel formation in the n-channel enhancement-type MOSFET.
drain and source.
28
 Since the channel is nonexistent with VGS = 0 V and “enhanced” by the
application of a positive gate-to-source voltage, this type of MOSFET is called an
enhancement-type MOSFET.

The level of VGS that results in the significant increase in drain current is called
the threshold voltage and is given the symbol VT or VTh. On specification sheets it
is referred to as VGS(Th).

As VGS is increased beyond the threshold level, the density of free carriers in the
induced channel will increase, resulting in an increased level of drain current.

Applying Kirchhoff’s voltage law to the terminal voltages of the MOSFET of

Fig. 28, we find that

29 By T.VenkataSridhar , ETC
Figure 28: Change in channel and
depletion region with increasing
level of VDS for a fixed value of VGS.

30 By T.VenkataSridhar , ETC
 Figure 29: Sketching the transfer characteristics for an n-channel enhancement-type
MOSFET from the drain characteristics.
31 By T.VenkataSridhar , ETC
 The construction of a p-channel enhancement-type MOSFET is exactly the
reverse of that appearing in Fig. 26, as shown in Fig. 30a. And the characteristics
are in 30b. and c.

Figure 30:

32 By T.VenkataSridhar , ETC
 Figure 31: Symbols for: (a) n-channel enhancement-type MOSFETs and (b) p-channel
enhancement type MOSFETs.

TBS
33 By T.VenkataSridhar , ETC
 CMOS

MESFET

34
By T.VenkataSridhar , ETC
 End of FETs
(As per syllabus)

? (Any doubts)

35
By T.VenkataSridhar , ETC
 FETs –
Biasing
(DC Analysis)

36
By T.VenkataSridhar , ETC
 For the field-effect transistor, the relationship between input and output quantities
is nonlinear due to the squared term in Shockley’s equation. Linear relationships
result in straight lines when plotted on a graph of one variable versus the other,
whereas nonlinear functions result in curves as obtained for the transfer
characteristics of a JFET.

37 By T.VenkataSridhar , ETC
Fixed-Bias Configuration
The simplest of biasing
arrangements for the
n-channel JFET appears in
Fig. 1. Referred to as the
fixed-bias configuration, it is
one of the few FET
configurations that can be
solved just as directly using
either a mathematical or a
graphical approach.
The configuration of Fig. 1
includes the ac levels Vi and
Vo and the coupling
capacitors (C1 and C2).
Follow DC analysis steps that
learned earlier in BJT.

38 By T.VenkataSridhar , ETC
Fixed-Bias Configuration Continued…
For the dc analysis,

Input loop

The zero-volt drop across RG permits replacing RG

by a short-circuit equivalent, as appearing in the
network of Fig. 2, specifically redrawn for the dc
analysis.
Applying Kirchhoff’s voltage law in the clockwise
direction of the indicated loop of Fig. 2 results in

Since VGG is a fixed dc supply, the voltage VGS is

fixed in magnitude, resulting in the designation
“fixed-bias configuration.”
39 By T.VenkataSridhar , ETC
Output loop Fixed-Bias Configuration Continued…

40 By T.VenkataSridhar , ETC
 Fixed-Bias Configuration Continued…

The drain-to-source voltage of the output

section can be determined by applying
Kirchhoff’s voltage law as follows:

Recall that single-subscript voltages refer to

the voltage at a point with respect to ground.
For the configuration of Fig. 2,

Using double-subscript notation, we have

By T.VenkataSridhar , ETC
41
 Fixed-Bias Configuration Continued…

42 By T.VenkataSridhar , ETC
43 By T.VenkataSridhar , ETC
 The results clearly confirm the
fact that the mathematical and
graphical approaches generate
solutions that are quite close.

44 By T.VenkataSridhar , ETC
Self-Bias Configuration

45 By T.VenkataSridhar , ETC
Input loop Self-Bias Configuration Continued…

Note in this case that VGS is a function of the output

current ID and not fixed in magnitude as occurred for the
fixed-bias configuration.
Output loop

46 By T.VenkataSridhar , ETC
Self-Bias Configuration Continued…

47 By T.VenkataSridhar , ETC
 Self-Bias Configuration Continued…
Suppose, for example, that we choose a
level of ID equal to one-half the saturation
level. That is,

The result is a second point for the

straight-line plot as shown in Fig. 11. The
straight line as defined by Eq. (10) is then
drawn and the quiescent point obtained at the
intersection of the straight-line plot and the
device characteristic curve. The quiescent
values of ID and VGS can then be determined
and used to find the other quantities of interest.

48 By T.VenkataSridhar , ETC
 Self-Bias Configuration Continued…

Mathematical approach

49 By T.VenkataSridhar , ETC
Voltage Divider-Bias Configuration
The basic construction in Figure 12 is exactly the same like earlier, but the dc analysis
of each is quite different. IG = 0 A for FET amplifiers, but the magnitude of IB for
common-emitter BJT amplifiers can affect the dc levels of current and voltage in both the
input and output circuits. Recall that IB provides the link between input and output circuits
for the BJT voltage-divider configuration, whereas VGS does the same for the FET
configuration.
The network of Fig. 12 is
redrawn as shown in Fig. 13 for
the dc analysis. Note that all the
capacitors, including the bypass
capacitor CS, have been replaced
by an “open-circuit” equivalent in
Fig. 13b.

In addition, the source VDD

was separated into two equivalent
sources to permit a further
separation of the input and output
regions of the network.

50 Figure 12: Voltage-divider bias arrangement.

By T.VenkataSridhar , ETC
 Voltage divider-Bias Configuration Continued…

Since IG = 0 A, Kirchhoff’s current law

requires that IR1 = IR2, and the series
equivalent circuit appearing to the left of the
figure can be used to find the level of VG.
The voltage VG, equal to the voltage across
R2, can be found using the voltage-divider
rule and Fig. 13a as follows:

Applying Kirchhoff’s voltage law in the

clockwise direction to the indicated loop
of Fig. 13 results in
Figure 13: Redrawn network of Fig.12 for dc analysis.

51 By T.VenkataSridhar , ETC
Voltage divider-Bias Configuration Continued…

Figure 14: Sketching the

network equation for the
voltage-divider configuration.

By substituting ID = 0 mA into Eq. (16) and finding the resulting value of VGS as follows:

52 By T.VenkataSridhar , ETC
 Voltage divider-Bias Configuration Continued…

Since the intersection on the

vertical axis is determined by
ID= VG/RS and VG is fixed by the
input network, increasing values
of RS will reduce the level of the Figure 15: Effect of RS on
ID intersection as shown in the resulting Q-point.
Fig.15
53 By T.VenkataSridhar , ETC
Voltage divider-Bias Configuration Continued…

54 By T.VenkataSridhar , ETC
 Figure 16: Example 2.

55 By T.VenkataSridhar , ETC
Figure 17: Determining the Q-point for the network of Fig. 16.

56 By T.VenkataSridhar , ETC
57 By T.VenkataSridhar , ETC
58
 By T.VenkataSridhar , ETC
59
 The examples to follow have a design or synthesis
orientation in that specific levels are provided and network
parameters such as RD, RS, VDD, and so on, must be
determined. In any case, the approach is in many ways the
opposite of that described in previous sections.

In some cases, it is just a matter of applying Ohm’s law in

its appropriate form. In particular, if resistive levels are
requested, the result is often obtained simply by applying
Ohm’s law in the following form:
Figure18: Self-bias
configuration to be designed.

Try to solve as many tutorials/problems as possible.

60 By T.VenkataSridhar , ETC
 End of FETs
DC Analysis
(As per syllabus)

? (Any doubts)

61
By T.VenkataSridhar , ETC
 FETs
AC Analysis

62 By T.VenkataSridhar , ETC
 INTRODUCTION
Field-effect transistor amplifiers provide an excellent voltage gain with the added
feature of a high input impedance.
They are also low-power-consumption configurations with good frequency range
and minimal size and weight.
JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers
having similar voltage gains. The depletion MOSFET (MESFET) circuit, however,
has a much higher input impedance than a similar JFET configuration.
Whereas a BJT device controls a large output (collector) current by means of a
relatively small input (base) current, the FET device controls an output (drain)
current by means of a small input (gate-voltage) voltage.
In general, therefore, the BJT is a current-controlled device and the FET is a
voltage-controlled device.

In both cases, however, note that the output current is the controlled variable.
Because of the high input characteristic of FETs, the ac equivalent model is
somewhat simpler than that employed for BJTs. Whereas the BJT has an
amplification factor, β (beta), the FET has a ‘transconductance’ factor, gm.
63 By T.VenkataSridhar , ETC
 The FET can be used as a linear amplifier or as a digital device in logic
circuits.

In fact, the enhancement MOSFET is quite popular in digital circuitry,

especially in CMOS circuits that require very low power consumption.

FET devices are also widely used in high-frequency applications and in

buffering (interfacing) applications.

Although the common-source configuration is the most popular one, providing

an inverted, amplified signal.

One also finds common-drain (source-follower) circuits providing unity gain

with no inversion and common-gate circuits providing gain with no inversion.

The ac analysis of a JFET configuration requires that a small-signal ac model for

the JFET be developed. A major component of the ac model will reflect the fact
that an ac voltage applied to the input gate-to-source terminals will control the
level of current from drain to source.
64 By T.VenkataSridhar , ETC
65 By T.VenkataSridhar , ETC
 Following the curvature of the transfer
characteristics, it is reasonably clear that the slope
and, therefore, gm increase as we progress from
VP to IDSS. In other words, as VGS approaches 0
V, the magnitude of gm increases.

Equation (2) reveals that gm can be

determined at any Q-point on the transfer
characteristics by simply choosing a finite
increment in VGS (or in ID) about the Q-point
and then finding the corresponding change in ID
(or VGS, respectively). The resulting changes in
each quantity are then substituted in Eq. (2) to
determine gm.

66 By T.VenkataSridhar , ETC
67 By T.VenkataSridhar , ETC
68 By T.VenkataSridhar , ETC
69 By T.VenkataSridhar , ETC
70 By T.VenkataSridhar , ETC
71 By T.VenkataSridhar , ETC
72 By T.VenkataSridhar , ETC
73 By T.VenkataSridhar , ETC
 The control of Id by Vgs is included as a current source gmVgs connected from drain to
source as shown in Fig. 4. The current source has its arrow pointing from drain to source
to establish a 180° phase shift between output and input voltages as will occur in actual
operation. The model for the JFET transistor in the ac domain can be constructed as
below Fig. 4.

The input impedance is represented by the open circuit at the input terminals and the
output impedance by the resistor rd from drain to source. Note that the gate-to-source
voltage is now represented by Vgs (lowercase subscripts) to distinguish it from dc
levels. In addition, note that the source is common to both input and output circuits,
whereas the gate and drain terminals are only in “touch” through the controlled current
source gmVgs.
74 By T.VenkataSridhar , ETC
75 By T.VenkataSridhar , ETC
 (TBS)

The fixed-bias configuration of

Fig. 6. includes the coupling
capacitors C1 and C2, which isolate
the dc biasing arrangement from the
applied signal and load; they act as
short circuit equivalents for the ac
analysis.

Once the levels of gm and rd are

determined from the dc biasing
arrangement, specification sheet, or
characteristics, the ac equivalent
model can be substituted between the
appropriate terminals as shown in
Fig. 7. (assuming applied all ac
76
analysis steps)
By T.VenkataSridhar , ETC
77 By T.VenkataSridhar , ETC
78
79 By T.VenkataSridhar , ETC
80
By T.VenkataSridhar , ETC
 (TBS)

The capacitor CS across the

source resistance assumes its
open-circuit equivalence for
dc, allowing RS to define the
operating point.
Under ac conditions, the
capacitor assumes the
short-circuit state and “short
circuits” the effects of RS.

81 By T.VenkataSridhar , ETC
Figure 12: Network of Fig. 11 following the substitution
of the JFET ac equivalent circuit.

82 Figure 13: Redrawn network of Fig. 12. By T.VenkataSridhar , ETC

 Initially, the resistance rd will be left out of the analysis to form a basis for comparison.

Figure 14: Self-bias JFET configuration including the effects of RS with rd = ∞Ω.

83 By T.VenkataSridhar , ETC
84 By T.VenkataSridhar , ETC
 Figure 15: Including the effects of rd in the self-bias JFET configuration.

85 By T.VenkataSridhar , ETC
86 By T.VenkataSridhar , ETC
87 By T.VenkataSridhar , ETC
88 By T.VenkataSridhar , ETC
 (VDB try to study/solve yourself)
The popular voltage-divider configuration for BJTs can also be applied to JFETs as
demonstrated in Fig. 16.

R1 and R2 are in parallel with the open-circuit

equivalence of the JFET, resulting in Fig. 17
&18

Figure 16: JFET voltage-divider configuration.

89 By T.VenkataSridhar , ETC
 Figure 18: Redrawn network of Fig. 17.
Figure 17: Network of Fig. 16 under ac conditions.

Note that the equations for Zo

and Av are the same as obtained
for the fixed-bias and self-bias
(with bypassed RS)
configurations. The only
difference is the equation for Zi,
which is now sensitive to the
parallel combination of R1 and
R2.

90 By T.VenkataSridhar , ETC
 The last JFET configuration to be analyzed in detail is the common-gate configuration of
Fig. 19, which parallels the common-base configuration employed with BJT transistors.
Substituting the JFET equivalent circuit results in Fig. 20.
Note the continuing requirement that the controlled source gmVgs be connected from drain
to source with rd in parallel. The isolation between input and output circuits has obviously
been lost since the ‘gate terminal is now connected to the common ground’ of the network
and the controlled current source is connected directly from drain to source.
In addition, the resistor connected between input terminals is no longer R G, but the resistor
RS connected from source to ground.
Note also the location of the controlling voltage Vgs and the fact that it appears directly
across the resistor RS.

Figure 19: JFET common-gate configuration. Figure 20: Network of Fig. 19 following
substitution of JFET ac equivalent model
91 By T.VenkataSridhar , ETC
 Figure 21: Determining Z’i for the network of Fig. 19.
92
93 By T.VenkataSridhar , ETC
94 By T.VenkataSridhar , ETC
95 By T.VenkataSridhar , ETC
96 By T.VenkataSridhar , ETC
 Applying Kirchhoff’s current law at node S,
we obtain

97 By T.VenkataSridhar , ETC
98 By T.VenkataSridhar , ETC
 ( Try to study/solve tutorials yourself )

99 By T.VenkataSridhar , ETC
 Further Refer
Electronic Devices and Circuit Theory.
By
Robert L. Boylstad, Louis Nashelsky.

Electronic Devices and Circuits.

By
Jacob Millman, Christos C Halkias.

100
UP
By T.VenkataSridhar , ETC