(I) CMOS PROCESSING TECHNOLOGY:The design of CMOS integrated circuits is highly dependent upon the fabrication steps.

A typical CMOS integrated circuit will consist of many individual layers such as polycrystalline silicon (poly), silicon dioxide (quartz glass), and metal conductors. Each layer is defined by its own distinct pattern made up of geometrical objects that are strategically placed relative to other layers to form transistors and the needed interconnect lines that define the circuit itself. The processing sequence consists of the physical steps that must be performed in order to create the patterned layers on a silicon substrate. (A) Oxides:Silicon dioxide is used extensively in integrated circuits because it is easy to grow or deposit, and has excellent insulating characteristics. It is used as the gate insulator in a MOSFET, and provides insulation between conducting layers. There are two ways that oxides are created, thermal growth and CVD (chemical vapor deposition). Both are summarized below. Thermal Oxides:Thermally-grown oxides use silicon atoms from the substrate in the reaction Si + O2 SiO2 which creates silicon dioxide at an elevated growth temperature, typically from about 900C to 1100C. This is called dry oxidation to distinguish it from a wet oxidation process that obtains the oxygen from steam via

in about the same temperature range. In general, dry oxidation produces a better insulator but ischaracterized by relatively slow growth rate; steam oxidation is much faster, but the resultingoxides are of lower quality. One important characteristic of the thermal oxidation process is that silicon is consumed during the oxide growth. CVD Oxides:Chemical vapor deposition (CVD) oxides are created using reactions such as the one below that combines silane (SiH4)with oxygen: which is valid for temperatures below 1000C. Reactions of this type create molecules that are then deposited on top of the wafer. The important characteristic

of a CVD oxide is that it does not use silicon atoms from the substrate, so it can be deposited on top of any existing layer. CVD oxides are used extensively as insulating dielectrics between conducting layers such as metals above the surface of the silicon. (B) Polysilicon:Modern MOS technology makes heavy use of polycrystalline silicon (which is called polysilicon or simply poly) as a deposited conducting layer on top of oxides. A simple reaction to produce poly is the pyrolysis of silane

which gives varying characteristics as the temperature is varied. Polycrystal silicon gains its name because it consists of many small regions crystal, called crystallites, instead of having a single crystal structure throughout. This state is achieved by depositing silicon over an amorphous material such as silicon dioxide. Silicon atoms attempt to form crystals, but do not have a well-defined base to grow on. This results in the formation of the local crystal regions called crystallites. Polysilicon is used because it provides excellent coverage, has good adhesion properties to the silicon dioxide surface, and can be subjected to high temperature processing steps. One of the drawbacks of the material is that even heavily doped poly has a substantial resistance to current flow. This problem is solved by using a high-temperature (refractory) metal such as titanium as a coating on the top, creating what is called a silicide.. (C) Metal Layers :Most interconnects are created using a patterned layer of metals or metal alloys and compounds. In modern processing, 4 to 7 or more separate metal interconnect layers have become commonplace. In the early days of MOS processing, aluminum (A1) was used exclusively for FET gates and interconnects. It was the metal of choice because it was easy to evaporate and deposit on the wafer and exhibited good adhesion to the surfaces. One of the drawbacks was its relatively low melting temperature. Refractory metals such as platinum and tungsten are deposited on top of polysilicon to create silicides that have a low sheet resistance. Tungsten itself is used for plugs between metal layers. And, more recently, work by IBM has led to the use of copper as a viable interconnect material.

The CMOS Process Flow:The basic sequence that is needed to fabricate nFETs and pFETs in a p-type wafer is called an n-well process, since an n-region must be introduced to accommodate the pFETs.

Figure 1: Initial steps in a Bulk n-Well Processs

The starting point in our example process is a heavily doped P+ wafer that we will generally call the substrate. A thin P- silicon epitaxial layer is grown on top of the wafer to provide a well-defined background for the transistors; this results in the cross-sectional view with the general structure depicted in Figure 1(a). Since nFETs have a p-type bulk, they can be created in the epitaxial layer. A pFET, on the other hand, requires an n-type bulk, so that we provide an n-well in the pepitaxial layer for these transistors. The n-well is created using a deep ion implant that is diffused deeper into the substrate, resulting in the cross-section shown in Figure 1(b). Once this has been accomplished, the threshold voltage ion implant adjustments must be performed for both nFETs and pFETs. These are shown in Figures 1(c) and 1(d). Creating a positive nFET threshold voltage requires a boron(p-type) with a dose determined by the oxide thickness, doping levels, and other physical parameters.

The working value of the pFET threshold voltage is also established by a ion implantation step; a donor implant makes the value more negative while an acceptor implant makes the value less negative. The next step is the creation of the dielectric isolation regions. This is summarized by the steps shown in Figure1(e) and 1(f).

Figure-1: Initial steps in a Bulk n-Well Processs The next group of processing steps are used to form the transistors themselves. Access to the bare silicon surface [Figure 2(a)] is achieved by stripping the nitride and stress-relief oxide layers.This allows the careful growth of the gate oxide layer

in which XOX is established as in Figure 2(b). The gate oxide establishes the value of the oxide capacitance per unit area and is considered one of the most critical steps in the CMOS process flow.

Figure 2: Formation of MOSFETs in CMOS Process The next step is to deposit the gate polysilicon layer, which is then patterned by lithography according to the location of the transistor gates; this results in the structure shown in Figure 2(c).The transistors themselves are formed by ion implants using the self-aligned scheme. pFETs are created using a p-type boron implant in which nFET locations are blocked with photoresist; the resulting crosssection is portrayed in Figure 2(d). Similarly, nFETs require an n-type implant for drain and source regions. To accomplish this, pFET locations are blocked with resist while the n-implant is performed, leaving the structure shown in Figure 2(e). At this point, both FET polarities are established.

(e) nFET n+ drain/ source implant Figure 2: Formation of MOSFETs in CMOS Process Figure 3 illustrates the above-wafer steps in the processing sequence. In (a), the surface has been coated with a CVD oxide that acts to electrically insulate the device from overlaying conductors. In advanced processes, this is followed by steps that planarize the surface for the next material layer. Contact cuts are etched into the oxide where needed, and then filled with a metal plug such as tungsten [Figure 3(b)] . The first layer of metal interconnect, denoted generically as Metal1 is deposited and patterned as implied by the view in Figure 3(c).This is repeated for each subsequent interconnect level. Figure 4 illustrates the crosssectional view after the deposition of the second metal; in this case, the contacts are called vias.

Figure 3: First Metallization Step

Figure 4: Cross sectional view after second metal deposition