Features of 8086 Microprocessor

1. Intel 8086 was launched in 1978.

2. It was the first 16-bit microprocessor.
3. This microprocessor had major improvement over the execution
speed of 8085.
4. It is available as 40-pin Dual-Inline-Package (DIP).
5. It is available in three versions:
a. 8086 (5 MHz)
b. 8086 (8 MHz)
c. 8086 (10 MHz)
6. It consists of 29,000 transistors.
7. It had Multiply and Divide instructions.
 Data Structure
• For multiple-byte data items stored in memory, need to specify
which order:

• Most Significant byte at lowest address ("Big Endian"), OR

• Least Significant byte at lowest address ("Little Endian")
• 8086 has a little Endian data structure
 Block Diagram of Intel 8086
The 8086 CPU is divided into two functional units:

1. Bus Interface Unit (BIU)

2. Execution Unit (EU)
Internal (Block Diagram) Architecture of 8086
CPU

Fig. 1: Block Diagram of Intel 8086

 Bus Interface Unit (BIU)
The BIU provides hardware functions. Including
generation of the memory and I/0 addresses for the
transfer of data between itself and the outside world.

Fetch the instruction or data from memory.

Write the data to memory.

 Instruction Queue
To increase the execution speed, BIU fetches as many as six
instruction bytes ahead to time from memory.

All six bytes are then held in first in first out 6 byte register
called instruction queue.

Then all bytes have to be given to EU one by one.

This pre fetching operation of BIU may be in parallel with

execution operation of EU, which improves the speed execution
of the instruction.
 Execution Unit (EU)
The functions of execution unit are:
To decode the instructions.
To execute the instructions.
EU receives the program instruction codes and data from
the BIU, executes these instructions and store the result in
general purpose registers. By passing the data back to the
BIU data can be stored in a memory location or written to
an output device
It receives and outputs all its data through BIU.
 Fetch and Execute cycle
• The BIU outputs the contents of the instruction pointer register
(IP) onto the Address bus, causing the selected byte or word in
memory to be read into the BIU.
• Register IP is incremented by one to prepare for the next
instruction fetch.
• Once inside the BIU, the instruction is passed to the queue: a
first-in/first-out storage register sometimes likened to a pipeline.
• Assuming that the queue is initially empty, the EU immediately
draws this instruction from the queue and begins execution.
 Fetch and Execute cycle
• While the EU is executing this instruction, the BIU proceeds to

fetch a new instruction. Depending on the execution time of the

first instruction, the BIU may fill the queue with several new
instructions before the EU is ready to draw its next instruction.

• The cycle continues, with the BIU filling the queue with

instructions and the EU fetching and executing these

instructions.
Fetch and Execute cycle
 Programming model of 8086
• The programming model for a microprocessor shows the various

internal registers that are accessible to the programmer. The

Following Figure is a model for the 8086.Ingeneral, each register
has a special function.
 Registers
• General Purpose Registers:
• These registers can be used as 8-bit registers individually or can be used as
16-bit in pair to have AX,BX, CX, and DX.

• Pointer Group Registers:

• The pointer and index group are all 16 bit registers. These registers are used

as memory pointers.

• MOV AH,[SI]
• Register IP is included into memory pointer but this register has only one
function to point the next instruction to be fetched to the BIU.
 Registers
• Segment Register
• Additional registers called

segment registers generate

memory address when
combined with other in the
microprocessor. In 8086
microprocessor, memory is
divided into 4 segments as
follow:
 CONT…
• 1. Code Segment (CS): The CS register is used for addressing a
memory location in the Code Segment of the memory, where the
executable program is stored.
• 2. Data Segment (DS): The DS contains most data used by program.
Data are accessed in the Data Segment by an offset address or the
content of other register that holds the offset address.
• 3. Stack Segment (SS): SS defined the area of memory used for
the stack.
• 4. Extra Segment (ES): ES is additional data segment that is
used by some of the string to hold the destination data.
 Segment registers
• Calculate the beginning and ending address for the data
segment assuming that register
• DS = E000H
• Solution

• Base address can be found by appending four 0’s :

• Base address E0000H
• Ending address can be found by adding 64K ..
• E0000H + FFFFH = EFFFFH
 118

Flag Registers of 8086

Flag register in EU is of 16-bit and is shown in fig. :

Flags Register determines the current state of the processor.

They are modified automatically by CPU after mathematical
operations, this allows to determine the type of the result, and
to determine conditions to transfer control to other parts of the
program.
 119

CONT…
8086 has 9 flags and they are divided into two categories:

• 1. Conditional Flags
• 2. Control Flags
 120

Conditional Flags
❑ Conditional flags represent result of last arithmetic or logical

instruction executed. Conditional flags are as follows:

❑ Carry Flag (CF)

❑ Auxiliary Flag (AF)

❑ Parity Flag (PF)

❑ Zero Flag (ZF)

❑ Sign Flag (SF)

❑ Overflow Flag (OF)

 121

Conditional flag
• Carry Flag (CF) - this flag is set to 1 when there is an carry out from
MSB.
• Parity Flag (PF) - this flag is set to 1 when there is even number of one
bits in result, and to 0 when there is odd number of one bits.
• Auxiliary Flag (AF) - set to 1 when there is a carry from low nibble to
upper nibble(4 bits).
• Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this
flag is set to 0.
• Sign Flag (SF) - set to 1 when result is negative. When result is
positive it is set to 0. (This flag takes the value of the most significant
bit.)
• Overflow Flag (OF):Used for signed arithmetic operations.
 122

Control Flags
❑ Control flags are set or reset deliberately to control the

operations of the execution unit. Control flags are as

follows:
1. Trap Flag (TP):
2. Interrupt Flag (IF):

3. Direction Flag (DF):

 123

Control Flags
• Trap Flag (TF) - Used for on-chip debugging.

• Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to

interrupts from external devices.

• Direction Flag (DF) –Causing the string instruction to auto decrement

the index register when set and Clearing DF causes the Auto increment.
Physical And Logical Address
 IP Register
• The Instruction Pointer register(IP)
contains the offset address of the next
sequential instruction to be executed.
Thus, the IP register can not be
directly modified.
• These register descriptions have
slowly been introducing us to a new
way of addressing memory, called:
• segment-offset addressing.

• The segment register is used to point

to the beginning of any one of the 64K
memory
 Physical Address
• Each segment register is 16 bit wide while the address bus is

20 bits wide. The BIU takes care of this by appending four 0 s

to the lower order bits of the segment register.

Physical Address 20 bit

Converting Logical Address to Physical address
Segment Register and Default offset registers in
8086
Segment Registers Default offset Register
CS IP
DS BX,SI,DI
SS SP or BP
ES DI for String Instruction
Ex1
• Let us Assume that the CS register has the value
3000H and IP register has value 2000h. To fetch an
instruction from the next memory location.

CS x 10H = 30000H Base address of the code Segment

+IP = 02000H Offset Address
32000H Memory Address from where the next Instruction to be
taken
Ex:2
• Consider the Execution of the instruction MOV AX,[BX]
• Let us assume that DS and BX have the values 1000H
and 3000H respectively.
• To calculate the address from where the data has to be
taken

DS X 10 H = 10000H Base Address of Data Segment

+ BX = 03000H Offset Address
13000H Memory address from where data is to
be taken
• If the segment registers CS,DS and SS have values 1000H ,
2000H, 3000H respectively. What will be the 20 bit start and
end address of the code , data and Stack Segments?
8086 Pin Diagram
Pin Description
• Data Bus (AD0 – AD15): D0-D15
• These 16 pins are used as Address and data bus. During T1 state

this lines provides address and data lines are valid only during T2
to T4.

• Whenever the ALE pin is high these pins works as a address bus

and when ALE is low these pins carry the data.

Pin Description
◼ Address bus (AD0 – AD 15, A16/S3 – A19/S6):
• This 20 lines are correspond to the CPU’s 20-bit address.
These lines are valid only during T1 state.
• S6 : always remains at logic 0
• S5 : indicate condition of IF flag bit
• S4 and S3 indicate the segment addressed by 8086 during the
current bus cycle
• NMI : Non- Maskable interrupt is a hardware interrupt.
• similar to INTR except that no check IF flag bit

• RESET :
• This input causes the 8086 to reset, if it is held at logic 1 for at least
4 clock cycle. Whenever the 8086 is RESET, CS and IP are
initialized to FFFFh and 0000H, respectively and all other registers
are initialized to 0000h.

• VCC(power supply) : +5.0V, ±10%

• INTR-Interrupt Request :

• This is a level triggered input. This is sampled during the last

clock cycles of each instruction to determine the availability of the
request. If any interrupt request is pending, the processor enters the
interrupt acknowledge cycle.
• When IF = 1 and if INTR is held high the 8086 gets interrupted .

When IF = 0 , INTR is disabled.

• Ready:
• This input signal is used to insert wait state in to the timing cycle of
8086. if the READY pin is at logic 1, it has no effect on operation
of the microprocessor. If it is at logic 0, the 8086 enters the wait
state and remains idle. This signal is used to interface the slowly
interfacing device with the 8086.

• MN/MX:
• This pin is used to select either the minimum mode or maximum mode
operation for the 8086. this is achieved by connecting this pin to either
+5V (Minimum mode) or to the ground for maximum mode.
◼ TEST :
• This pin is an input pin that is tested by wait instruction. If this pin is at
logic 0 , the wait instruction function as NOP. This pin is often connected
to the BUSY pin of the 8087 to perform the floating point operations.

• Read (RD):
• This active low output signal indicates that the direction of data flow
from memory or IO to CPU. It can be combined with M/IO to generate
MEMR and IOR signals.
 Pin Description
• Clock (CLK):
• All events in the microprocessor are synchronizes to the system clock

applied to CLK pin. The clock signal must have duty cycle for 33%.

◼ BHE / S7:
• This signal is multiplexed with the S7 status indicator. It is output only

during the T1 state. BHE and A0 are typically used to select even or
odd memory banks.
BHE A0 Action
0 0 Access 16-bit word
0 1 Access odd byte to D8- D15
1 0 Access even byte to D0-D7
1 1 No action
Function of Pins used in Minimum mode
• INTA –Interrupt Acknowledge :
• This signal is used as a read strobe for interrupt acknowledge
cycles. i.e. when it goes low, the processor has accepted the
interrupt.

◼ DT/R –Data Transmit/Receive:

• This output is used to decide the direction of data flow through the
transreceivers (bidirectional buffers). When the processor sends out
data, this signal is high and when the processor is receiving data,
this signal is low.
Pin Description
• ALE (Address Latch Enable):
• Signal output on this pin can be used to Demultiplex the address ,

data bus and status lines. ALE pulse is high during T1 state.

• M/IO :
• The 8086 does not output separate memory and I/O signals.
Instead , the M/IO signal output during early in T1 state. So if
M/IO = 1 then it is memory operation or M/IO = 0 then IO
operation.
Pin Description

◼ Write(WR):
• This active low output signal indicates that the direction of data flow

from CPU to memory or IO. It can be combined with M/IO to generate

MEMW and IOW signals.
• DEN –Data Enable :
• This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transreceivers (
bidirectional buffers ) to separate the data from the multiplexed
address/data signal. It is active from the middle of T2 until the
middle ofT4. This is tristated during ‘ hold acknowledge’ cycle.
• HOLD, HLDA-Acknowledge :
• When the HOLD line goes high, it indicates to the processor that

another master is requesting the bus access. The processor, after

receiving the HOLD request, issues the hold acknowledge signal on
HLDA pin, in the middle of the next clock cycle after completing
the current bus cycle.
• GND(Ground) : GND

• Minimum mode Pins

• M/IO
• WR
• INTA
• HOLD
• HLDA
• DEN
• ALE
Maximum Mode Pins
• MN/MX = 0(ground)
• S2’,S1’,S0’:indicate function of current bus cycle
• these signal : normally decoded by 8288 bus controller
❑Request / Grant (RQ0/GT0 , RQ1/GT1) :

o These two pins are bidirectional, allowing a coprocessor to request

control of the system buses . The 8086 respond by disconnecting itself

from the system buses and pulsating the RQ/GT line in

acknowledgement. These lines are bidirectional and are used to request

and grant DMA operation.

• LOCK(lock output):
• lock is an output signal intended for use in a bus arbitration scheme with

another processor. Arbitration refers to the process of determining which

processor should have the control of the system buses at any given time.
The LOCK signal is output low during the execution of any instruction
with LOCK prefix. This signal is meant to be output whenever
processor wants to lock out other processor from using the bus.
• QS1, QS0(queue status) :
• show status of internal instruction queue
• provided for access by the numeric coprocessor(8087)
• They allow the coprocessor to track the progress of an instruction
through the queue.
 8284A
clock generation, RESET synchronization, READY
synchronization, and TTL-level peripheral clock signal

Pin Diagram of 8284A Clock generator

8284A
8284A connection with 8086
Bus Buffering and Latching
The 8288 Bus Controller
Minimum mode Interface
Maximum mode Interface
8288 Commands
Memory Read cycle Minimum mode
Memory write cycle Minimum mode
Minimum-mode I/O read cycle
Minimum-mode I/O write cycle
Maximum mode Memory Write Cycle
 Memory Bank

1Mx 8 Memory bank of 8088 Byte transfer by 8088

Memory Bank
Memory Bank
 Memory Bank
BHE A0 Action
0 0 Access 16-bit word
0 1 Access odd byte to D8- D15
1 0 Access even byte to D0-D7
1 1 No action
 Memory Bank
BHE A0 Action
0 0 Access 16-bit word
0 1 Access odd byte to D8- D15
1 0 Access even byte to D0-D7
1 1 No action
 Memory Bank
BHE A0 Action
0 0 Access 16-bit word
0 1 Access odd byte to D8- D15
1 0 Access even byte to D0-D7
1 1 No action
 Memory bank
BHE A0 Action
0 0 Access 16-bit word
0 1 Access odd byte to D8- D15
1 0 Access even byte to D0-D7
1 1 No action
Addressing Modes
• Method of Accessing data from memory or Registers.
• Types of Addressing Modes
• Register Addressing mode
• Immediate Addressing mode
• Direct Addressing Mode
• Register Indirect Addressing Mode
• Based-Relative Addressing mode
• Indexed Relative Addressing mode
• Based-indexed relative addressing mode
Register Addressing mode
• Transfers a copy of a byte or word from the source register or
memory location to the destination register or memory
location.

MOV BX, DX ; copy the contents of DX into BX

MOV ES,AX ; copy the contents of AX into ES
ADD AL,BH ; add the contents of BH to contents of AL

Source and destination registers must have the same size

Register Addressing mode
Immediate Addressing mode
• Transfers the source, an immediate byte or word of data, into
the destination register or memory location.
• The source operand is a constant
• Immediate addressing mode can be used to load information
into any of the registers except the segment registers and flag
registers.
MOV AX,2550H ; move 2550H into AX
MOV CX,625 ; load the decimal value 625 into CX
MOV BL, 40H ; load 40H into BL

MOV AX,2550H
MOV DS, AX
MOV DS, 0123H ; illegal instruction!
Immediate Addressing mode
Direct Addressing mode
• Moves a byte or word between a memory location and a
register.
• This address is the offset address.

MOV AX, [2400] ; move contents of DS:2400H into AX

The physical address is calculated by combining the contents

of offset location 2400 with DS.
Example::
Find the physical address off the memory location and its contents
after the execution off the following, assuming that DS = 1512H.
MOV AL, 3BH
MOV [3518], AL

Solution:
First 3BH is copied into AL,
Then in line two, the contents off AL are moved to logical address
DS:3518 which is 1512:3518.
Shifting DS left and adding it to the offset gives the physical
address off 18638H (15120H + 3518H = 18638H).
After the execution off the second instruction, the memory
location with address 18638H will contain tithe value 3BH..
• Example for the instruction MOV AL,[1234H] and DS =
1000H
Examples of Direct Addressing modes

MOV AL,[2C00h] Copy the content of data segment memory location 2C00h in to AL
register (8 Bit)

MOV AX,[3400h] Copies the word content of data segment memory location 3400h in
to AX (16 bit)

MOV [100H], AL Copies BL in to Data Segment Memory Location 100h (8 bit)

MOV [72C2h], CX Copies CX in to data segment memory location 72C2H (16 bit)

MOV Copies Al in to extra segment memory location 2000H (8 Bit)

ES:[2000H],AL

MOV SP,[4E2h] Copies the word contents of data segment memory location 4E2h in
SP (16 bit)
Register Indirect Addressing mode
• Instruction specifies an address where data is located. This

addressing mode works with SI,DI,BX,BP registers.

• Example1 : Write value 0065h at the address pointed by DS:BX
• MOV BX,1200h
• MOV [BX],65H

• Example1 : transfer the byte from AL to the address pointed by

DS: 1202H
• MOV [1202h],AL
The operation of MOV AX,[BX] instruction when BX =
1000H and DS = 0100H.
Base Plus index addressing mode
• This mode is similar to indirect addressing mode because it
indirectly addresses the memory data. This type of addressing
uses one base register and one index register to indirectly
address the memory
• MOV DX,[BX+DI]

• Suppose BX = 1000h , DI = 0010h , and DS = 0100h, which

translate in to memory location 2101H. This instruction
transfers a copy of the word from location 0210H in to DX
register.
Base Plus Index Mode
MOV DX,[BX+DI]
Examples
Base Plus index Plus offset addressing mode
• Examples:
• MOV AL,DISP[BX][SI]
• MOV AL, DISP[BX+DI]
• MOV AL,[BP+SI+DISP]

• MOV AX,[BX+DI+15]
Instruction Set
• Data Transfer Instructions
• MOV
• XCHG
• XLAT
• LEA
• LDS
• LES
MOV
MOV Destination, Source
The destination can be a register or a memory location. The
source can be a register, a memory location or an immediate
number. The source and destination cannot both be memory
locations. They must both be of the same type (bytes or words).
MOV instruction does not affect any flag.
 Examples of MOV
MOV CX, 037AH Put immediate number 037AH to CX

MOV BL, [437AH] Copy byte in DS at offset 437AH to BL

MOV AX, BX Copy content of register BX to AX

MOV DL, [BX] Copy byte from memory at [BX] to DL

MOV DS, BX Copy word from BX to DS register

MOV RESULT [BP], AX Copy AX to two memory locations;

AL to the first location, AH to the second;
EA of the first memory location is sum of the
displacement represented by RESULTS and content of BP. Physical address
= EA + SS.

MOV ES: RESULTS [BP], AX Same as the above instruction, but physical address =
EA + ES, because of the segment override prefix ES
XCHG
• XCHG Destination, Source
• The XCHG instruction exchanges the content of a register with the
content of another register or with the content of memory
location(s). It cannot directly exchange the content of two memory
locations. The source and destination must both be of the same
type (bytes or words). The segment registers cannot be used in this
instruction. This instruction does not affect any flag.
Examples

XCHG AX, DX Exchange word in AX with word in DX

XCHG BL, CH Exchange byte in BL with byte in CH

XCHG AL, PRICES [BX] Exchange byte in AL with byte in memory at

EA = PRICE [BX] in DS.
LEA
• LEA Register, Source

This instruction determines the offset of the variable or

memory location named as the source and puts this offset in
the indicated 16-bit register. LEA does not affect any flag.

LEA BX, PRICES Load BX with offset of PRICE in DS

LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP in SS

LEA CX, [BX][DI] Load CX with EA = [BX] + [DI]

LDS
• LDS Register, Memory address of the first word

This instruction loads new values into the specified register and
into the DS register from four successive memory locations. The
word from two memory locations is copied into the specified
register and the word from the next two memory locations is
copied into the DS registers. LDS does not affect any flag.

LDS BX, [4326] Copy content of memory at displacement 4326H in DS to

BL, content of 4327H to BH. Copy content at displacement of
4328H and 4329H in DS to DS register.

LDS SI, SPTR Copy content of memory at displacement SPTR and SPTR + 1
in DS to SI register. Copy content of memory at displacements
SPTR + 2 and SPTR + 3 in DS to DS register. DS: SI now points at start of
the desired string.
LES
• LES Register, Memory address of the first word

This instruction loads new values into the specified register and into the
ES register from four successive memory locations. The word from the
first two memory locations is copied into the specified register, and the
word from the next two memory locations is copied into the ES register.
LES does not affect any flag.

LES BX, [789AH] Copy content of memory at displacement 789AH in

DS to BL, content of 789BH to BH, content of
memory at displacement 789CH and 789DH in DS is copied to ES
register.

LES DI, [BX] Copy content of memory at offset [BX] and offset
[BX] + 1 in DS to DI register. Copy content of memory at
offset [BX] + 2 and [BX] + 3 to ES register.
XLATB
•The XLATB instruction is used to translate a byte from one code (8
bits or less) to another code (8 bits or less).

•The instruction replaces a byte in AL register with a byte pointed

to by BX in a lookup table in the memory. Before the XLATB
instruction can be executed, the lookup table containing the
values for a new code must be put in memory, and the offset of
the starting address of the lookup table must be loaded in BX.

•The code byte to be translated is put in AL. The XLATB instruction

adds the byte in AL to the offset of the start of the table in BX. It
then copies the byte from the address pointed to by (BX + AL)
back into AL. XLATB instruction does not affect any flag.
Example
• 8086 routine to convert unpacked BCD to ASCII equivalent: A BCD
code byte is in AL at the start, ASCII code in AL after conversion.

MOV BX, OFFSET ASCII Point BX to the start of ASCII table in

DS
XLATB Replace BCD in AL with ASCII from
table.
 Arithmetic
Instructions
ADD, ADC
• ADD Destination, Source
• ADC Destination, Source
These instructions add a number from some source to a number in some
destination and put the result in the specified destination. The ADC also
adds the status of the carry flag to the result. The source may be an
immediate number, a register, or a memory location. The destination
may be a register or a memory location. The source and the destination
in an instruction cannot both be memory locations.

Flags affected: AF, CF, OF, SF, ZF.

Examples
ADD AL, 74H Add immediate number 74H to content of AL. Result in AL

ADC CL, BL Add content of BL plus carry status to content of CL

ADD DX, BX Add content of BX to content of DX

ADD DX, [SI] Add word from memory at offset [SI] in DS to content of DX

ADC AL, PRICES [BX] Add byte from effective address PRICES [BX]
plus carry status to content of AL

ADD AL, PRICES [BX] Add content of memory at effective address

PRICES [BX] to AL
SUB,SBB
• SUB Destination, Source
• SBB Destination, Source
These instructions subtract the number in some source from the
number in some destination and put the result in the destination. The
SBB instruction also subtracts the content of carry flag from the
destination. The source may be an immediate number, a register or
memory location. The destination can also be a register or a memory
location. However, the source and the destination cannot both be
memory location.

Flags affected: AF, CF, OF, PF, SF, ZF.

 Examples
SUB CX, BX CX – BX; Result in CX

SBB CH, AL Subtract content of AL and content of CF from

content of CH. Result in CH

SUB AX, 3427H Subtract immediate number 3427H from AX

SBB BX, [3427H] Subtract word at displacement 3427H in DS and

content of CF from BX

SUB PRICES [BX], 04H Subtract 04 from byte at effective address PRICES
[BX], if PRICES is declared with DB; Subtract 04
from word at effective address PRICES [BX], if it is declared with DW.

SBB CX, TABLE [BX] Subtract word from effective address TABLE [BX]
and status of CF from CX.

SBB TABLE [BX], CX Subtract CX and status of CF from word in

memory at effective address TABLE[BX].
MUL
• MUL Source
This instruction multiplies an unsigned byte in some source
with an unsigned byte in AL register or an unsigned word in
some source with an unsigned word in AX register. The
source can be a register or a memory location. When a byte
is multiplied by the content of AL, the result (product) is put
in AX. When a word is multiplied by the content of AX, the
result is put in DX and AX registers.
 Examples

MUL BH Multiply AL with BH; result in AX

MUL CX Multiply AX with CX; result high word in DX, low word in
AX

MUL BYTE PTR [BX] Multiply AL with byte in DS pointed to by [BX]

MUL FACTOR [BX] Multiply AL with byte at effective address

FACTOR [BX], if it is declared as type byte with DB. Multiply
AX with word at effective address FACTOR [BX], if it is declared
as type word with DW.

MOV AX, MCAND_16 Load 16-bit multiplicand into AX

MOV CL, MPLIER_8 Load 8-bit multiplier into CL
MOV CH, 00H Set upper byte of CX to all 0’s
MUL CX AX times CX; 32-bit result in DX and AX
IMUL
• IMUL Source

This instruction multiplies a signed byte from source with a

signed byte in AL or a signed word from some source with a
signed word in AX. The source can be a register or a memory
location. When a byte from source is multiplied with content of
AL, the signed result (product) will be put in AX. When a word
from source is multiplied by AX, the result is put in DX and AX.
If the magnitude of the product does not require all the bits of
the destination, the unused byte / word will be filled with
copies of the sign bit.
Examples
IMUL BH Multiply signed byte in AL with signed byte in BH;
result in AX.

IMUL AX Multiply AX times AX; result in DX and AX

MOV CX, MULTIPLIER Load signed word in CX

MOV AL, MULTIPLICAND Load signed byte in AL

IMUL CX Multiply CX with AX; Result in DX and AX
DIV
• DIV Source

This instruction is used to divide an unsigned word by a byte

or to divide an unsigned double word (32 bits) by a word.
When a word is divided by a byte, the word must be in the
AX register. The divisor can be in a register or a memory
location. After the division, AL will contain the 8-bit
quotient, and AH will contain the 8-bit remainder. When a
double word is divided by a word, the most significant word
of the double word must be in DX, and the least significant
word of the double word must be in AX. After the division,
AX will contain the 16-bit quotient and DX will contain the
16-bit remainder.
Examples
DIV BL Divide word in AX by byte in BL; Quotient in AL, remainder
in AH

DIV CX Divide down word in DX and AX by word in CX; Quotient in

AX, and remainder in DX.

DIV SCALE [BX] AX / (byte at effective address SCALE [BX]) if SCALE [BX] is
of type byte; or (DX and AX) / (word at effective address
SCALE[BX] if SCALE[BX] is of type word
IDIV
• IDIV Source
This instruction is used to divide a signed word by a signed byte, or to
divide a signed double word by a signed word

When dividing a signed word by a signed byte, the word must be in

the AX register. The divisor can be in an 8-bit register or a memory
location. After the division, AL will contain the signed quotient, and
AH will contain the signed remainder. The sign of the remainder will
be the same as the sign of the dividend.
IDIV
When dividing a signed double word by a signed word, the most
significant word of the dividend (numerator) must be in the DX register,
and the least significant word of the dividend must be in the AX
register. The divisor can be in any other 16-bit register or memory
location. After the division, AX will contain a signed 16-bit quotient,
and DX will contain a signed 16-bit remainder. The sign of the
remainder will be the same as the sign of the dividend.

IDIV BL Signed word in AX/signed byte in BL

IDIV BP Signed double word in DX and AX/signed

word in BP

IDIV BYTE PTR [BX] AX / byte at offset [BX] in DS

INC
• INC destination

The INC instruction adds 1 to a specified register or to a memory

location. AF, OF, PF, SF, and ZF are updated, but CF is not affected.
This means that if an 8-bit destination containing FFH or a 16-bit
destination containing FFFFH is incremented, the result will be all 0’s
with no carry.
 Examples
INC BL Add 1 to contains of BL register

INC CX Add 1 to contains of CX register

INC BYTE PTR [BX] Increment byte in data segment at offset contained
in BX.

INC WORD PTR [BX] Increment the word at offset of [BX] and [BX + 1]
in the data segment.

INC TEMP Increment byte or word named TEMP in the data

segment. Increment byte if MAX_TEMP declared with DB.
Increment word if MAX_TEMP is declared with DW.

INC PRICES [BX] Increment element pointed to by [BX] in array

PRICES. Increment a word if PRICES is declared as an
array of words; Increment a byte if PRICES is declared as an
array of bytes.
DEC
• DEC Destination
This instruction subtracts 1 from the destination word or byte. The
destination can be a register or a memory location. AF, OF, SF, PF, and
ZF are updated, but CF is not affected.

DEC CL Subtract 1 from content of CL register

DEC BP Subtract 1 from content of BP register

DEC BYTE PTR [BX] Subtract 1 from byte at offset [BX] in DS.

DEC WORD PTR [BP] Subtract 1 from a word at offset [BP] in SS.

DEC COUNT Subtract 1 from byte or word named COUNT in

DS. Decrement a byte if COUNT is declared with a DB;
Decrement a word if COUNT is declared with a DW.
DAA DECIMAL ADJUST AFTER BCD ADDITION

This instruction is used to make sure the result of adding two packed
BCD numbers is adjusted to be a legal BCD number. The result of the
addition must be in AL for DAA to work correctly.

Let AL = 59 BCD, and BL = 35 BCD

ADD AL, BL AL = 8EH; lower nibble > 9, add 06H to AL
DAA AL = 94 BCD, CF = 0

Let AL = 88 BCD, and BL = 49 BCD

ADD AL, BL AL = D1H; AF = 1, add 06H to AL

DAA AL = D7H; upper nibble > 9, add 60H to AL
AL = 37 BCD, CF = 1
DAS (DECIMAL ADJUST AFTER BCD SUBTRACTION)
This instruction is used after subtracting one packed BCD number from
another packed BCD number, to make sure the result is correct packed
BCD. The result of the subtraction must be in AL for DAS to work
correctly.

Let AL = 86 BCD, and BH = 57 BCD

SUB AL, BH AL = 2FH; lower nibble > 9, subtract 06H from AL
DAS AL = 29 BCD, CF = 0

Let AL = 49 BCD, and BH = 72 BCD

SUB AL, BH AL = D7H; upper nibble > 9, subtract 60H from AL
DAS AL = 77 BCD, CF = 1 (borrow is needed)
CBW (CONVERT SIGNED BYTE TO SIGNED WORD)

This instruction copies the sign bit of the byte in AL to all

the bits in AH. AH is then said to be the sign extension of
AL. CBW does not affect any flag.

Let AX = 00000000 10011011 (–155 decimal)

CBW Convert signed byte in AL to signed word in AX

AX = 11111111 10011011 (–155 decimal)
CWD (CONVERT SIGNED WORD TO SIGNED DOUBLE WORD)

This instruction copies the sign bit of a word in AX to all the bits of the
DX register. In other words, it extends the sign of AX into all of DX. CWD
affects no flags.

Let DX = 00000000 00000000, and AX = 11110000 11000111 (–3897 decimal)

CWD Convert signed word in AX to signed double word in DX:AX
DX = 11111111 11111111
AX = 11110000 11000111 (–3897 decimal)
AAD
• ADD converts unpacked BCD digits in the AH and AL register
into a single binary number in the AX register in preparation
for a division operation.

MOV AX, 0205h ; The unpacked BCD number 25

AAD ; After AAD, AH=0 and ; AL=19h (25)

After the division AL will then contain the unpacked BCD quotient and AH will
contain the unpacked BCD remainder.
AAM
• AAM converts the result of the multiplication of two valid
unpacked BCD digits into a valid 2-digit unpacked BCD
number
AAS
• AAS converts the result of the subtraction of two valid unpacked
BCD digits to a single valid BCD number.
AAA
• AAA converts the result of the addition of two valid unpacked
BCD digits to a valid 2-digit BCD number

Example:
MOV AH, 0 ; Clear AH for MSD
MOV AL, 6 ; BCD 6 in AL
ADD AL, 5 ; Add BCD 5 to digit in AL
AAA ; AH=1, AL=1 representing BCD 11
 Logical
Instructions
AND
AND Destination, Source
This instruction ANDs each bit in a source byte or word with the
same numbered bit in a destination byte or word. The result is put
in the specified destination. The content of the specified source is
not changed. The source can be an immediate number, the content
of a register, or the content of a memory location. The destination
can be a register or a memory location. The source and the
destination cannot both be memory locations.

AND CX, [SI] AND word in DS at offset [SI] with word in CX

register; Result in CX register

AND BH, CL AND byte in CL with byte in BH; Result in BH

AND BX, 00FFH 00FFH Masks upper byte, leaves lower byte
unchanged.
OR
OR Destination, Source

This instruction ORs each bit in a source byte or word with the
same numbered bit in a destination byte or word. The result is put
in the specified destination. The content of the specified source is
not changed. The source can be an immediate number, the content
of a register, or the content of a memory location. The destination
can be a register or a memory location. The source and destination
cannot both be memory locations.
Examples
OR AH, CL CL ORed with AH, result in AH, CL not changed

OR BL, 80H BL ORed with immediate number 80H; sets MSB of BL to 1

OR CX, TABLE [SI] CX ORed with word from effective address TABLE [SI];
Content of memory is not changed.
XOR
• XOR Destination, Source
This instruction Exclusive-ORs each bit in a source byte or word with
the same numbered bit in a destination byte or word. The result is
put in the specified destination. The content of the specified source
is not changed. The source can be an immediate number, the content
of a register, or the content of a memory location. The destination
can be a register or a memory location. The source and destination
cannot both be memory locations.

XOR CL, BH Byte in BH exclusive-ORed with byte in CL.

Result in CL. BH not changed.

XOR WORD PTR [BX], 00FFH Exclusive-OR immediate number 00FFH with
word at offset [BX] in the data segment.
Result in memory location [BX]
NOT
• NOT Destination
The NOT instruction inverts each bit (forms the 1’s complement) of a
byte or word in the specified destination. The destination can be a
register or a memory location. This instruction does not affect any
flag.

NOT BX Complement content or BX register

NOT BYTE PTR [BX] Complement memory byte at offset [BX] in data
segment.
NEG
• NEG Destination
This instruction replaces the number in a destination with its 2’s
complement. The destination can be a register or a memory location.
It gives the same result as the invert each bit and add one algorithm.

NEG AL Replace number in AL with its 2’s complement

NEG BX Replace number in BX with its 2’s complement

NEG BYTE PTR [BX] Replace byte at offset BX in DX with its 2’s
complement
CMP
• CMP Destination, Source
This instruction compares a byte / word in the specified source with a
byte / word in the specified destination. The source can be an
immediate number, a register, or a memory location. The destination
can be a register or a memory location. However, the source and the
destination cannot both be memory locations.

For the instruction CMP CX, BX, the values of CF, ZF, and SF will be as
follows:

CF ZF SF
CX = BX 0 1 0 Result of subtraction is 0
CX > BX 0 0 0 No borrow required, so CF = 0
CX < BX 1 0 1 Subtraction requires borrow, so CF = 1
Examples
CMP AL, 01H Compare immediate number 01H with byte in AL

CMP BH, CL Compare byte in CL with byte in BH

CMP CX, TEMP Compare word in DS at displacement TEMP with word at

CX

CMP PRICES [BX], 49H Compare immediate number 49H with byte at
offset [BX] in array PRICES
TEST
• TEST Destination, Source
This instruction ANDs the byte / word in the specified source with the
byte / word in the specified destination. Flags are updated, but
neither operand is changed. The test instruction is often used to set
flags before a Conditional jump instruction.

The source can be an immediate number, the content of a register,

or the content of a memory location. The destination can be a
register or a memory location. The source and the destination
cannot both be memory locations. CF and OF are both 0’s after
TEST. PF, SF and ZF will be updated to show the results of the
destination. AF is be undefined.
Examples

TEST AL, BH AND BH with AL. No result stored; Update PF, SF, ZF.

TEST CX, 0001H AND CX with immediate number 0001H; No result

stored; Update PF, SF, ZF

TEST BP, [BX][DI] AND word are offset [BX][DI] in DS with word in BP.
No result stored. Update PF, SF, and ZF
RCL
RCL Destination, Count

This instruction rotates all the bits in a specified word or byte some
number of bit positions to the left. The operation circular because
the MSB of the operand is rotated into the carry flag and the bit in
the carry flag is rotated around into LSB of the operand.

RCL DX, 1 Word in DX 1 bit left, MSB to CF, CF to LSB

MOV CL, 4 Load the number of bit positions to rotate into CL

RCL SUM [BX], CL Rotate byte or word at effective address
SUM [BX] 4 bits left Original bit 4 now in CF, original CF now in bit
3.
RCR
RCR Destination, Count

This instruction rotates all the bits in a specified word or byte some
number of bit positions to the right. The operation circular because
the LSB of the operand is rotated into the carry flag and the bit in
the carry flag is rotate around into MSB of the operand.

RCR BX, 1 Word in BX right 1 bit, CF to MSB, LSB to CF

MOV CL, 4 Load CL for rotating 4 bit position RCR BYTE PTR [BX], 4
Rotate the byte at offset [BX] in DS 4 bit positions right
CF = original bit 3, Bit 4 – original CF.
 ROL
• ROL Destination, Count
This instruction rotates all the bits in a specified word or byte to the
left some number of bit positions. The data bit rotated out of MSB is
circled back into the LSB. It is also copied into CF. In the case of
multiple-bit rotate, CF will contain a copy of the bit most recently
moved out of the MSB.

ROL AX, 1 Rotate the word in AX 1 bit position left, MSB to LSB and CF

MOV CL, 04H Load number of bits to rotate in CL

ROL BL, CL Rotate BL 4 bit positions

ROL FACTOR [BX], 1 Rotate the word or byte in DS at EA = FACTOR [BX]

by 1 bit position left into CF
 ROR
• ROR Destination, Source

This instruction rotates all the bits in a specified word or byte some
number of bit positions to right. The operation is desired as a rotate
rather than shift, because the bit moved out of the LSB is rotated
around into the MSB. The data bit moved out of the LSB is also copied
into CF.

ROR BL, 1 Rotate all bits in BL right 1 bit position LSB to MSB and to
CF

MOV CL, 08H Load CL with number of bit positions to be

rotated
ROR WORD PTR [BX], CL Rotate word in DS at offset [BX] 8 bit position
right
 SAL / SHL
• SAL Destination, Count
This instruction shifts each bit in the specified destination some number
of bit positions to the left. As a bit is shifted out of the LSB operation, a
0 is put in the LSB position. The MSB will be shifted into CF. The
destination operand can be a byte or a word. It can be in a register or in
a memory location.

SAL BX, 1 Shift word in BX 1 bit position left, 0 in LSB

MOV CL, 02h Load desired number of shifts in CL

SAL BP, CL Shift word in BP left CL bit positions, 0 in LSBs

SAL BYTE PTR [BX], 1 Shift byte in DX at offset [BX] 1 bit position left, 0 in
LSB
 SAR
• SAR Destination, Count
This instruction shifts each bit in the specified destination some
number of bit positions to the right. As a bit is shifted out of the MSB
position, a copy of the old MSB is put in the MSB position. In other
words, the sign bit is copied into the MSB. The LSB will be shifted into
CF. The destination operand can be a byte or a word. It can be in a
register or in a memory location.

SAR DX, 1 Shift word in DI one bit position right, new MSB = old MSB

MOV CL, 02H Load desired number of shifts in CL

SAR WORD PTR [BP], CL Shift word at offset [BP] in stack segment right by
two bit
 SHR
• SHR destination, source
This instruction shifts each bit in the specified destination some number
of bit positions to the right. As a bit is shifted out of the MSB position, a
0 is put in its place. The bit shifted out of the LSB position goes to CF. The
destination operand can be a byte or a word in a register or in a memory
location.

SHR BP, 1 Shift word in BP one bit position right, 0 in MSB

MOV CL, 03H Load desired number of shifts into CL

SHR BYTE PTR [BX] Shift byte in DS at offset [BX] 3 bits right; 0’s in 3 MSBs
 Branching
Instructions
JMP
• JMP label
• JMP BX
• JMP [BX]
JA / JNBE
(JUMP IF ABOVE / JUMP IF NOT BELOW OR EQUAL)

CMP AX, 4371H ; Compare by subtracting 4371H from AX

JA NEXT ;Jump to label NEXT if AX above 4371H

CMP AX, 4371H ;Compare (AX – 4371H)

JNBE NEXT ;Jump to label NEXT if AX not below or equal
to 4371H
JAE /(JUMP
JNBIF ABOVE
/ JNC OR EQUAL / JUMP IF NOT BELOW / JUMP IF NO CARRY)

CMP AX, 4371H ;Compare (AX – 4371H)

JAE NEXT ;Jump to label NEXT if AX above 4371H

CMP AX, 4371H ;Compare (AX – 4371H)

JNB NEXT ;Jump to label NEXT if AX not below 4371H

ADD AL, BL ;Add two bytes

JNC NEXT ;If the result with in acceptable range, continue

JB / JC / JNAE
(JUMP IF BELOW / JUMP IF CARRY / JUMP IF NOT ABOVE OR EQUAL)

CMP AX, 4371H ;Compare (AX – 4371H)

JB NEXT ;Jump to label NEXT if AX below 4371H

ADD BX, CX ;Add two words

JC NEXT ;Jump to label NEXT if CF = 1

CMP AX, 4371H ;Compare (AX – 4371H)

JNAE NEXT ;Jump to label NEXT if AX not above or equal to

4371H
JBE / (JUMP
JNAIF BELOW OR EQUAL / JUMP IF NOT ABOVE)

CMP AX, 4371H ;Compare (AX – 4371H)

JBE NEXT ;Jump to label NEXT if AX is below or equal to
4371H

CMP AX, 4371H ;Compare (AX – 4371H)

JNA NEXT ;Jump to label NEXT if AX not above 4371H

JG / JNLE
(JUMP IF GREATER / JUMP IF NOT LESS THAN OR EQUAL)

CMP BL, 39H ;Compare by subtracting 39H from BL

JG NEXT ;Jump to label NEXT if BL more positive than 39H

CMP BL, 39H ;Compare by subtracting 39H from BL

JNLE NEXT ;Jump to label NEXT if BL is not less than or equal

to 39H
JGE / (JUMP
JNLIF GREATER THAN OR EQUAL / JUMP IF NOT LESS THAN)

CMP BL, 39H ;Compare by subtracting 39H from BL

JGE NEXT ;Jump to label NEXT if BL more positive than or equal to
39H

CMP BL, 39H ;Compare by subtracting 39H from BL

JNL NEXT ;Jump to label NEXT if BL not less than 39H

JL / JNGE
(JUMP IF LESS THAN / JUMP IF NOT GREATER THAN OR EQUAL)

CMP BL, 39H Compare by subtracting 39H from BL

JL AGAIN Jump to label AGAIN if BL more negative than 39H

CMP BL, 39H Compare by subtracting 39H from BL

JNGE AGAIN Jump to label AGAIN if BL not more positive than or
equal to 39H
 JLE / JNG
(JUMP IF LESS THAN OR EQUAL / JUMP IF NOT GREATER)

CMP BL, 39H Compare by subtracting 39H from BL

JLE NEXT Jump to label NEXT if BL more negative than or equal to
39H

CMP BL, 39H Compare by subtracting 39H from BL

JNG NEXT Jump to label NEXT if BL not more positive than 39H
 JE / JZ
(JUMP IF EQUAL / JUMP IF ZERO)

CMP BX, DX Compare (BX-DX)

JE DONE Jump to DONE if BX = DX

IN AL, 30H Read data from port 8FH

SUB AL, 30H Subtract the minimum value.
JZ START Jump to label START if the result of subtraction is 0
JNE / JNZ
(JUMP NOT EQUAL / JUMP IF NOT ZERO)

IN AL, 0F8H Read data value from port

CMP AL, 72 Compare (AL –72)
JNE NEXT Jump to label NEXT if AL != 72

ADD AX, 0002H Add count factor 0002H to AX

DEC BX Decrement BX
JNZ NEXT Jump to label NEXT if BX != 0
JS (JUMP IF SIGNED / JUMP IF NEGATIVE)

ADD BL, DH Add signed byte in DH to signed byte in DL

JS NEXT Jump to label NEXT if result of addition is negative number

JNS
(JUMP IF NOT SIGNED / JUMP IF POSITIVE)

DEC AL Decrement AL
JNS NEXT Jump to label NEXT if AL has not decremented to FFH
JP / JPE
(JUMP IF PARITY / JUMP IF PARITY EVEN)

IN AL, 0F8H Read ASCII character from Port F8H

OR AL, AL Set flags
JPE ERROR Odd parity expected, send error message if parity found
even
JNP / JPO
(JUMP IF NO PARITY / JUMP IF PARITY ODD)

IN AL, 0F8H Read ASCII character from Port F8H

OR AL, AL Set flags
JPO ERROR Even parity expected, send error message if parity found odd
JO
(JUMP IF OVERFLOW)

ADD AL, BL Add signed bytes in AL and BL

JO ERROR Jump to label ERROR if overflow from add
JNO
(JUMP IF NO OVERFLOW)

ADD AL, BL Add signed byte in AL and BL

JNO DONE Process DONE if no overflow
JCXZ
(JUMP IF THE CX REGISTER IS ZERO)

JCXZ SKIP If CX = 0, skip the process

SUB [BX], 07H Subtract 7 from data value
SKIP: ADD AX,DX Next instruction
LOOP
(JUMP TO SPECIFIED LABEL IF CX != 0 AFTER AUTO DECREMENT)

This instruction is used to repeat a series of instructions some

number of times. The number of times the instruction sequence is to
be repeated is loaded into CX. Each time the LOOP instruction
executes, CX is automatically decremented by 1. If CX is not 0,
execution will jump to a destination specified by a label in the
instruction. If CX = 0 after the auto decrement, execution will simply
go on to the next instruction after LOOP. The destination address for
the jump must be in the range of –128 bytes to +127 bytes from the
address of the instruction after the LOOP instruction. This instruction
does not affect any flag.
Example

MOV BX, OFFSET PRICES Point BX at first element in array

MOV CX, 40 Load CX with number of elements in array
NEXT: MOV AL, [BX] Get element from array
INC AL Increment the content of AL
MOV [BX], AL Put result back in array
INC BX Increment BX to point to next location
LOOP NEXT Repeat until all elements adjusted
LOOPE / LOOPZ
(LOOP WHILE CX != 0 AND ZF = 1)

•This instruction is used to repeat a group of instructions some number of

times, or until the zero flag becomes 0. The number of times the
instruction sequence is to be repeated is loaded into CX.

•Each time the LOOP instruction executes, CX is automatically decremented

by 1. If CX != 0 and ZF = 1, execution will jump to a destination specified by
a label in the instruction.

• If CX = 0, execution simply go on the next instruction after LOOPE /

LOOPZ. In other words, the two ways to exit the loop are CX = 0 or ZF = 0.

•The destination address for the jump must be in the range of –128 bytes
to +127 bytes from the address of the instruction after the LOOPE / LOOPZ
instruction. This instruction does not affect any flag.
Example

MOV BX, OFFSET ARRAY Point BX to address of ARRAY before start of array
DEC BX Decrement BX
MOV CX, 100 Put number of array elements in CX
NEXT: INC BX Point to next element in array
CMP [BX], OFFH Compare array element with FFH
LOOPE NEXT
LOOPNE / LOOPNZ
(LOOP WHILE CX != 0 AND ZF = 0)

•This instruction is used to repeat a group of instructions some number

of times, or until the zero flag becomes a 1. The number of times the
instruction sequence is to be repeated is loaded into the count register
CX.

• Each time the LOOPNE / LOOPNZ instruction executes, CX is

automatically decremented by 1. If CX ! = 0 and ZF = 0, execution will
jump to a destination specified by a label in the instruction. If CX = 0,
after the auto decrement or if ZF = 1, execution simply go on the next
instruction after LOOPNE / LOOPNZ.

•In other words, the two ways to exit the loop are CX = 0 or ZF = 1. The
destination address for the jump must be in the range of –128 bytes to
+127 bytes from the address of the instruction after the LOOPNE /
LOOPZ instruction. This instruction does not affect any flags.
Example

MOV BX, OFFSET ARRAY Point BX to adjust before start of array

DEC BX Decrement BX
MOV CX, 100 Put number of array in CX
NEXT: INC BX Point to next element in array
CMP [BX], ODH Compare array element with 0DH
LOOPNZ NEXT
CALL
• Near Call
• Decrement SP and saves the address of next instruction (IP)
• Far Call
• Decrement SP and Saves the content of CS and Again decrement the SP
and saves the address of next instruction after the call.
Examples
• CALL Mult
• CALL BX
• CALL WORD PTR [BX]
RET
• Near :
• It will get back value of IP from the stack.
• Far :
• It will get back value of IP and CS from the stack.
String Manipulation Instructions
MOVSB No operands
MOVSW No operands

This instruction copies a byte or a word from location in the data segment
to a location in the extra segment. The offset of the source in the data
segment must be in the SI register. The offset of the destination in the
extra segment must be in the DI register. For multiple-byte or
multiple-word moves, the number of elements to be moved is put in the
CX register so that it can function as a counter. After the byte or a word is
moved, SI and DI are automatically adjusted to point to the next source
element and the next destination element. If DF is 0, then SI and DI will
incremented by 1 after a byte move and by 2 after a word move. If DF is
1, then SI and DI will be decremented by 1 after a byte move and by 2
after a word move. MOVS does not affect any flag.
Example

MOV SI, OFFSET SOURCE Load offset of start of source string in

DS into SI
MOV DI, OFFSET DESTINATION Load offset of start of destination string
in ES into DI
CLD Clear DF to auto increment SI and DI
after move
MOV CX, 04H Load length of string into CX as counter
REP MOVSB Move string byte until CX = 0
LODSB No operands
LODSW No operands
(LOAD STRING BYTE INTO AL OR STRING WORD INTO AX)
This instruction copies a byte from a string location
pointed to by SI to AL, or a word from a string location
pointed to by SI to AX. If DF is 0, SI will be automatically
incremented (by 1 for a byte string, and 2 for a word
string) to point to the next element of the string. If DF is 1,
SI will be automatically decremented (by 1 for a byte
string, and 2 for a word string) to point to the previous
element of the string. LODS does not affect any flag.

CLD Clear direction flag so that SI is auto-incremented

MOV SI, OFFSET SOURCE Point SI to start of string
LODS Copy a byte or a word from string to AL or AX
 STOSB No operands
STOSW No operands
(STORE STRING BYTE OR STRING WORD)
This instruction copies a byte from AL or a word from AX to a
memory location in the extra segment pointed to by DI. In
effect, it replaces a string element with a byte from AL or a
word from AX. After the copy, DI is automatically
incremented or decremented to point to next or previous
element of the string. If DF is cleared, then DI will
automatically incremented by 1 for a byte string and by 2 for
a word string. If DI is set, DI will be automatically
decremented by 1 for a byte string and by 2 for a word
string. STOS does not affect any flag.
Example

MOV DI, OFFSET TARGET

STOW

MOV DI, OFFSET TARGET

STOSB
REP / REPE / REPZ / REPNE / REPNZ (PREFIX)
(REPEAT STRING INSTRUCTION UNTIL SPECIFIED CONDITIONS
EXIST)

REP is a prefix, which is written before one of the string instructions. It

will cause the CX register to be decremented and the string instruction
to be repeated until CX = 0. The instruction REP MOVSB, for example,
will continue to copy string bytes until the number of bytes loaded into
CX has been copied.

REPE and REPZ are two mnemonics for the same prefix. They stand for
repeat if equal and repeat if zero, respectively. They are often used with
the Compare String instruction or with the Scan String instruction. They
will cause the string instruction to be repeated as long as the compared
bytes or words are equal (ZF = 1) and CX is not yet counted down to zero.
In other words, there are two conditions that will stop the repetition: CX =
0 or string bytes or words not equal.
REP / REPE / REPZ / REPNE / REPNZ (PREFIX)
(REPEAT STRING INSTRUCTION UNTIL SPECIFIED CONDITIONS
EXIST)

REPNE and REPNZ are also two mnemonics for the same prefix.
They stand for repeat if not equal and repeat if not zero, respectively.
They are often used with the Compare String instruction or with the Scan
String instruction. They will cause the string instruction to be repeated as
long as the compared bytes or words are not equal (ZF = 0) and CX is not
yet counted down to zero.

REPE CMPSB Compare string bytes until end of string or until string bytes
not equal.
REPNE SCASW Scan a string of word until a word in the string matches
the word in AX or until all of the string has been scanned.
CMPSB No Operands
CMPSW No Operands
(COMPARE STRING BYTES OR STRING WORDS)
This instruction can be used to compare a byte / word in one string with
a byte / word in another string. SI is used to hold the offset of the byte
or word in the source string, and DI is used to hold the offset of the byte
or word in the destination string.

The flags are affected by the comparison, but the two operands are not
affected. After the comparison, SI and DI will automatically be
incremented or decremented to point to the next or previous element
in the two strings. If DF is set, then SI and DI will automatically be
decremented by 1 for a byte string and by 2 for a word string. If DF is
reset, then SI and DI will automatically be incremented by 1 for byte
strings and by 2 for word strings
Example

MOV SI, OFFSET FIRST Point SI to source string

MOV DI, OFFSET SECOND Point DI to destination string
CLD DF cleared, SI and DI will auto-increment after
compare
MOV CX, 100 Put number of string elements in CX
REPE CMPSB Repeat the comparison of string bytes until end of
string or until compared bytes are not equal
SCASB / SCASW (SCAN A STRING BYTE OR A
STRING WORD)
SCAS compares a byte in AL or a word in AX with a byte or a word in ES
pointed to by DI. Therefore, the string to be scanned must be in the extra
segment, and DI must contain the offset of the byte or the word to be
compared. If DF is cleared, then DI will be incremented by 1 for byte
strings and by 2 for word strings. If DF is set, then DI will be decremented
by 1 for byte strings and by 2 for word strings. SCAS affects AF, CF, OF, PF,
SF, and ZF, but it does not change either the operand in AL (AX) or the
operand in the string.
Example
The following program segment scans a text string of 80
characters for a carriage return, 0DH, and puts the offset of
string into DI:

MOV DI, OFFSET STRING

MOV AL, 0DH Byte to be scanned for into AL
MOV CX, 80 CX used as element counter
CLD Clear DF, so that DI auto increments
REPNE SCAS Compare byte in string with byte in AL
Flag Manipulation
Instructions
STC (SET CARRY FLAG)
This instruction sets the carry flag to 1. It does not affect any other flag.

CLC (CLEAR CARRY FLAG)

This instruction resets the carry flag to 0. It does not affect any other
flag.

CMC (COMPLEMENT CARRY FLAG)

This instruction complements the carry flag. It does not affect any other
flag.

STD (SET DIRECTION FLAG)

This instruction sets the direction flag to 1. It does not affect any other
flag.

CLD (CLEAR DIRECTION FLAG)

This instruction resets the direction flag to 0. It does not affect any
other flag.
STI (SET INTERRUPT FLAG)
Setting the interrupt flag to a 1 enables the INTR interrupt input of the 8086

CLI (CLEAR INTERRUPT FLAG)

This instruction resets the interrupt flag to 0. If the interrupt flag is reset, the
8086 will not respond to an interrupt signal on its INTR input.

LAHF (Copy Low Byte Of Flag Register To AH Register)

The LAHF instruction copies the low-byte of the 8086 flag register to AH
register. It can then be pushed onto the stack along with AL by a PUSH AX
instruction. LAHF does not affect any flag.

SAHF (Copy AH Register To Low Byte Of Flag Register)

The SAHF instruction replaces the low-byte of the 8086 flag register with a
byte from the AH register. SAHF changes the flags in lower byte of the flag
register.
Stack Related
Instructions
PUSH – PUSH Source
The PUSH instruction decrements the stack pointer by 2 and
copies a word from a specified source to the location in the
stack segment to which the stack pointer points. The source
of the word can be general-purpose register, segment
register, or memory. The stack segment register and the
stack pointer must be initialized before this instruction can
be used. PUSH can be used to save data on the stack so that
it will not destroyed by a procedure. This instruction does
not affect any flag.
Example

PUSH BX Decrement SP by 2, copy BX to stack.

PUSH DS Decrement SP by 2, copy DS to stack.

PUSH BL Illegal; must push a word

PUSH TABLE [BX] Decrement SP by 2, and copy word from memory in DS

at EA = TABLE + [BX] to stack
POP – POP Destination

The POP instruction copies a word from the stack location

pointed to by the stack pointer to a destination specified
in the instruction. The destination can be a
general-purpose register, a segment register or a memory
location. The data in the stack is not changed. After the
word is copied to the specified destination, the stack
pointer is automatically incremented by 2 to point to the
next word on the stack. The POP instruction does not
affect any flag.
Examples

POP DX Copy a word from top of stack to DX; increment SP by 2

POP DS Copy a word from top of stack to DS; increment SP by 2

POP TABLE [DX] Copy a word from top of stack to memory in DS with
EA = TABLE + [BX]; increment SP by 2.
PUSHF (PUSH FLAG REGISTER TO STACK)
The PUSHF instruction decrements the stack pointer by 2
and copies a word in the flag register to two memory
locations in stack pointed to by the stack pointer. The stack
segment register is not affected. This instruction does to
affect any flag.

POPF (POP WORD FROM TOP OF STACK TO

FLAG REGISTER)
The POPF instruction copies a word from two memory
locations at the top of the stack to the flag register and
increments the stack pointer by 2. The stack segment
register and word on the stack are not affected. This
instruction does to affect any flag.
INPUT / OUTPUT
Instruction
IN – IN Accumulator, Port
The IN instruction copies data from a port to the AL or AX
register. If an 8-bit port is read, the data will go to AL. If a
16-bit port is read, the data will go to AX.

IN AL, OC8H Input a byte from port OC8H to AL

IN AX, 34H Input a word from port 34H to AX

MOV DX, 0FF78H Initialize DX to point to port

IN AL, DX Input a byte from 8-bit port 0FF78H to AL
IN AX, DX Input a word from 16-bit port 0FF78H to AX
OUT – OUT Port, Accumulator

The OUT instruction copies a byte from AL or a word from

AX to the specified port. The OUT instruction has two
possible forms, fixed port and variable port.

OUT 3BH, AL Copy the content of AL to port 3BH

OUT 2CH, AX Copy the content of AX to port 2CH

MOV DX, 0FFF8H Load desired port address in DX

OUT DX, AL Copy content of AL to port FFF8H
OUT DX, AX Copy content of AX to port FFF8H
Miscellaneous Instructions
• HLT (HALT PROCESSING)
• NOP (PERFORM NO OPERATION)
• ESC (ESCAPE)
• This instruction is used to pass instructions to a coprocessor, such as the
8087 Math coprocessor, which shares the address and data bus with 8086.
• INT – INT TYPE
1. Decrement the stack pointer by 2 and push the flags on to the stack.

2. Decrement the stack pointer by 2 and push the content of CS onto the stack.

3. Decrement the stack pointer by 2 and push the offset of the next instruction after
the INT number instruction on the stack.

4. Get a new value for IP from an absolute memory address of 4 times the type
specified in the instruction. For an INT 8 instruction, for example, the new IP will be
read from address 00020H.

5. Get a new for value for CS from an absolute memory address of 4 times the type
specified in the instruction plus 2, for an INT 8 instruction, for example, the new
value of CS will be read from address 00022H.

6. Reset both IF and TF. Other flags are not affected.

INT 35 New IP from 0008CH, new CS from 0008Eh

INT 3 Get new IP from 0000CH new CS from 0000EH

 INTO (INTERRUPT ON OVERFLOW)
If the overflow flag (OF) is set, this instruction causes the 8086 to do an indirect
far call to a procedure you write to handle the overflow condition. Before doing
the call, the 8086 will

1. Decrement the stack pointer by 2 and push the flags on to the stack.

2. Decrement the stack pointer by 2 and push CS on to the stack.

3. Decrement the stack pointer by 2 and push the offset of the next instruction
after INTO instruction onto the stack.

4. Reset TF and IF. Other flags are not affected. To do the call, the 8086 will read
a new value for IP from address 00010H and a new value of CS from address
00012H.
IRET (INTERRUPT RETURN)
When the 8086 responds to an interrupt signal or to an interrupt
instruction, it pushes the flags, the current value of CS, and the
current value of IP onto the stack. It then loads CS and IP with the
starting address of the procedure, which you write for the response
to that interrupt.

The IRET instruction is used at the end of the interrupt service

procedure to return execution to the interrupted program. To do this
return, the 8086 copies the saved value of IP from the stack to IP, the
stored value of CS from the stack to CS, and the stored value of the
flags back to the flag register.
Assembler Directive
• Data Defining Directives:
• DB:
• The DB directive is used to declare a byte type variable, or a
set aside one or more storage locations of type byte in
memory.
• Syntax
• Name DB data1,data2,data3
• Here data can be any numeric value in hexadecimal,
decimal , binary or ? Symbol for variables that are not
initialized.
Examples
PRICES DB 49H, 98H, 29H Declare array of 3 bytes named PRICE and initialize them with
specified values.

NAME DB “THOMAS” Declare array of 6 bytes and initialize with ASCII codes for the
letters in THOMAS.

TEMP DB 100 DUP (?) Set aside 100 bytes of storage in memory and give it the name
TEMP. But leave the 100 bytes un-initialized.

PRESSURE DB 20 DUP (0) Set aside 20 bytes of storage in memory, give it the name
PRESSURE and put 0 in all 20 locations.
• DW:
• The DW directive is used to tell the assembler to define a variable of
type word or to reserve storage locations of type word in memory. The
statement MULTIPLIER DW 437AH, for example, declares a variable of
type word named MULTIPLIER, and initialized with the value 437AH
when the program is loaded into memory to be run.
• Syntax:
• Name DW Word1,Word2,Word3
Example
WORDS DW 1234H, 3456H Declare an array of 2 words and initialize them with the
specified values.

STORAGE DW 100 DUP (0) Reserve an array of 100 words of memory and initialize all
100 words with 0000. Array is named as STORAGE.

STORAGE DW 100 DUP (?) Reserve 100 word of storage in memory and give it the
name STORAGE, but leave the words un-initialized.
• DD (DEFINE DOUBLE WORD) :
• The DD directive is used to declare a variable of type double word or to
reserve memory locations, which can be accessed as type double word.
The statement ARRAY DD 25629261H, for example, will define a double
word named ARRAY and initialize the double word with the specified
value when the program is loaded into memory to be run.
• Syntax:
• Name DD Double word1, Double word2, Double word3

MEM DD 456D0F35, ?
• DQ (Define quad words):
• DQ directive is used to allocate and initialize one or more
quad words (8 bytes) of data.
• Syntax:
• Name DQ Quad word1, Quad word2
• DT (Define 10 Bytes):
• This directive allocates and optionally initialize 10 bytes of data.
• Syntax:
• Name DT value1, value2
PTR(Pointer)
• The pointer operator is used to declare the type of a label,
variable or memory operand. The operator PTR is prefixed by
either BYTE or WORD. If the prefix is BYTE, then the particular
label, variable or memory operand is treated as an 8-bit
quantity, while if WORD is the prefix, then it is treated as a 16-
bit quantity. In other words, the PTR operator is used to
specify the data type -byte or word.
Example
• MOV AL, BYTE PTR [SI] ;Moves content of memory
locationaddressed by SI (8-bit) to AL
• INC BYTE PTR [BX] ;Increments byte contents of memory
location addressed by BX
• MOV BX, WORD PTR [2000H] ; Moves 16-bit content of
memory location 2000H to BX, i.e. [2000H] to BL [2001 H] to
BH
• INC WORD PTR [3000H] Increments word contents of
memory location 3000H considering contents of 3000H
(lower byte) and 3001 H (higher byte) as a 16-bit number
? (Uninitialized value)
• It is used as an initializer in data declarations. It
indicates the value that the assembler allocates but
does not initialize. It can used alone or with DUP
operator.

• Example:
• MEM DW ?
• Mem-2 DB ?,?,?
• Mem-3 DB 20 DUP(?)
OFFSET
• OFFSET directive is used to load the offset of memory location
to the pointer register.

MEM1 DB 21

MOV SI, offset MEM1

MOV SI,MEM1
EQU
• EQU is used to give a name to some value or symbol. Each time the
assembler finds the given name in the program, it replaces the name with
the value or symbol you equated with that name. Suppose, for example,
you write the statement FACTOR EQU 03H at the start of your program,
and later in the program you write the instruction statement ADD AL,
FACTOR. When the assembler codes this instruction statement, it will code
it as if you had written the instruction ADD AL, 03H.

CONTROL EQU 11000110 B Replacement

MOV AL, CONTROL Assignment

DECIMAL_ADJUST EQU DAA Create clearer mnemonic for DAA

ADD AL, BL Add BCD numbers

DECIMAL_ADJUST Keep result in BCD format
DUP(Duplicate)
• The DUP directive can be used to initialized several
locations and to assign value to those locations.
• Syntax:
• Name Data type num DUP (Initialized value)
• Table DW 10 DUP(0)
EVEN
• The EVEN directive aligns the next variable or instruction on
even offset address.

ORG
⚫ ORG directive is used to begin an
assembly language program at specific
offset address.
⚫ ORG 1000H
Segment defining directives
• ASSUME: Assume Logical Segment Name
• The ASSUME directive is used to inform the assembler, the names
of the logical segments to be assumed for different segments used
in the program. In the assembly language program, each segment is
given a name. For example, the code segment may be given the
name CODE, data segment may be given the name DATA etc.
• The statement ASSUME CS : CODE directs the assembler that the
machine codes are available in a segment named CODE, and hence
the CS register is to be loaded with the address (segment) allotted
by the operating system for the label CODE.
ENDS: END of Segment
• This directive marks the end of a logical segment.
The logical segments are assigned with the names
using the ASSUME directive.
DATA SEGMENT
.
.
.
DATA ENDS
ASSUME CS: CODE, DS:DATA
CODE SEGMENT.
.
.
.
CODE ENDS
END
END: END of Program
• The END directive marks the end of an assembly
language program. When the assembler comes
across this END directive, it ignores the source lines
available later on. Hence, it should be ensured that
the END statement should be the last statement in
the file and should not appear in between.
Write a program to ADD two 16 bit numbers.

DATA SEGMENT
NUM DW 1234H, 0F234H
SUM DW 2 DUP(0)
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV AX,NUM ; First number loaded into AX
MOV BX,0H ; For carry BX register is cleared
ADD AX,NUM+2 ; Second number added with AX
JNC DOWN ; Check for carry
INC BX ; If carry generated increment the BX
DOWN: MOV SUM,AX ; Storing the sum value
MOV SUM+2,BX ; Storing the carry value
MOV AH,4CH
INT 21H
CODE ENDS INPUT : 1234H, F234H
END START OUTPUT : 10468H
 Write a program to ADD two 32 bit numbers.
DATA SEGMENT Move LSB of NUM1 to AX
NUM1 DW 0FFFFH,0FFFFH ;Add LSB of NUM2 to AX
NUM2 DW 1111H,1111H ;Store the LSB in SUM
SUM DW 4 DUP(0) ; Move MSB of NUM1 to AX
DATA ENDS ; Add MSB of NUM2 to AX
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX INPUT: 0FFFFFFFFH, 011111111H
MOV AX,NUM1
OUTPUT: 0111111110H
ADD AX,NUM2
MOV SUM,AX
MOV AX,NUM1+2
ADC AX,NUM2+2
JNC DOWN ; Check for carry
MOV SUM+4,01H
DOWN: MOV SUM+2,AX
MOV AH,4CH
INT 21H
CODE ENDS
END START
Write a program to multiply two 16 bit numbers.
DATA SEGMENT
NUM DW 1234H,1234H
PROD DW 2 DUP(0)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
LEA SI, NUM ; SI pointed to the Multiplicand
MOV AX,[SI] ; Multiplicand has to be in AX register
MOV BX,[SI+2] ; SI+2 pointed to the Multiplier and move it
to BX
MUL BX ;Perform the multiplication
MOV PROD,AX ;32 bit product stored in DX-AX registers
MOV PROD+2,DX
MOV AH,4CH
INT 21H
CODE ENDS
END START
Write a program to find factorial of a number.
DATA SEGMENT
X DW 06H
FACT DW ?
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV AX,01H
MOV CX,X
UP: MUL CX
LOOP UP
MOV FACT,AX
MOV AH,4CH
INT 21H
CODE ENDS
END START
Input: 06
Output: 2D0H
Write a program to find given number is positive or negative.
DATA SEGMENT
NUM DB 12H
MES1 DB “DATA IS POSITIVE $”
MES2 DB “DATA IS NEGATIVE $”
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV AL,NUM
ROL AL,1
JC NEGA
MOV DX,OFFSET MES1 ;Declare it positive.
JMP EXIT ;Exit program.
NEGA: MOV DX,OFFSET MES2;Declare it negative.
EXIT: MOV AH,09H ; Write a $ Terminated string.
INT 21H
MOV AH,4CH ; Terminate the process
INT 21H
CODE ENDS
END START
Write a program to find given number even or odd.
DATA SEGMENT
X DB 27H
MSG1 DB “NUMBER IS EVEN$”
MSG2 DB “NUMBER IS ODD$”
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV AX,X
TEST AX,01H
JNZ EXIT
LEA DX,MSG1
MOV AH,09H
INT 21H
JMP LAST
EXIT: LEA DX,MSG2 ;Declare it is Odd number.
MOV AH,09H
INT 21H
LAST: MOV AH,4CH
INT 21H
CODE ENDS
END START
Write a program to transfer given string from one
location to another.
DATA SEGMENT
STR1 DB “HOW ARE YOU”
STR2 DB 20 DUP(0)
DATA ENDS

CODE SEGMENT
ASSUME CS:CODE,DS:DATA,ES:DATA
START: MOV AX,DATA
MOV DS,AX
MOV ES,AX
LEA SI,STR1
LEA DI,STR2
MOV CX, lengthof STR1
CLD
REP MOVSB
MOV AH,4CH
INT 21H
CODE ENDS
END START
 Interrupts
• Interrupt Types
• Hardware Interrupts: External event
• Software Interrupts: Internal event (Software generated)
• Maskable and non-maskable interrupts
• Interrupt priority
• Interrupt Vectors and Interrupt Handlers
Purpose of Interrupts
• Interrupts are useful when interfacing I/O devices with low
data-transfer rates, like a keyboard or a mouse, in which case polling
the device wastes valuable processing time
• The peripheral interrupts the normal application execution,
requesting to send or receive data.
• The processor jumps to a special program called Interrupt Service
Routine to service the peripheral
• After the processor services the peripheral, the execution of the
interrupted program continues.
 BASIC INTERRUPT TERMINOLOGY
• Interrupt Service Routine (ISR) or Interrupt handler: code used
for handling a specific interrupt
• Interrupt priority: In systems with more than one interrupt
inputs, some interrupts have a higher priority than other
• They are serviced first if multiple interrupts are triggered simultaneously
• Interrupt vector: Code loaded on the bus by the interrupting
device that contains the Address (segment and offset) of
specific interrupt service routine
• Interrupt Masking: Ignoring (disabling) an interrupt
• Non-Maskable Interrupt: Interrupt that cannot be ignored
(power-down)
•Interrupt V/S Polling
Types of Interrupts
 Procedure when interrupt arrives
1. It decremented SP by 2 and pushes Flag register on the stack.
2. It disables 8086 INTR input by clearing IF flag in Flag register
3. It resets the TF (trap) flag in Flag register
4. It decremented SP again by 2 and pushes current CS contents
on the stack.
5. It decremented SP again by 2 and pushes current IP contents
on the stack.
6. It does an indirect far jump to the start of the procedure
written to respond to the interrupt.
 How does 8086 get the address of a particular ISR?

In an 8086 system, each “interrupter” has an id#

–8086 treat this id# as interruption type#
–after receiving INTR signal, 8086 sends an INTA signal
–after receiving INTA signal, interrupter releases it’s id#,
i.e., type# of the interruption.
8086 multiplies this id# or type# by 4 to produced the
desired address in the vector table

8086 reads 4 bytes of memory starting from this

address to get the starting address of ISR
• lower 2 byte is loaded in to IP
• higher 2 bytes to CS