8086 MICROPROCESSOR
Overview
The 8086("eighty eighty-six", also called iAPX
86) is a 16-bit microprocessor chip designed
by Intel between early 1976 and mid-1978, when it
was released
Having Data Bus of 16 bit
Clock Frequencies of 5,8 &10 MHz
Can Address up to 1 Mbytes of Memory
It has more than 20,000 instructions
Provides fourteen 16-Bit registers
Overview cont.……
The 8086 gave rise to the x86 architecture which
eventually became Intel's most successful line of
processors
EU & BIU
The 8086 CPU logic has been partitioned into two
functional units namely Bus Interface Unit (BIU)
and Execution Unit (EU)
The major reason for this separation is to increase
the processing speed of the processor
The BIU has to interact with memory and
input/output devices in fetching the instructions
and data required by the EU
EU is responsible for executing the instructions of
the programs and to carry out the required
processing
8086 Architecture
Execution Unit
The Execution Unit (EU) has
Control unit
Arithmetic and Logical Unit (ALU)
General registers
Flag register
Pointers
Index registers
Control unit isresponsible for the co-ordination of all
other units of the processor
ALU performs various arithmetic and logical
operations over the data
General registers are used for temporary storage and
manipulation of data and instructions
Accumulator register consists of two 8-bit registers
AL and AH, which can be combined together and
used as a 16-bit register AX
Accumulator can be used for I/O operations and
string manipulation
Base register consists of two 8-bit registers BL and
BH, which can be combined together and used as a
16-bit register BX
BX register usually contains a data pointer used for
based indexed or register indirect addressing. Similar
to 8085 H-L register.
Count register consists of two 8-bit registers CL and
CH, which can be combined together and used as a
16-bit register CX
Count register can be used as a counter in string
manipulation and shift/rotate instructions
Data register consists of two 8-bit
registers DL and DH, which can be
combined together and used as a 16-bit
register DX
Data register can be used to hold 16 bit
result
Stack Pointer (SP) is a 16-bit register pointing to
program stack
Base Pointer (BP) is a 16-bit register pointing to data in
stack segment. BP register is usually used for based,
based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for
indexed, based indexed and register indirect addressing,
as well as a source data addresses in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for
indexed, based indexed and register indirect addressing,
as well as a destination data addresses in string
manipulation instructions.
BIU
INSTRUCTION STREAM BYTE QUEUE
It is of 6 Bytes.
To increase the execution speed, BIU fetches as
many as six instruction bytes ahead to time from
memory.
It operates on the principle first in first out (FIFO).
Then all bytes are given to EU one by one.
Therefore fetch and execution are taking place
concurrently in order to improve the performance
of the microprocessor
The BIU feeds the instruction stream to the
execution unit through a 6 byte pre fetch
queue
Segment Registers
The memory of 8086 is divided into 4
segments namely
Code segment (program memory)
Data segment (data memory)
Stack memory (stack segment)
Extra memory (extra segment)
Code Segment (CS) register is a 16-bit register
containing address of 64 KB segment with
processor instructions
The processor uses CS segment for all accesses to
instructions referenced by instruction pointer
(IP) register
Stack Segment (SS) register is a 16-bit register
containing address of 64KB segment with
program stack
By default, the processor assumes that all data
referenced by the stack pointer (SP) and base
pointer (BP) registers is located in the stack
segment
Data Segment (DS) register is a 16-bit register
containing address of 64KB segment with
program data
By default, the processor assumes that all data
referenced by general registers (AX, BX, CX,
DX) and index register (SI, DI) is located in the
data segment
Extra Segment (ES) register is a 16-bit register
containing address of 64KB segment, usually with
program data
By default, the processor assumes that the DI
register references the ES segment in string
manipulation instructions
The Instruction Pointer (IP) in 8086 acts as
a Program Counter.
It points to the address of the next
instruction to be executed.
Its content is automatically incremented
when the execution of a program
proceeds further.
The contents of the IP and Code Segment
Register are used to compute the memory
address of the instruction code to be
fetched.
This is done during the Fetch Cycle.
They are each 16 bits long and has 216 or 64 KB
addresses
Different kinds of segment registers are used to
calculate the address within the 1MB memory
space
Given code segment cs=1234H and IP=05678H
how do we get memory physical address
Status Flags
Status Flags determines the current state of the
accumulator.
They are modified automatically by CPU after
mathematical operations.
This allows to determine the type of the result.
8086 has 16-bit status register.
It is also called Flag Register or Program Status
Word (PSW).
There are nine status flags and seven bit
positions remain unused.
Status Flags
Pin Diagram of 8086
AD15-AD0: These are the time multiplexed memory I/O
address and data lines.
AD0 – AD7 carries lower order byte
AD8 – AD15 carries higher order bytes
During the first clock cycle it is carries 16 bit address and after
that it carries 16 bit data
A19/S6,A18/S5,A17/S4,A16/S3: These are the time
multiplexed address and status lines.
During first clock cycle, it carries 4 – bits address and later it
carries status signals
The S4 and S3 combination indicates which segment register is
presently being used for memory accesses.
S7 / BHE
Stands for Bus High Enable
It is available at pin 34 and used to indicate the
transfer of data using D8 – D15. This signal is low
during the first clock cycle, thereafter it is active.
RD: This signal on low indicates the peripheral
that the processor is performing memory or
I/O read operation.
READY: This is the acknowledgement from the
slow device or memory that they have
completed the data transfer.
INTR-Interrupt Request: This is a triggered
input. If any interrupt request is pending, the
processor enters the interrupt acknowledge
cycle. This can be internally masked by resulting
the interrupt enable flag. This signal is active
high and internally synchronized.
TEST: This input is examined by a ‘WAIT’
instruction. If the TEST pin goes low, execution
will continue, else the processor remains in an
idle state
CLK- Clock Input: The clock input provides the
basic timing for processor operation and bus
control activity.
MN/MX: The logic level at this pin decides
whether the processor is to operate in either
minimum or maximum mode.
Maximum and Minimum modes
The 8086 microprocessor can be configured to work
in either of the two modes
Minimum mode MN/MX =1
Maximum mode MN/MX =0
Minimum mode
Single processor mode : no additional processor
can be connected
8086 is responsible for generating all control
signals for memory and I/O
Used to design simple applications
Maximum and Minimum modes
Maximum mode
Multiprocessor mode: additional processors can
be connected e.g. 8087 the arithmetic co-
processor
External bus controller responsible for
generating all control signals for memory and
I/O
Used for complex and large applications
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