AEC OnlineGoogle
AEC OnlineGoogle
net/publication/363291711
CITATIONS READS
3 2,555
2 authors:
All content following this page was uploaded by Syed Thouheed Ahmed on 16 September 2022.
K u m ar Raj a D R
Sy ed T h o u h eed A h m ed | Sy ed M u zam i l B ash a
ANALOG ELECTRONIC CIRCUITS
Principles and Fundamentals
First Edition
Kumar Raja D R
REVA University, Bengaluru, India
This book is sold subject to the condition that it shall not, by way of trade or otherwise, be lent, resold, hired out, or otherwise
circulated without the publisher's prior written consent in any form of binding or cover other than that in which it is published
and without a similar condition including this condition being imposed on the subsequent purchaser and without limiting the
rights under copyright reserved above, no part of this publication may be reproduced, stored in or introduced into retrieval
system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording and otherwise) without the
prior written permission of both the copyright owner and the above mentioned publisher of this book.
ISBN 978-93-5636-178-2
This edition is manufactured, printed and distributed in India and is authorised for sale in India, Bangladesh, Pakistan,
Nepal Sri Lanka and the Maldives.
Printed in India.
JOHN FORD
ELECTRONICS
Is clearly the winner of the dat
CONTENTS
i
Reverse Biased PN Junction Diode 5
Reverse Characteristics Curve for a Junction
Diode 6
Forward Biased PN Junction Diode 6
Forward Characteristics Curve for a Junction
Diode 7
Junction Diode Summary 7
Junction Diode Ideal and Real Characteristics
8
RECTIFIERS 8
INTRODUCTION 8
Characteristics of a Rectifier Circuit 9
CLASSIFICATION OF RECTIFIERS 11
HALF-WAVE RECTIFIER 11
Operation 12
DISADVANTAGES OF HALF-WAVE
RECTIFIER 12
FULL WAVE RECTIFIER 13
Advantages 16
Disadvantages 16
BIPOLAR JUNCTION TRANSISTOR 16
ii
INTRODUCTION 16
CONSTRUCTION OF BJT AND ITS
SYMBOLS 16
Bipolar Transistor Construction 17
TRANSISTOR CURRENT
COMPONENTS 18
Bipolar Transistor Configurations 19
COMMON-BASE CONFIGURATION 19
TRANSISTOR AS AN AMPLIFIER 21
Common-Emitter Configuration 21
Relationship analysis between α and β 23
COMMON – COLLECTOR CONFIGURATION
23
Limits of operation 24
BJT HYBRID MODEL 25
Z-parameters 25
Y-parameters 26
Hybrid parameters (h-parameters) 26
THE HYBRID MODEL FOR TWO
PORT 27
iii
Analysis of a Transistor amplifier circuit using h-
parameters 31
Current Gain or Current Amplification (Ai) 31
Input Impedance (Zi) 31
Voltage Gain or Voltage Gain
Amplification Factor(Av) 32
Output Admittance (Yo) 33
Voltage Amplification Factor(Avs) taking into
account the resistance (Rs) of the
source 33
Current Amplification (Ais) taking into account
the source Resistance(RS) 34
Operating Power Gain (AP) 34
NEED FOR TRANSISTOR BIASING: 34
DC LOAD LINE 35
AC LOAD LINE 36
STABILITY FACTOR (S) 37
Stability factor S’ and S’’ 37
METHODS OF TRANSISTOR BIASING 38
Fixed bias (base bias) 38
Merits 38
iv
Demerits 38
EMITTER-FEEDBACK BIAS 39
Merits 39
Demerits 39
COLLECTOR TO BASE BIAS OR
COLLECTOR FEED-BACK BIAS 40
Merits 41
Demerits 41
COLLECTOR –EMITTER FEEDBACK BIAS
41
VOLTAGE DIVIDER BIAS OR SELF BIAS
OR EMITTER BIAS 42
Merits 44
Demerits 44
v
By varying the value of Vgs 47
Varying the value of Vds holding
Vgs constant 47
When both Vgs and Vds is applied
48
CHARACTERISTICS OF N-CHANNEL
JFET 48
Drain Characteristics 49
PINCH OFF Region 49
BREAKDOWN REGION 49
TRANSFER
CHARACTERISTICS 50
DIFFERENCE BETWEEN Vp
AND Vgsoff 50
Why the gate to source junction of
a JFET be always reverse biased? 50
JFET PARAMETERS 51
THE FET SMALL SIGNAL MODEL 51
MOSFET 52
CONSTRUCTION OF AN N-
CHANNEL MOSFET 53
DEPLETION MOSFET 53
vi
Depletion mode operation 53
Enhancement mode operation of the D-
MOSFET 54
Characteristics of Depletion MOSFET
54
TRANSFER CHARACTERISTICS 55
E-MOSFETS 55
CHARACTERISTICS OF E MOSFET
56
DRAIN CHARACTERISTICS 56
TRANSFER CHARACTERISTICS 56
APPLICATION OF MOSFET 57
Field Effect Transistor 57
INTRODUCTION 57
Common Source (CS) Amplifier 58
Common Drain Amplifier 58
Voltage Gain 59
Input Impedance 59
Output Impedance 59
vii
CLASSIFICATION OF AMPLIFIERS
61
DECIBEL NOTATION 61
MULTISTAGE AMPLIFIERS 62
DISTORTION IN AMPLIFIERS 63
NON – LINEAR DISTORTION 63
FREQUENCY DISTORTION 64
PHASE DISTRIBUTION 64
INTERMODULATION DISTORTION
64
FREQUENCY RESPONSE OF AN
AMPLIFIER 64
LOW FREQUENCY RESPONSE 66
HIGH FREQUENCY RESPONSE 66
FREQUENCY RESPONSE PLOTS 66
BANDWIDTH 66
RC COUPLED AMPLIFIER 67
ANALYSIS OF TWO STAGE RC
COUPLED AMPLIFIER 67
Current gain (Ai2) 68
Input resistance (Ri2) 68
viii
Voltage gain (Av2) 68
Current gain (Ai1) 68
Input resistance (Ri1) 68
Voltage gain (Av1) 69
Overall gain (Av ) 69
Darlington Transistor 69
POWER AMPLIFIERS 69
Power Transistor 70
Difference between Voltage and Power
Amplifiers 70
Classification Based on
Frequencies 71
Classification Based on Mode of
Operation 71
Terms Considering Performance 72
Collector Efficiency 72
Power Dissipation Capacity 72
Distortion 72
CLASS A POWER AMPLIFIER 72
Advantages of Class A Amplifiers 75
Disadvantages of Class A Amplifiers 75
ix
TRANSFORMER COUPLED 75
CLASS-A POWER AMPLIFIER 75
Transformer Action 76
Circuit Analysis 77
Advantages 77
Disadvantages 77
Applications 77
CLASS –B POWER AMPLIFIER 78
Class B Operation 78
Class B Push-Pull Amplifier 78
Construction 78
Operation 79
Power Efficiency of Class B Push-Pull
Amplifier 79
Complementary Symmetry Push-Pull
Class B Amplifier 80
Advantages 80
Disadvantages 81
Cross-over Distortion 81
Class AB Power Amplifier 82
x
Class C Power Amplifier 83
xi
GAIN STABILITY 89
REDUCTION IN FREQUENCY DISTORTION
90
NON LINEAR DISTORTION 90
NOISE 90
OSCILLATORS 90
Amplifier vs. Oscillator 91
Alternator vs. Oscillator 91
Classification of Oscillators 91
Nature of Sinusoidal Oscillations 92
Practical Oscillator Circuit 93
Frequency Stability of an Oscillator 93
The Barkhausen Criterion 94
Principle of Feedback Amplifier 94
Types of Tuned Circuit Oscillators 95
Hartley Oscillator 95
Construction 95
Tank Circuit 96
Operation 96
Frequency 96
xii
Advantages 97
Disadvantages 97
Applications 97
Colpitts Oscillator 97
Construction 97
Tank Circuit 98
Operation 98
Frequency 98
Advantages 98
Applications 99
RC Phase shift oscillator 99
Drawbacks of LC circuits 99
Principle of Phase-shift oscillators 99
Phase-shift Oscillator Circuit 100
Construction 100
Operation 101
Advantages 101
Disadvantages 101
Wien bridge oscillator 101
Construction 101
xiii
Operation 102
Advantages 103
Disadvantages 103
xiv
Ideal Op-Amp 106
Practical Op-Amp 106
Inverting Amplifier 107
Non-Inverting Amplifier 108
Integrator and Differentiator 109
Waveform Generators 110
Square Wave Generator 110
Triangular Wave Generator 112
Bibliography 113
xv
1
Chapter-1
DIODE CIRCUITS
P-N junction diode, I-V characteristics of a diode; review of half-wave and full-wave rectifiers,
clamping and clipping circuits. Input output characteristics of BJT in CB, CE, CC configurations,
biasing circuits,Load line analysis, common emitter, common base and common collector amplifiers;
Small signal equivalent circuits.
INTRODUCTON
Based on the electrical conductivity all the materials in nature are classified as
insulators,semiconductors, and conductors.
Insulator: An insulator is a material that offers a very low level (or negligible) of conductivity when
voltage is applied. Eg: Paper, Mica, glass, quartz. Typical resistivity level of an insulator is of the order
of 1010 to 1012 Ω-cm. The energy band structure of an insulator is shown in the fig.1.1. Band structure
ofa material defines the band of energy levels that an electron can occupy. Valance band is the range
of electron energy where the electron remain bended too the atom and do not contribute to the electric
current. Conduction bend is the range of electron energies higher than valance band where electrons
are free to accelerate under the influence of external voltage source resulting in the flow of charge.
The energy band between the valance band and conduction band is called as forbidden band
gap. It is the energy required by an electron to move from balance band to conduction band i.e. the
energy required for a valance electron to become a free electron.
1 eV = 1.6 x 10-19 J
For an insulator, as shown in the fig.1.1 there is a large forbidden band gap of greater than 5Ev.
Becauseof this large gap there a very few electrons in the CB and hence the conductivity of insulator
is poor. Even an increase in temperature or applied electric field is insufficient to transfer electrons
from VB to CB.
CB
CB CB
Forbidden band o
Eo =≈6eV
gap Eo ≈6eV
VB
VB
VB
Conductors: A conductor is a material which supports a generous flow of charge when a voltage is applied
across its terminals. i.e. it has very high conductivity. Eg: Copper, Aluminum, Silver, Gold. The resistivity
of a conductor is in the order of 10-4 and 10-6 Ω-cm. The Valance and conduction bands overlap (fig1.1)
and there is no energy gap for the electrons to move from valance band to conduction band. This implies
that there are free electrons in CB even at absolute zero temperature (0K). Therefore at room temperature
when electric field is applied large current flows through the conductor.
Semiconductor: A semiconductor is a material that has its conductivity somewhere between the insulator
and conductor. The resistivity level is in the range of 10 and 104 Ω-cm. Two of the most commonly used
are Silicon (Si=14 atomic no.) and germanium (Ge=32 atomic no.). Both have 4 valanceelectrons. The
forbidden band gap is in the order of 1eV. For eg., the band gap energy for Si, Ge and GaAs is 1.21, 0.785
and 1.42 eV, respectively at absolute zero temperature (0K). At 0K and at low temperatures, the valance
band electrons do not have sufficient energy to move from V to CB. Thus semiconductors act a insulators
at 0K. as the temperature increases, a large number of valance electrons acquire sufficient energy to leave
the VB, cross the forbidden bandgap and reach CB. These are now free electrons as they can move freely
under the influence of electric field. At room temperature there are sufficient electrons in the CB and
hence the semiconductor is capable of conducting some current at room temperature.
Inversely related to the conductivity of a material is its resistance to the flow of charge or current.
Typical resistivity values for various materials’ are given as follows.
Semiconductor Types
EXTRINSIC SEMICONDUCTOR
Intrinsic semiconductor has very limited applications as they conduct very small amounts of
current at room temperature. The current conduction capability of intrinsic semiconductor can beincreased
significantly by adding a small amounts impurity to the intrinsic semiconductor. By adding impurities it
becomes impure or extrinsic semiconductor. This process of adding impurities is called as doping. The
amount of impurity added is 1 part in 106 atoms.
N type semiconductor: If the added impurity is a pentavalent atom then the resultant semiconductor is
called N-type semiconductor. Examples of pentavalent impurities are Phosphorus, Arsenic, Bismuth,
Antimony etc.
P type semiconductor: If the added impurity is a trivalent atom then the resultant semiconductor is called
P-type semiconductor. Examples of trivalent impurities are Boron, Gallium , indium etc. Thus inP type
sc , holes are majority carriers and electrons are minority carriers. Since each trivalent impurity atoms are
capable accepting an electron, these are called as acceptor atoms. The following fig 1.5b shows the
pictorial representation of P type sc
The conductivity of N type sc is greater than that of P type sc as the mobility of electron is
greater than that of hole.
For the same level of doping in N type sc and P type sc, the conductivity of an N type sc
is around twice that of a P type sc.
A PN Junction Diode is one of the simplest semiconductor devices around, and which has
the characteristic of passing current in only one direction only. However, unlike a resistor, a diode does
not behave linearly with respect to the applied voltage as the diode has an exponential current- voltage (
I-V ) relationship and therefore we cannot described its operation by simply using an equation such as
Ohm’s law.
If a suitable positive voltage (forward bias) is applied between the two ends of the PN junction, it
can supply free electrons and holes with the extra energy they require to cross the junction as the width of
the depletion layer around the PN junction is decreased.
By applying a negative voltage (reverse bias) results in the free charges being pulled away from
the junction resulting in the depletion layer width being increased. This has the effect of increasing or
decreasing the effective resistance of the junction itself allowing or blocking current flow through the
diode.
Then the depletion layer widens with an increase in the application of a reverse voltage and
narrows with an increase in the application of a forward voltage. This is due to the differences in the
electrical properties on the two sides of the PN junction resulting in physical changes taking place. One
of the results produces rectification as seen in the PN junction diodes static I-V (current-voltage)
characteristics. Rectification is shown by an asymmetrical current flow when the polarity of bias voltage
is altered as shown below.
4
But before we can use the PN junction as a practical device or as a rectifying device we need to
firstly bias the junction, ie connect a voltage potential across it. On the voltage axis above, “Reverse Bias”
refers to an external voltage potential which increases the potential barrier. An external voltage which
decreases the potential barrier is said to act in the “Forward Bias” direction.
There are two operating regions and three possible “biasing” conditions for the standard
Junction Diode and these are:
1. Zero Bias – No external voltage potential is applied to the PN junction diode.
2. Reverse Bias – The voltage potential is connected negative, (-ve) to the P-type material and
positive, (+ve) to the N-type material across the diode which has the effect of Increasing the PN junction
diode’s width.
3. Forward Bias – The voltage potential is connected positive, (+ve) to the P-type material and
negative, (-ve) to the N-type material across the diode which has the effect of Decreasing the PN junction
diodes width.
Zero Biased Junction Diode
When a diode is connected in a Zero Bias condition, no external potential energy is applied to the
PN junction. However if the diodes terminals are shorted together, a few holes (majority carriers) in the
P-type material with enough energy to overcome the potential barrier will move across the junction against
this barrier potential. This is known as the “Forward Current” and is referenced as IF
Likewise, holes generated in the N-type material (minority carriers), find this situation favourable
and move across the junction in the opposite direction. This is known as the “Reverse Current” and is
referenced as IR. This transfer of electrons and holes back and forth across the PN junction is known as
diffusion, as shown below.
5
The potential barrier that now exists discourages the diffusion of any more majority carriers across
the junction. However, the potential barrier helps minority carriers (few free electrons in the P- region and
few holes in the N-region) to drift across the junction.
The minority carriers are constantly generated due to thermal energy so this state of equilibrium
can be broken by raising the temperature of the PN junction causing an increase in the generation of
minority carriers, thereby resulting in an increase in leakage current but an electric current cannot flow
since no circuit has been connected to the PN junction.
Reverse Biased PN Junction Diode
When a diode is connected in a Reverse Bias condition, a positive voltage is applied to the N- type
material and a negative voltage is applied to the P-type material.
The positive voltage applied to the N-type material attracts electrons towards the positive electrode
and away from the junction, while the holes in the P-type end are also attracted away from the junction
towards the negative electrode.
The net result is that the depletion layer grows wider due to a lack of electrons and holes and
presents a high impedance path, almost an insulator. The result is that a high potential barrier is created
thus preventing current from flowing through the semiconductor material.
Increase in the Depletion Layer due to Reverse Bias
6
This condition represents a high resistance value to the PN junction and practically zero current
flows through the junction diode with an increase in bias voltage. However, a very small leakagecurrent
does flow through the junction which can be measured in micro-amperes, ( μA ).
One final point, if the reverse bias voltage Vr applied to the diode is increased to a sufficiently
high enough value, it will cause the diode’s PN junction to overheat and fail due to the avalanche effect
around the junction. This may cause the diode to become shorted and will result in the flow of maximum
circuit current, and this shown as a step downward slope in the reverse static characteristics curve below.
Reverse Characteristics Curve for a Junction Diode
Sometimes this avalanche effect has practical applications in voltage stabilizing circuits where a
series limiting resistor is used with the diode to limit this reverse breakdown current to a presetmaximum
value thereby producing a fixed voltage output across the diode. These types of diodes are commonly
known as Zener Diodes and are discussed in a later tutorial.
Forward Biased PN Junction Diode
When a diode is connected in a Forward Bias condition, a negative voltage is applied to the N-
type material and a positive voltage is applied to the P-type material. If this external voltage becomes
greater than the value of the potential barrier, approx. 0.7 volts for silicon and 0.3 volts for germanium,
the potential barriers opposition will be overcome and current will start to flow.
This is because the negative voltage pushes or repels electrons towards the junction giving them
the energy to cross over and combine with the holes being pushed in the opposite direction towards the
junction by the positive voltage. This results in a characteristics curve of zero current flowing up to this
voltage point, called the “knee” on the static curves and then a high current flow through the diode with
little increase in the external voltage as shown below.
7
The application of a forward biasing voltage on the junction diode results in the depletion layer
becoming very thin and narrow which represents a low impedance path through the junction thereby
allowing high currents to flow. The point at which this sudden increase in current takes place is represented
on the static I-V characteristics curve above as the “knee” point.
Reduction in the Depletion Layer due to Forward Bias
This condition represents the low resistance path through the PN junction allowing very large
currents to flow through the diode with only a small increase in bias voltage. The actual potential
difference across the junction or diode is kept constant by the action of the depletion layer at
approximately 0.3v for germanium and approximately 0.7v for silicon junction diodes.
Since the diode can conduct “infinite” current above this knee point as it effectively becomes a
short circuit, therefore resistors are used in series with the diode to limit its current flow. Exceeding its
maximum forward current specification causes the device to dissipate more power in the form of heat than
it was designed for resulting in a very quick failure of the device.
Junction Diode Summary
The PN junction region of a Junction Diode has the following important characteristics:
Semiconductors contain two types of mobile charge carriers, “Holes” and “Electrons”.
The holes are positively charged while the electrons negatively charged.
A semiconductor may be doped with donor impurities such as Antimony (N-type doping),
so that it contains mobile charges which are primarily electrons.
A semiconductor may be doped with acceptor impurities such as Boron (P-type doping),
8
RECTIFIERS:
INTRODUCTION
For the operation of most of the electronics devices and circuits, a d.c. source is required. So it is
advantageous to convert domestic a.c. supply into d.c voltages. The process of converting a.c. voltage into
d.c. voltage is called as rectification. This is achieved with i) Step-down Transformer, ii) Rectifier,
iii) Filter and iv) Voltage regulator circuits.
These elements constitute d.c. regulated power supply shown in the fig 1 below.
9
The block diagram of a regulated D.C. power supply consists of step-down transformer, rectifier,
filter, voltage regulator and load. An ideal regulated power supply is an electronics circuit designed to
provide a predetermined d.c. voltage Vo which is independent of the load current and variations in the
input voltage ad temperature. If the output of a regulator circuit is a AC voltage then it is termed as voltage
stabilizer, whereas if the output is a DC voltage then it is termed as voltage regulator.
RECTIFIER
Any electrical device which offers a low resistance to the current in one direction but a high resistance to
the current in the opposite direction is called rectifier. Such a device is capable of converting a sinusoidal
input waveform, whose average value is zero, into a unidirectional Waveform, with a non- zero average
component. A rectifier is a device, which converts a.c. voltage (bi-directional) to pulsating
d.c. voltage (Unidirectional).
The effective (or) R.M.S. current squared ofa periodic function of time is given by the area of one cycle
of the curve, which represents the square of the function divided by the base.
1T
T
Vrms V d (wt)
peakvalue
Peak factor =
rmsvalue
iii) Form factor:
Rmsvalue
Form factor=
averagevalue
v) Efficiency :
It is the ratio of d.c output power to the a.c. input power. It signifies, how efficiently the rectifier circuit
converts a.c. power into d.c. power.
o / p power
i / p power
The d.c. power to be delivered to the load in a rectifier circuit decides the rating of the
Transformer used in the circuit. So, transformer utilization factor is defined as
Pdc
TUF
pac(rated)
viii) % Regulation:
The variation of the d.c. output voltage as a function of d.c. load current is called regulation. The
percentage regulation is defined as
VNL VFL
% Re gulation *100
VFL
CLASSIFICATION OF RECTIFIERS
Using one or more diodes in the circuit, following rectifier circuits can be designed.
1) Half - Wave Rectifier
2) Full – Wave Rectifier
3) Bridge Rectifier
HALF-WAVE RECTIFIER:
A Half – wave rectifier as shown in fig 1.2 is one, which converts a.c. voltage into a pulsating voltage
using only one half cycle of the applied a.c. voltage.
The a.c. voltage is applied to the rectifier circuit using step-down transformer-rectifying element i.e., p-
n junction diode and the source of a.c. voltage, all connected is series. The a.c. voltage is applied to the
rectifier circuit using step-down transformer
Operation:
For the positive half-cycle of input a.c. voltage, the diode D is forward biased and hence it conducts.
Now a current flows in the circuit and there is a voltage drop across RL.
For the negative half-cycle of input, the diode D is reverse biased and hence it does not
Conduct. Now no current flows in the circuit i.e., i=0 and Vo=0. Thus for the negative half- cycle
no power is delivered to the load.
Fig. 5 shows the input and output wave forms of the ckt.
During positive half of the input signal, anode of diode D1 becomes positive and at the
same time the anode of diode D2 becomes negative. Hence D1 conducts and D2 does not
conduct. The load current flows through D1 and the voltage drop across RL will be equal to
the input voltage.
During the negative half cycle of the input, the anode of D1 becomes negative and the anode of
D2 becomes positive. Hence, D1 does not conduct and D2 conducts. The load current flows through D2
and the voltage drop across RL will be equal to the input voltage. It is noted that the load current flows in
the both the half cycles of ac voltage and in the same direction through the load resistance.
i) AVERAGEVOLTAGE
14
1T
Vrms
V d (wt)
2
1
Vrms
2 (V sim(wt)) d (wt)
m
Rms value
Form factor=
averagevalue
V) Efficiency:
Advantages:
Transistors are three terminal active devices made from different semiconductor materials that can act as
either an insulator or a conductor by the application of a small signal voltage. The transistor's ability to
change between these two states enables it to have two basic functions: "switching" (digital electronics)
or "amplification" (analogue electronics). Then bipolar transistors have the ability to operate within three
different regions:
Bipolar Transistors are current regulating devices that control the amount of current flowing through
them in proportion to the amount of biasing voltage applied to their base terminal acting like a
current-controlled switch. The principle of operation of the two transistor types PNP and NPN, is
exactly the same the only difference being in their biasing and the polarity of the power supply for
each type.
Bipolar Transistor Construction
The construction and circuit symbols for both the PNP and NPN bipolar transistor are given
above with the arrow in the circuit symbol always showing the direction of "conventional
current flow" between the base terminal and its emitter terminal. The direction of the arrow
always points from the positive P-type region to the negative N-type region for both transistor
types, exactly the same as for the standard diode symbol.
TRANSISTOR CURRENT COMPONENTS:
The above fig 3.2 shows the various current components, which flow across the forward biased emitter
junction and reverse- biased collector junction. The emitter current IE consists of hole current IPE (holes
crossing from emitter into base) and electron current InE (electrons crossing from base into emitter).The
ratio of hole to electron currents, IpE / InE , crossing the emitter junction is proportional to the ratio of the
conductivity of the p material to that of the n material. In a transistor, the doping of that of the emitter is
made much larger than the doping of the base. This feature ensures (in p-n-p transistor) that the emitter
current consists an almost entirely of holes. Such a situation is desired since the current which results from
electrons crossing the emitter junction from base to emitter do not contribute carriers, which can reach the
collector.
For a p-n-p transistor, ICO consists of holes moving across JC from left to right (base to collector) and
electrons crossing JC in opposite direction. Assumed referenced direction for ICO i.e. from right to left, then
for a p-n-p transistor, ICO is negative. For an n-p-n transistor, ICO is positive.The basic operation will be
described using the pnp transistor. The operation of the pnp transistor is exactly the same if the roles
played by the electron and hole are interchanged. One p-n junction of a transistor is reverse-biased,
whereas the other is forward-biased.
19
As the Bipolar Transistor is a three terminal device, there are basically three possible ways to connect
it within an electronic circuit with one terminal being common to both the input and output. Each
method of connection responding differently to its input signal within a circuit as the static
characteristics of the transistor vary with each circuit arrangement.
1. Common Base Configuration - has Voltage Gain but no Current Gain.
2 Common Emitter Configuration - has both Current and Voltage Gain.
3. Common Collector Configuration - has Current Gain but no Voltage Gain.
COMMON-BASE CONFIGURATION
Common-base terminology is derived from the fact that the : base is common to both input and output of
t configuration. base is usually the terminal closest to or at ground potential. Majority carriers can cross
the reverse-biased junction because the injected majority carriers will appear as minority carriers in the n-
type material. All current directions will refer to conventional (hole) flow and the arrows in all electronic
symbols have a direction defined by this convention.
Note that the applied biasing (voltage sources) are such as to establish current in the direction indicated
for each branch.
TRANSISTOR AS AN AMPLIFIER
Common-Emitter Configuration
It is called common-emitter configuration since : emitter is common or reference to both input and
output terminals. Emitter is usually the terminal closest to or at ground potential. Almost amplifier
design is using connection of CE due to the high gain for current and voltage. Two set of
characteristics are necessary to describe the behavior for CE ;input (base terminal) and output
(collector terminal) parameters. Proper Biasing common-emitter configuration in active region.
Base-emitter junction is forward bias Increasing VCE will reduce IB for different values.
Also called emitter-follower(EF). It is called common-emitter configuration since both the signal
source and the load share the collector terminal as a common connection point. The output voltage is
obtained at emitter terminal. The input characteristic of common-collector configuration is similar
with common-emitter configuration. Common-collector circuit configuration is provided with the
load resistor connected from emitter to ground. It is used primarily for impedance- matching
purpose since it has high input impedance and low output impedance.
For the common-collector configuration, the output characteristics are a plot of IE vs VCE for a range
of values of
IB.
Fig 3.11 Output Characteristics of CC Configuration for npn Transistor
Limits of operation
Many BJT transistor used as an amplifier. Thus it is important to notice the limits of operations. At
least 3 maximum values is mentioned in data sheet.
There are:
There are few rules that need to be followed for BJT transistor used as an amplifier. The rules are:
transistor need to be operate in active region! IC < ICmax PC < PCmax
25
Fig. 1
A two-port network is represented by four external variables: voltage V1 and current I1 at the input port,
and voltage V2 and current I2 at the output port, so that the two-port network can be treated as a black box
modeled by the relationships between the four variables, V1,V2, I1,I2 . Out of four variables two can be
selected as are independent variables and two are dependent variables. The dependent variables can be
expressed interns of independent variables. This leads to various two port parameters out of which the
following three are important:
Where
Input impedance with output port open circuited
If the input current I1 and output voltage V2 are taken as independent variables, the dependent
variables V1 and I2 can be written as
NETWORK:
Based on the definition of hybrid parameters the mathematical model for two pert networks known as
h-parameter model can be developed. The hybrid equations can be written as:
If these parameters are specified for a particular configuration, then suffixes e,b or c are also
included, e.g. hfe ,h ib are h parameters of common emitter and common collector amplifiers
Using two equations the generalized model of the amplifier can be drawn as shown in fig. 2.
To form a transistor amplifier it is only necessary to connect an external load and signal source as
For the transistor amplifier stage, Ai is defined as the ratio of output to input currents.
Input impedance:
The impedance looking into the amplifier input terminals ( 1,1' ) is the input impedance Zi
29
Voltage gain:
The ratio of output voltage to input voltage gives the gain of the transistors.
Output Admittance:
It is defined as
Consider input source to be a current source IS in parallel with a resistance RS as shown in fig. 3.
h-parameters:
To analyze multistage amplifier the h-parameters of the transistor used are obtained
from manufacture
data sheet. The manufacture data sheet usually provides h-parameter in CE
configuration. These parameters may be converted into CC and CB values. For
example fig. 4 hrc in terms of CE parameter can be obtained as follows.
The two port network of Fig. 1.4 represents a transistor in any one of its configuration. It is
assumed that h-parameters remain constant over the operating range. The input is sinusoidal and I1,V-
1,I2 and V2 are phase quantities.
In the circuit of Fig , RS is the signal source resistance .The impedance seen when looking into the
amplifier terminals (1,1’) is the amplifier input impedance Zi,
Zi = V1 / I1
From the input circuit of Fig V1 = hi I1 +
hrV2 Zi = ( hi I1 + hrV2) / I1
= hi + hr V2 / I1
32
Substituting
V2 = -I2 ZL = A1I1ZL
Zi = hi + hr A1I1ZL / I1
= hi + hr A1ZL
Substituting for Ai
Zi = hi - hf hr ZL / (1+ hoZL)
= hi - hf hr ZL / ZL(1/ZL+ ho)
The ratio of output voltage V2 to input voltage V1 give the voltage gain of the transistor i.e,
Av = V2 / V1
Substituting
V2 = -I2 ZL = A1I1ZL
Av = A1I1ZL / V1 = AiZL / Zi
Yo is obtained by setting VS to zero, ZL to infinity and by driving the output terminals from a generator
V2. If the current V2 is I2 then Yo= I2/V2 with VS=0 and RL= ∞.
I2= hf I1 + hoV2
Dividing by V2,
I2 / V2 = hf I1/V2 + ho
33
RSI1 + hi I1 + hrV2 = 0
= hf (-hr/( RS + hi)+ho
The output admittance is a function of source resistance. If the source impedance is resistive then Yo is
real.
Voltage Amplification Factor(Avs) taking into account the resistance (Rs) of the source
From the equivalent input circuit using Thevenin’s equivalent for the source shown in Fig. 5.6
V1 = VS Zi / (Zi + RS)
V1 / VS = Zi / ( Zi + RS)
Then, Avs = Av Zi / ( Zi +
Zi
Avs = AisZL / RS
There are four conditions to be met by a transistor so that it acts as a faithful ampr:
1) Emitter base junction must be forward biased (VBE=0.7Vfor Si, 0.2V for Ge) and collector
base junction must be reverse biased for all levels of i/p signal.
2) Vce voltage should not fall below VCE (sat) (0.3V for Si, 0.1V for Ge) for any part of the i/p
signal. For VCE less than VCE (sat) the collector base junction is not probably reversebiased.
3) The value of the signal Ic when no signal is applied should be at least equal to the max. collector
current t due to signal alone.
4) Max. rating of the transistor Ic(max), VCE (max) and PD(max) should not be exceeded at any value of
i/p signal.
Consider the fig shown in fig1. If operating point is selected at A, A represents a condition when no
bias is applied to the transistor i.e, Ic=0, VCE =0. It does not satisfy the above said conditions necessary for
faithful amplification.
Point C is too close to PD(max) curve of the transistor. Therefore the o/p voltage swing in the positive
direction is limited.
Point B is located in the middle of active region .It will allow both positive and negative half cycles
in the o/p signal. It also provides linear gain and larger possible o/p voltages andcurrents
Hence operating point for a transistor amplifier is selected to be in the middle of active region.
DC LOAD LINE
Referring to the biasing circuit of fig 4.2a, the values of VCC and RC are fixed and Ic and VCE are
dependent on RB.
Applying Kirchhoff’s voltage law to the collector circuit in fig. 4.2a, we get
The straight line represented by AB in fig4.2b is called the dc load line. The coordinates of the end
point A are obtained by substituting VCE =0 in the above equation. Then . Therefore The
coordinates of A are VCE =0 and .
The coordinates of B are obtained by substituting Ic=0 in the above equation. Then Vce = Vcc.
Therefore the coordinates of B are VCE =Vcc and Ic=0. Thus the dc load line AB can be drawn if the values
of Rc and Vcc are known.
As shown in the fig4.2b, the optimum POINT IS LOCATED AT THE MID POINT OF THE
MIDWAY BETWEEN a AND b. In order to get faithful amplification, the Q point must be well within
the active region of the transistor.
Even though the Q point is fixed properly, it is very important to ensure that the operating point
remains stable where it is originally fixed. If the Q point shifts nearer to either A or B, the output voltage
and current get clipped, thereby o/p signal is distorted.
In practice, the Q-point tends to shift its position due to any or all of the following three main factors.
1) Reverse saturation current, Ico, which doubles for every 10oC raise in temperature
2) Base emitter Voltage ,VBE, which decreases by 2.5 mV per oC
3) Transistor current gain, hFE or β which increases withtemperature.
If base current IB is kept constant since IB is approximately equal to Vcc/RB. If the transistor is replaced
by another one of the same type, one cannot ensure that the new transistor will have identical parameters
as that of the first one. Parameters such as β vary over a range. This results in the variation ofcollector
current Ic for a given IB. Hence, in the o/p characteristics, the spacing between the curves might increase
or decrease which leads to the shifting of the Q-point to a location which might be completely
unsatisfactory.
AC LOAD LINE
After drawing the dc load line, the operating point Q is properly located at the center of the dc
load line. This operating point is chosen under zero input signal condition of the circuit. Hence the ac
load line should also pas through the operating point Q. The effective ac load resistance Rac, is a
combination of RC parallel to RL i.e. || . So the slope of the ac load line CQD will be .
To draw the ac load line, two end points, I.e. VCE(max) and IC(max) when the signal is applied are required.
By joining points c and D, ac load line CD is constructed. As RC > Rac, The dc load line is less steep
than ac load line.
The rise of temperature results in increase in the value of transistor gain β and the leakage current
Ico. So, IC also increases which results in a shift in operating point. Therefore, The biasing network should
be provided with thermal stability. Maintenance of the operating point is specified by S, which indicates
the degree of change in operating point due to change in temperature.
For CE configuration
S’ is defined as the rate of change of IC with VBE, keeping IC and VBE constant.
S’’ is defined as the rate of change of IC with β, keeping ICO and VBE constant.
38
This form of biasing is also called base bias. In the fig 4.3 shown, the single
power source (for example, battery) is used for both collector and base of a transistor,
although separate batteries can also be used.
In the given circuit, Vcc = IBRB + Vbe
Therefore, IB = (Vcc - Vbe)/RB
Since the equation is independent of current ICR, dIB//dICR =0 and the
stability factor is given by the equation….. reduces to
S=1+β
Since β is a large quantity, this is very poor biasing circuit. Therefore in
practice the circuit is not used fo biasing.
For a given transistor, Vbe does not vary significantly during use. As Vcc is
of fixed value, on selection of R the base current IB is fixed. Therefore this type is
called fixed bias type of circuit.
Also for given circuit, Vcc = ICRC + Vce
Therefore, Vce = Vcc - ICRC
Merits:
It is simple to shift the operating point anywhere in the active region by
merely changing the base resistor (RB).
A very small number of components are required.
Demerits:
The collector current does not remain constant with variation in temperature
or power supply voltage. Therefore the operating point is unstable.
Changes in Vbe will change IB and thus cause RE to change. This in turn
will alter the gain of the stage.
When the transistor is replaced with another one, considerable change in the
value ofβ can be expected. Due to this change the operating point will shift.
39
EMITTER-FEEDBACK BIAS:
The emitter feedback bias circuit is shown in the fig 4.4. The fixed bias circuit
is modified by attaching an external resistor to the emitter. This resistor introduces
negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law, the
voltage across the base resistor is
VRb = VCC - IeRe - Vbe.
If Vbe is held constant and temperature increases, then the collector current
Ic increases. However, a larger Ic causes the voltage drop across resistor Rc to
increase, which in turn reduces the voltage across the base resistor Rb. A lower
base-resistor voltage drop reduces the base current Ib, which results in less collector
current Ic. Because an increase in collector current with temperature is opposed, the
operating point is kept stable.
Merits:
Circuit stabilizes the operating point against variations in temperature and β
(i.e. replacement of transistor)
Demerits:
In this circuit, to keep Ic independent of β, the following condition must be
met:
Usage: The feedback also decreases the input impedance of the amplifier as
seen from the base, which can be advantageous. Due to the gain reduction from
feedback, this biasing form is used only when the trade-off for stability is warranted.
The above fig4.6 shows the collector –emitter feedback bias circuit that can
be obtained by applying both the collector feedback and emitter feedback. Here the
collector feedback is provided by connecting a resistance RB from the collector to the
base and emitter feedback is provided by connecting an emitter Re from emitter to
ground. Both feed backs are used to control collector current and base current IB in
the opposite direction to increase the stability as compared to the previous biasing
circuits.
The voltage divider as shown in the fig 4.7 is formed using external resistors
R1 and R2. The voltage across R2 forward biases the emitter junction. By proper
selection of resistors R1 and R2, the operating point of the transistor can be made
independent of β. In this circuit, the voltage divider holds the base voltage fixed
independent of base current provided the divider current is large compared to the base
current. However, even with a fixed base voltage, collector current varies with
temperature (for example) so an emitter resistor is added to stabilize the Q-point,
similar to the above circuits with emitter resistor.
voltage across
provided .
It is apparent from above expression that the collector current is independent of ? thus the
stability is excellent. In all practical cases the value of VBE is quite small in comparison to the
V2, so it can be ignored in the above expression so the collector current is almost independent
of the transistor parameters thus this arrangement provides excellent stability.
Again applying KVL in collector circuit, we have
The resistor RE provides stability to the circuit. If the current through the collector rises, the
voltage across the resistor RE also rises. This will cause VCE to increase as the voltage V2 is
independent of collector current. This decreases the base current, thus collector current
increases to its former value.
Stability factor for such circuit arrangement is given by
Which is excellent since it is the smallest possible value for the stability. In actual practice the value of stability
factor is around 8-10, since Req/RE cannot be ignored as compared to 1.
Merits:
Chapter-2
MOSFET CIRCUITS
MOSFET structure and I-V characteristics. MOSFET as a switch. small signal equivalent circuits -
gain, input and output impedances, small-signal model and common-source, common-gate and
common-drain amplifiers, trans conductance, high frequency equivalent circuit.
INTRODUCTION
The Field effect transistor is abbreviated as FET , it is an another semiconductor device like a BJT
which can be used as an amplifier or switch.
The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a
current controlled device. Unlike BJT a FET requires virtually no input current.
This gives it an extremely high input resistance , which is its most important advantage over a bipolar
transistor.
FET is also a three terminal device, labeled as source, drain and gate.
The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the counter part of
the base.
The material that connects the source to drain is referred to as the channel.
FET operation depends only on the flow of majority carriers ,therefore they are called uni polar
devices. BJT operation depends on both minority and majority carriers.
As FET has conduction through only majority carriers it is less noisy than BJT.
FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less space
than BJTs.
FET amplifiers have low gain bandwidth product due to the junction capacitive effects and produce
more signal distortion except for small signal operation.
The performance of FET is relatively unaffected by ambient temperature changes. As it has a negative
temperature coefficient at high current levels, it prevents the FET from thermal breakdown. The BJT
has a positive temperature coefficient at high current levels which leads to thermal breakdown.
CLASSIFICATION OF FET:
There are two major categories of field effect transistors:
1. Junction Field Effect Transistors
2. MOSFETs
These are further sub divided in to P- channel and N-channel devices.
MOSFETs are further classified in to two types Depletion MOSFETs and Enhancement. MOSFETs
When the channel is of N-type the JFET is referred to as an N-channel JFET, when the channel is of P-
type the JFET is referred to as P-channel JFET.
The schematic symbols for the P-channel and N-channel JFETs are shown in the figure.
46
A piece of N- type material, referred to as channel has two smaller pieces of P-type material attached to
its sides, forming PN junctions. The channel ends are designated as the drain and source . And the two
pieces of P-type material are connected together and their terminal is called the gate. Since this channel is
in the N-type bar, the FET is known as N-channel JFET.
1) When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving
immobile ions on the N and P sides , the region containing these immobile ions is known as depletion
regions.
2) If both P and N regions are heavily doped then the depletion region extends symmetrically on both
sides.
3) But in N channel FET P region is heavily doped than N type thus depletion region extends more in N
region than P region.
4) So when no Vds is applied the depletion region is symmetrical and the conductivity becomes Zero.
Since there are no mobile carriers in the junction.
5) As the reverse bias voltage is increases the thickness of the depletion region also increases. i.e. the
effective channel width decreases .
6) By varying the value of Vgs we can vary the width of the channel.
This increasing drain current Id produces a voltage drop across rd which reverse biases the gate to
48
source junction,(rd> rs) .Thus the depletion region is formed which is not symmetrical .
The depletion region i.e. developed penetrates deeper in to the channel near drain and less towards
source because Vrd >> Vrs. So reverse bias is higher near drain than at source.
As a result growing depletion region reduces the effective width of the channel. Eventually a voltage
Vds is reached at which the channel is pinched off. This is the voltage where the current Id begins to
level off and approach a constant value.
So, by varying the value of Vds we can vary the width of the channel holding Vgs constant.
It is of course in principle not possible for the channel to close Completely and there by reduce the current
Id to Zero for, if such indeed, could be the case the gate voltage Vgs is applied in the direction to provide
additional reverse bias
When voltage is applied between the drain and source with a battery Vdd, the electrons flow from
source to drain through the narrow channel existing between the depletion regions. This constitutes
the drain current Id, its conventional direction is from drain to source.
The value of drain current is maximum when no external voltage is applied between gate and source
and is designated by Idss.
When Vgs is increased beyond Zero the depletion regions are widened. This reduces the effective
width of the channel and therefore controls the flow of drain current through the channel.
When Vgs is further increased a stage is reached at which to depletion regions touch each other that
means the entire channel is closed with depletion region. This reduces the drain current to Zero.
Drain Characteristics:-
Drain characteristics shows the relation between the drain to source voltage Vds and
drain current Id. In order to explain typical drain characteristics let us consider the curve with Vgs=
0.V.
1. When Vds is applied and it is increasing the drain current ID also increases linearly up to knee
point.
2. This shows that FET behaves like an ordinary resistor. This region is called as ohmic region.
3. ID increases with increase in drain to source voltage. Here the drain current is increased slowly as
compared to ohmic region.
4) It is because of the fact that there is an increase in VDS .This in turn increases the reverse bias voltage
across the gate source junction .As a result of this depletion region grows in size thereby reducing the
effective width of the channel.
5) All the drain to source voltage corresponding to point the channel width is reduced to a minimum
value and is known as pinch off.
6) The drain to source voltage at which channel pinch off occurs is called pinch off voltage(Vp).
Id =Idss [1-Vgs/Vp]2
This causes
o The maximum saturation drain current is smaller
o The ohmic region portion decreased.
It is important to note that the maximum voltage VDS which can be applied to FET is the lowest
voltage which causes available break down.
TRANSFER CHARACTERISTICS:-
These curves shows the relationship between drain current ID and gate to source voltage VGS
for different values of VDS.
i) First adjust the drain to source voltage to some suitable value , then increase the gate to source
voltage in small suitable value.
ii) Plot the graph between gate to source voltage along the horizontal axis and current ID on the
vertical axis. We shall obtain a curve like this.
iii) As we know that if Vgs is more negative curves drain current to reduce . where V gs is made
sufficiently negative, Id is reduced to zero. This is caused by the widening of the depletion region
to a point where it is completely closes the channel. The value of Vgs at the cutoff pointis
designed as Vgsoff
iv) While the lower end is indicated by a voltage equal to Vgsoff
v) If Vgs continuously increasing , the channel width is reduced , then Id =0
vi) It may be noted that curve is part of the parabola; it may be expressed as
Id=Idss[1-Vgs/Vgsoff]2
DIFFERENCE BETWEEN Vp AND Vgsoff –
Vp is the value of Vgs that causes the JFET to become constant current component, It is measured at
Vgs =0V and has a constant drain current of Id =Idss .Where Vgsoff is the value of Vgs that reduces Id to
approximately zero.
The gate to source junction of a JFET is never allowed to become forward biased because the gate
material is not designed to handle any significant amount of current. If the junction is allowed to become
forward biased, current is generated through the gate material. This current may destroy the component. There
is one more important characteristic of JFET reverse biasing i.e. JFET’s have extremely high characteristic gate
input impedance. This impedance is typically in the high mega ohm range. With the advantage of extremely
high input impedance it draws no current from the source. The high input impedance of the JFET has led to its
extensive use in integrated circuits. The low current requirements of the component makes it perfect for use in
ICs. Where thousands of transistors must be etched on to a single piece of silicon. The low current draw helps
the IC to remain relatively cool, thus allowing more components to be placed in a smaller physical area.
51
JFET PARAMETERS
The electrical behavior of JFET may be described in terms of certain parameters. Such parameters are
obtained from the characteristic curves.
A C Drain resistance(rd):
It is also called dynamic drain resistance and is the a.c resistance between the drain and source terminal, when
the JFET is operating in the pinch off or saturation region. It is given by the ratio of small change in drain to
source voltage ∆Vds to the corresponding change in drain current ∆Id for a constant gate to source voltage Vgs.
Mathematically it is expressed as rd=∆Vds/ ∆Id where Vgs is held constant.
TRANCE CONDUCTANCE (gm):
It is also called forward transconductance . It is given by the ratio of small change in drain current (∆Id) to the
corresponding change in gate to source voltage (∆Vds)
Mathematically the transconductance can be written as
gm=∆Id/∆Vds
AMPLIFICATION FACTOR (µ)
It is given by the ratio of small change in drain to source voltage (∆Vds) to the corresponding change in gate
to source voltage (∆Vgs)for a constant drain current (Id).
Thus µ=∆Vds/∆Vgs when Id held constant
The amplification factor µ may be expressed as a product of transconductance (gm)and ac drain resistance (rd)
µ=∆Vds/∆Vgs=gm rd
gm= |Vds
Is the mutual conductance or transconductance .It is also called as gfs or yfs common source forward
conductance .
The second parameter rd is the drain resistance or output resistance is defined as
rd= |Vgs
The reciprocal of the rd is the drain conductance gd .It is also designated by Yos and Gos and called
the common source output conductance . So the small signal equivalent circuit for FET can be drawn in two
different ways.
52
MOSFET:-
We now turn our attention to the insulated gate FET or metal oxide semi conductor FET which is having
the greater commercial importance than the junction FET.
Most MOSFETS however are triodes, with the substrate internally connected to the source. The circuit
symbols used by several manufacturers are indicated in the Fig below.
As we can see the D MOSFET have physical channel between the source and drain terminals(Shaded area)
53
The E MOSFET on the other hand has no such channel physically. It depends on the gate voltage to form
a channel between the source and the drain terminals.
Both MOSFETS have an insulating layer between the gate and the rest of the component. This
insulating layer is made up of SIO2 a glass like insulating material. The gate material is made up of metal
conductor .Thus going from gate to substrate, we can have metal oxide semi conductor which is where the term
MOSFET comes from. Since the gate is insulated from the rest of the component, the MOSFET is sometimes
referred to as an insulated gate FET or IGFET. The foundation of the MOSFET is called the substrate. This
material is represented in the schematic symbol by the center line that is connected to the source. In the symbol
for the MOSFET, the arrow is placed on the substrate. As with JFET an arrow pointing in represents an N-
channel device, while an arrow pointing out represents p-channel device.
The N- channel MOSFET consists of a lightly doped p type substance into which two heavily doped n+
regions are diffused as shown in the Fig. These n+ sections, which will act as source and drain. A thin layerof
insulation silicon dioxide (SIO2) is grown over the surface of the structure, and holes are cut into oxide layer,
allowing contact with the source and drain. Then the gate metal area is overlaid on the oxide, covering the entire
channel region. Metal contacts are made to drain and source and the contact to the metal over the channel area
is the gate terminal. The metal area of the gate, in conjunction with the insulating dielectric oxide layer and the
semiconductor channel, forms a parallel plate capacitor. The insulating layer of sio2
Is the reason why this device is called the insulated gate field effect transistor. This layer results in an extremely
high input resistance (10 10 to 10power 15ohms) for MOSFET.
DEPLETION MOSFET
The basic structure of D –MOSFET is shown in the fig. An N-channel is diffused between source and
drain with the device an appreciable drain current IDSS flows foe zero gate to source voltage, Vgs=0.
5. The re distribution of charge in the channel causes an effective depletion of majority carriers , which
accounts for the designation depletion MOSFET.
6. That means biasing voltage Vgs depletes the channel of free carriers This effectively reduces the width
of the channel , increasing its resistance.
7. Note that negative Vgs has the same effect on the MOSFET as it has on the JFET.
8. As shown in the fig above, the depletion layer generated by Vgs (represented by the white space
between the insulating material and the channel) cuts into the channel, reducing its width. As a result
,Id<Idss. The actual value of ID depends on the value of Idss,Vgs(off) and Vgs.
Enhancement mode operation of the D-MOSFET:-
This operating mode is a result of applying a positive gate to source voltage Vgs to the device.
When Vgs is positive the channel is effectively widened. This reduces the resistance of the channel
allowing ID to exceed the value of IDSS
When Vgs is given positive the majority carriers in the p-type are holes. The holes in the p type
substrate are repelled by the +ve gate voltage.
At the same time, the conduction band electrons (minority carriers) in the p type material are
attracted towards the channel by the +gate voltage.
With the build up of electrons near the channel , the area to the right of the physical channel
effectively becomes an N type material.
The extended n type channel now allows more current, Id> Idss
6) If Vgs>0 the gate induces more electrons in channel side, it is added with the free electrons generated
by source. again the potential applied to gate determines the channel width and maintains constant
current flow through it as shown in Fig
TRANSFER CHARACTERISTICS:-
The combination of 3 operating states i.e. Vgs=0V, VGs<0V, Vgs>0V is represented by the D
MOSFET transconductance curve shown in Fig.
Here in this curve it may be noted that the region AB of the characteristics similar to that of JFET.
This curve extends for the positive values of Vgs
Note that Id=Idss for Vgs=0V when Vgs is negative,Id< Idss when Vgs= Vgs(off) ,Id is reduced to
approximately omA.Where Vgs is positive Id>Idss.So obviously Idss is not the maximum possible
value of Id for a MOSFET.
The curves are similar to JFET so thet the D MOSFET have the same transconductance equation.
E-MOSFETS
The E MOSFET is capable of operating only in the enhancement mode. The gate potential must be
positive w.r.t to source.
when the value of Vgs=0V, there is no channel connecting the source and drain materials.
As aresult , there can be no significant amount of drain current.
56
When Vgs=0, the Vdd supply tries to force free electrons from source to drain but the presence of p-
region does not permit the electrons to pass through it. Thus there is no drain current at Vgs=0,
If Vgs is positive, it induces a negative charge in the p type substrate just adjacent to the SIO2 layer.
As the holes are repelled by the positive gate voltage, the minority carrier electrons attracted toward
this voltage. This forms an effective N type bridge between source and drain providing a path for
drain current.
This +ve gate voltage forma a channel between the source and drain.
This produces a thin layer of N type channel in the P type substrate. This layer of free electrons is
called N type inversion layer.
The minimum Vgs which produces this inversion layer is called threshold voltage and is designated
by Vgs(th).This is the point at which the device turns on is called the threshold voltage Vgs(th)
When the voltage Vgs is <Vgs (th) no current flows from drain to source.
How ever when the voltage Vgs > Vgs (th) the inversion layer connects the drain to source and we
get significant values of current.
CHARACTERISTICS OF E MOSFET:-
o DRAIN CHARACTERISTICS
The volt ampere drain characteristics of an N-channel enhancement mode MOSFET are given in the fig
o TRANSFER CHARACTERISTICS:-
The current Idss at Vgs≤ 0 is very small beinf of the order of a few nano amps.
As Vgs is made +ve , the current Id increases slowly at forst, and then much more rapidly with an
increase in Vgs.
The standard transconductance formula will not work for the E MOSFET.
To determine the value of ID at a given value of VGs we must use the following relation
Id =K[Vgs-Vgs(Th)]2
57
From the data specification sheets, the 2N7000 has the following ratings.
Id(on)= 75mA(minimum).
And Vgs(th)=0.8(minimum)
APPLICATION OF MOSFET
One of the primary contributions to electronics made by MOSFETs can be found in the area of digital
(computer electronics). The signals in digital circuits are made up of rapidly switching dc levels. This signal
is called as a rectangular wave ,made up of two dc levels (or logic levels). These logic levels are0V and
+5V. A group of circuits with similar circuitry and operating characteristics is referred to as a logic family.
All the circuits in a given logic family respond to the same logic levels, have similar speed and power-
handling capabilities , and can be directly connected together. One such logic family is complementary
MOS (or CMOS) logic. This logic family is made up entirely of MOSFETs.
Chapter-3
MULTISTAGE AND POWER AMPLIFIERS
In order to realize the function of amplification, the transformer may appear to be a potential
device. However, in a transformer, though there is magnification of input voltage or current,
the power required for the load has to be drawn from the source driving the input of the
transformer. The output power is always less than the input power due to the losses in the core
and windings. The situation in amplification is that the input source is not capable of supplying
appreciable power. Hence the functional block meant for amplification should not draw any
power from the input source but should deliver finite out power to the load.
Thus the functional block required should have input power
Pi = Vi Ii = 0
And give the output
P0 = V0 I0 = finite
Such a functional block is called an ideal amplifier, which is shown in Fig.1 below.
The power gain of an ideal amplifier being infinite may sound like witchcraft in that something
can be produced from nothing. The real fact is that the ideal amplifier requires dc input power.
It converts dc power to ac power without any demand on the signal source to supply the power
for the load.
61
CLASSIFICATION OF AMPLIFIERS
Amplifiers are classified in many ways based on different criteria as given below.
I In terms of frequency range:
1. DC amplifiers. (0 Hz to 20 Hz)
2. Audio amplifiers (20 Hz to 20 KHz)
3. Radio frequency amplifiers (Few KHz to hundreds of KHz)
4. Microwave amplifiers (In the range of GHz)
5. Video amplifiers (Hundreds of GHz)
1. Direct coupling.
2. Resistance – capacitance (RC) coupling.
3. Transformer coupling.
1. Voltage amplifiers.
2. Current amplifiers.
3. Power amplifiers.
DECIBEL NOTATION:
The power gain of an amplifier is expressed as the ratio of the output power to the input power.
When we have more than one stage of amplification i.e. when the output of one stage becomes the
input to the next stage, the overall gain has to be obtained by multiplying the gains of the
62
individual stages. When large numbers are involved, this calculation becomes cumbersome.
Also, when we have passive coupling networks between amplifier stages, there will be attenuation
of the signal that is gain less than unity. To find the overall gain of a typical multistage amplifier
such as the one given below.
We have to multiply the various gains and attenuations. Moreover, when we wish to plot the gain
of an amplifier versus frequency, using large numbers for plotting is not convenient. Hence it has
been the practice to use a new unit called the decibel (usually abbreviated as dB) for measuring
the power gain of a four terminal network. The power gain in decibels is given by
G = 10 log10 P0 / Pi dB
This new notation is also significant in the field of acoustics as the response of the human ear
to sound intensity is found to be following this logarithmic pattern. The overall gain in decibel
notation can be obtained for the amplifier gain of the figure1 by simply adding the decibel
gains of the individual networks. If any network attenuates the signal, the gain will beless than
the unity and the decibel gain will be negative. Thus the overall gain for the amplifier chain
shown above is given by
Overall gain = 10 – 6 + 30 – 10 + 20 = 44 dB
The absolute power level of the output of an amplifier is sometimes specified in dBm, i.e. decibels
with reference to a standard power power level, which is usually, 1 Mw dissipated in a 600 load.
Therefore, if an amplifier has 100 Mw, its power level in dBm is equal to 10 log 100/1 = 20 dBm.
MULTISTAGE AMPLIFIERS:
In real time applications, a single amplifier can’t provide enough output. Hence, two or more
amplifier stages are cascaded (connected one after another) to provide greater output Such an
arrangement is known as multistage amplifier Though the basic purpose of this arrangement is
increase the overall gain, many new problems as a consequence of this, are to be taken care. For
e.g. problems such as the interaction between stages due to impedance mismatch, cumulative hum
& noise etc.
63
DISTORTION IN AMPLIFIERS:
In any amplifier, ideally the output should be a faithful reproduction of the input. This is called
fidelity. Of course there could be changes in the amplitude levels. However in practice this never
happens. The output waveform tends to be different from the input. This is called as thedistortion.
The distortion may arise either from the inherent non – linearity in the transistor characteristics or
from the influence of the associated circuit.
This is produced when the operation is over the non-linear part of the transfer characteristics of the
transistor. (A plot between output v/s input is called as the transfer characteristics). Since the
amplifier amplifies different parts of the input differently. For example, there can be compression
of the positive half cycle and expansion of the negative half cycle. Sometimes, the waveform can
become clipped also. (Flattening at the tips). Such a deviation from linear amplification produces
frequencies in the output, which are not originally present in the output. Harmonics (multiples) of
the input signal frequency are present in the output. The percentage harmonic distortion for the nth
Harmonic is given by
DT =
A distortion factor meter measures the total distortion. The spectrum or wave analyzer can be used
to measure the amplitude of each harmonic.
FREQUENCY DISTORTION:
A practical signal is usually complex (containing many frequencies). Frequency distortion occurs
when the different frequency components in the input signal are amplified differently. This is due
to the various frequency dependent reactances (capacitive & inductive) present in the circuit or the
active devices (BJT or FET).
PHASE DISTRIBUTION:
This occurs due to different frequency components of the input signal suffering different phase
shifts. The phase shifts are also due to reactive effects and the active devices. This causes problems
in TV picture reception. To avoid this amplifier phase shift should be proportional to the frequency.
INTERMODULATION DISTORTION:
The harmonics introduced in the amplifier can combine with each other or with the original
frequencies to produce new frequencies to produce new frequencies that are not harmonics of the
fundamental. This is called inter modulation distortion. This distortion results in unpleasant
hearing.
Frequency response of an amplifier is a plot between gain & frequency. If the gain is constant
(same) for all frequencies of the input signal, then this plot would be a flat line. But this never
happens in practice.
As explained earlier, there are different reactive effects present in the amplifier circuit and the
active devices used. Infact there are external capacitors used for blocking, capacitors etc. Also, in
tuned amplifiers, resonant LC circuits are connected in the collector circuits of the amplifier to get
narrow band amplification around the resonant frequencies.
Usually the frequency response of an amplifier is divided into three regions. (i) The mid band
region or flat region, over which the gain is constant (ii) The lower frequency region. Here the
amplifier behaves like a high pass filter, which is shown below.
At high frequencies, the reactance of C1 will be small & hence it acts as a short without any
attenuation (reduction in signal voltage) (iii) In the high frequency region above mid band, the
circuit often behaves like the low pass filter as shown below.
66
As the frequency is increased, the reactance of C2 decreases. Hence more voltage is dropped across
Rs and less is available at the output. Thus the voltage gain of the amplifier decreases at high
frequencies.
In the frequency below the mid band, the High pass filter as shown above can approximate the
amplifier. This is equal to 3 dB in log scale. For higher frequencies f >> f L, AL tends to unity.
Hence, the magnitude of AVL falls of to 70.7 % of the mid band value at f = fL, Such a frequency is
called the lower cut-off or lower 3 dB frequency.
In the high frequency region, above the mid band , the amplifier stage can be approximated by the
low pass circuit.
The gain & phase plots versus frequency can be approximately sketched by using straight-line
segments called asymptotes. Such plots are called Bode plots. Being in log scale, these plots are
very convenient for evaluation of cascaded amplifiers.
BANDWIDTH:
The range of frequencies from fL to fH is called the bandwidth of the amplifier. The product of mid
band gain and the 3dB Bandwidth of an amplifier is called the Gain-bandwidth product. It is figure
of merit or performance measure for the amplifier.
67
RC COUPLED AMPLIFIER:
Fig. (1) above shows a two stage RC coupled CE amplifier using BJTs where as fig.(2) shows the
FET version. The resistors RC & RB ( = R1R2 / (R1 + R2 ) and capacitors CC form the coupling
network. Because of this, the arrangement is called as RC coupled amplifier. The bypass capacitors
CE (= CS) are used to prevent loss of amplification due to –ve feedback. The junction capacitance
Cj should be taken into account when high frequency operation is considered.
When an ac signal is applied to the input of the I stage, it is amplified by the active device (BJT or
FET) and appears across the collector resistor RC / drain resistor RD. this output signal is connected
to the input of the second stage through a coupling capacitor CC. The second stage doesn’t further
amplification of the signal. In this way, the cascaded stages give a large output & the overall gain
is equal to the product of this individual stage gains.
This analysis is done using h parameter model. Assuming all capacitors are arbitrarily large and
act as ac short circuits across RE. The dc power supply is also replaced by a short circuit. Their h
parameter approximate models replace the transistors.
68
The parallel combination of resistors R1 and R2 is replaced by a single stage resistor RB.
For finding the overall gain of the two stage amplifier, we must know the gains of the individual
stages.
Using the NPN Darlington pair as the example, the collectors of two transistors are connected
together, and the emitter of TR1 drives the base of TR2. This configuration achieves β multiplication
because for a Base current ib, the collector current is β*ib where the current gain is greater than one,
or unity and this is defined as:
But the base current, IB2 is equal to transistor TR1 emitter current, IE1 as the emitter of TR1 is
connected to the base of TR2.
This means that the overall current gain, β is given by the gain of the first transistor multiplied by
the gain of the second transistor as the current gains of the two transistors multiply. In other words, a
pair of bipolar transistors combined together to make a single Darlington transistor pair can be
regarded as a single transistor with a very high value of β and consequently a high input resistance.
POWER AMPLIFIERS
After the audio signal is converted into electrical signal, it has several voltage amplifications done,
after which the power amplification of the amplified signal is done just before the loud speaker stage.
This is clearly shown in the below figure.
70
While the voltage amplifier raises the voltage level of the signal, the power amplifier raises the power
level of the signal. Besides raising the power level, it can also be said that a power amplifier is a
device which converts DC power to AC power and whose action is controlled by the input signal.
The DC power is distributed according to the relation,
DC power input = AC power output + losses
Power Transistor
For such Power amplification, a normal transistor would not do. A transistor that is manufactured to
suit the purpose of power amplification is called as a Power transistor.
A Power transistor differs from the other transistors, in the following factors.
It is larger in size, in order to handle large powers.
The collector region of the transistor is made large and a heat sink is placed at the collector-
base junction in order to minimize heat generated.
The emitter and base regions of a power transistor are heavily doped.
Due to the low input resistance, it requires low input power.
Hence there is a lot of difference in voltage amplification and power amplification. So, let us now try
to get into the details to understand the differences between a voltage amplifier and a power amplifier.
Voltage Amplifier
The function of a voltage amplifier is to raise the voltage level of the signal. A voltage amplifier is
designed to achieve maximum voltage amplification.
The voltage gain of an amplifier is given by
Av=β(RcRin)Av=β(RcRin)
The characteristics of a voltage amplifier are as follows −
The base of the transistor should be thin and hence the value of β should be greater than 100.
The resistance of the input resistor Rin should be low when compared to collector load RC.
The collector load RC should be relatively high. To permit high collector load, the voltage
amplifiers are always operated at low collector current.
The voltage amplifiers are used for small signal voltages.
71
Power Amplifier
The function of a power amplifier is to raise the power level of input signal. It is required to deliver
a large amount of power and has to handle large current.
The characteristics of a power amplifier are as follows −
The base of transistor is made thicken to handle large currents. The value of β being (β > 100)
high.
The size of the transistor is made larger, in order to dissipate more heat, which is produced
during transistor operation.
Transformer coupling is used for impedance matching.
Collector resistance is made low.
The Power amplifiers amplify the power level of the signal. This amplification is done in the last
stage in audio applications. The applications related to radio frequencies employ radio power
amplifiers. But the operating point of a transistor, plays a very important role in determining the
efficiency of the amplifier. The main classification is done based on this mode of operation.
The classification is done based on their frequencies and also based on their mode of operation.
Collector Efficiency
This explains how well an amplifier converts DC power to AC power. When the DC supply is given
by the battery but no AC signal input is given, the collector output at such a condition is observed as
collector efficiency.
The collector efficiency is defined as
η=averagea.cpoweroutputaveraged.cpowerinputtotransistorη=averagea.cpoweroutputaveraged.cpow
erinputtotransistor
For example, if the battery supplies 15W and AC output power is 3W. Then the transistor
efficiency will be 20%.
The main aim of a power amplifier is to obtain maximum collector efficiency. Hence the higher the
value of collector efficiency, the efficient the amplifier will be.
Distortion
A transistor is a non-linear device. When compared with the input, there occur few variations in the
output. In voltage amplifiers, this problem is not pre-dominant as small currents are used. But in
power amplifiers, as large currents are in use, the problem of distortion certainly arises.
Distortion is defined as the change of output wave shape from the input wave shape of the
amplifier. An amplifier that has lesser distortion, produces a better output and hence considered
efficient.
CLASS A POWER AMPLIFIER:
We have already come across the details of transistor biasing, which is very important for the
operation of a transistor as an amplifier. Hence to achieve faithful amplification, the biasing of the
transistor has to be done such that the amplifier operates over the linear region.
A Class A power amplifier is one in which the output current flows for the entire cycle of the AC
input supply. Hence the complete signal present at the input is amplified at the output. Thefollowing
figure shows the circuit diagram for Class A Power amplifier.
73
From the above figure, it can be observed that the transformer is present at the collector as a load.
The use of transformer permits the impedance matching, resulting in the transference of maximum
power to the load e.g. loud speaker.The operating point of this amplifier is present in the linear region.
It is so selected that the current flows for the entire ac input cycle. The below figure explains the
selection of operating point.
The output characteristics with operating point Q is shown in the figure above. Here (Ic)Q and
(Vce)Q represent no signal collector current and voltage between collector and emitter respectively.
When signal is applied, the Q-point shifts to Q1 and Q2. The output current increases to (Ic)max and
decreases to (Ic)min. Similarly, the collector-emitter voltage increases to (Vce)max and decreases to
(Vce)min.
D.C. Power drawn from collector battery Vcc is given by
Pin=voltage×current=VCC(IC)QPin=voltage×current=VCC(IC)Q
This power is used in the following two parts −
(PO)ac=I2RC=V2RC=(Vm2–
√)21RC=V2m2RC(PO)ac=I2RC=V2RC=(Vm2)21RC=Vm22RC
Where I is the R.M.S. value of a.c. output current through load, V is the R.M.S. value of a.c.
voltage, and Vm is the maximum value of V.
The D.C. power dissipated by the transistor (collector region) in the form of heat, i.e., (PC)dc
We have represented the whole power flow in the following diagram.
This class A power amplifier can amplify small signals with least distortion and the output will be
an exact replica of the input with increased strength.
Let us now try to draw some expressions to represent efficiencies.
Overall Efficiency
The overall efficiency of the amplifier circuit is given by
(η)overall=a.cpowerdeliveredtotheloadtotalpowerdeliveredbyd.csupply(η)overall=a.cpowerdelivered
totheloadtotalpowerdeliveredbyd.csupply
=(PO)ac(Pin)dc=(PO)ac(Pin)dc
Collector Efficiency
The collector efficiency of the transistor is defined as
(η)collector=averagea.cpoweroutputaveraged.cpowerinputtotransistor(η)collector=averagea.cpowero
utputaveraged.cpowerinputtotransistor
=(PO)ac(Ptr)dc=(PO)ac(Ptr)dc
Expression for overall efficiency
(PO)ac=Vrms×Irms(PO)ac=Vrms×Irms
=12–√[(Vce)max−(Vce)min2]×12–
√[(IC)max−(IC)min2]=12[(Vce)max−(Vce)min2]×12[(IC)max−(IC)min2]
=[(Vce)max−(Vce)min]×[(IC)max−(IC)min]8=[(Vce)max−(Vce)min]×[(IC)max−(IC)min]8
75
Therefore
(η)overall=[(Vce)max−(Vce)min]×[(IC)max−(IC)min]8×VCC(IC)Q(η)overall=[(Vce)max−(Vce)mi
n]×[(IC)max−(IC)min]8×VCC(IC)Q
Advantages of Class A Amplifiers
The advantages of Class A power amplifier are as follows −
Here R1 and R2 provide potential divider arrangement. The resistor Re provides stabilization, Ce is
the bypass capacitor and Re to prevent a.c. voltage. The transformer used here is a step-down
transformer. The high impedance primary of the transformer is connected to the high impedance
collector circuit. The low impedance secondary is connected to the load (generally loud speaker).
76
Transformer Action
The transformer used in the collector circuit is for impedance matching. R L is the load connected in
the secondary of a transformer. RL’ is the reflected load in the primary of the transformer.
The number of turns in the primary are n1 and the secondary are n2. Let V1and V2 be the primary and
secondary voltages and I1 and I2 be the primary and secondary currents respectively. The below figure
shows the transformer clearly.
We know that
V1V2=n1n2andI1I2=n1n2V1V2=n1n2andI1I2=n1n2
Or
V1=n1n2V2andI1=n1n2I2V1=n1n2V2andI1=n1n2I2
Hence
V1I1=(n1n2)2V2I2V1I1=(n1n2)2V2I2
But V1/I1 = RL’ = effective input resistance
And V2/I2 = RL = effective output resistance
Therefore,
R′L=(n1n2)2RL=n2RLRL′=(n1n2)2RL=n2RL
Where
n=numberofturnsinprimarynumberofturnsinsecondary=n1n2n=numberofturnsinprimarynumberoftur
nsinsecondary=n1n2
A power amplifier may be matched by taking proper turn ratio in step down transformer.
Circuit Operation
If the peak value of the collector current due to signal is equal to zero signal collector current, then
the maximum a.c. power output is obtained. So, in order to achieve complete amplification, the
operating point should lie at the center of the load line.
The operating point obviously varies when the signal is applied. The collector voltage varies in
opposite phase to the collector current. The variation of collector voltage appears across theprimary
of the transformer.
77
Circuit Analysis
The power loss in the primary is assumed to be negligible, as its resistance is very small.
The input power under dc condition will be
(Pin)dc=(Ptr)dc=VCC×(IC)Q(Pin)dc=(Ptr)dc=VCC×(IC)Q
Under maximum capacity of class A amplifier, voltage swings from (Vce)max to zero and current
from (Ic)max to zero.
Hence
Vrms=12–√[(Vce)max−(Vce)min2]=12–√[(Vce)max2]=2VCC22–√=VCC2–
√Vrms=12[(Vce)max−(Vce)min2]=12[(Vce)max2]=2VCC22=VCC2
Irms=12–√[(IC)max−(IC)min2]=12–√[(IC)max2]=2(IC)Q22–√=(IC)Q2–
√Irms=12[(IC)max−(IC)min2]=12[(IC)max2]=2(IC)Q22=(IC)Q2
Therefore,
(PO)ac=Vrms×Irms=VCC2–√×(IC)Q2–
√=VCC×(IC)Q2(PO)ac=Vrms×Irms=VCC2×(IC)Q2=VCC×(IC)Q2
Therefore,
Collector Efficiency = (PO)ac(Ptr)dc(PO)ac(Ptr)dc
Or,
(η)collector=VCC×(IC)Q2×VCC×(IC)Q=12(η)collector=VCC×(IC)Q2×VCC×(IC)Q=12
=12×100=50%=12×100=50%
The efficiency of a class A power amplifier is nearly than 30% whereas it has got improved to 50%
by using the transformer coupled class A power amplifier.
Advantages
The advantages of transformer coupled class A power amplifier are as follows.
When the signal is applied, the circuit is forward biased for the positive half cycle of the input and
hence the collector current flows. But during the negative half cycle of the input, the circuit is reverse
biased and the collector current will be absent. Hence only the positive half cycle is amplified at the
output.
As the negative half cycle is completely absent, the signal distortion will be high. Also, when the
applied signal increases, the power dissipation will be more. But when compared to class A power
amplifier, the output efficiency is increased.
Well, in order to minimize the disadvantages and achieve low distortion, high efficiency and high
output power, the push-pull configuration is used in this class B amplifier.
Construction
The circuit of a push-pull class B power amplifier consists of two identical transistors T1 and
T2 whose bases are connected to the secondary of the center-tapped input transformer Tr1. The
emitters are shorted and the collectors are given the VCC supply through the primary of the output
transformer Tr2.
The circuit arrangement of class B push-pull amplifier, is same as that of class A push-pull
amplifier except that the transistors are biased at cut off, instead of using the biasing resistors. The
figure below gives the detailing of the construction of a push-pull class B power amplifier.
79
Operation
The circuit of class B push-pull amplifier shown in the above figure clears that both the transformers
are center-tapped. When no signal is applied at the input, the transistors T1 and T2 are in cut off
condition and hence no collector currents flow. As no current is drawn from VCC, no power is wasted.
When input signal is given, it is applied to the input transformer Tr1 which splits the signal into two
signals that are 180o out of phase with each other. These two signals are given to the two identical
transistors T1 and T2. For the positive half cycle, the base of the transistor T1 becomes positive and
collector current flows. At the same time, the transistor T2 has negative half cycle, which throws the
transistor T2 into cutoff condition and hence no collector current flows. The waveform is produced
as shown in the following figure.
For the next half cycle, the transistor T1 gets into cut off condition and the transistor T2 gets into
conduction, to contribute the output. Hence for both the cycles, each transistor conducts alternately.
The output transformer Tr3 serves to join the two currents producing an almost undistorted output
waveform.
Idc=(IC)maxπIdc=(IC)maxπ
Therefore,
(pin)dc=2×[(IC)maxπ×VCC](pin)dc=2×[(IC)maxπ×VCC]
Here factor 2 is introduced as there are two transistors in push-pull amplifier.
R.M.S. value of collector current = (IC)max/2–√(IC)max/2
R.M.S. value of output voltage = VCC/2–√VCC/2
Under ideal conditions of maximum power
Therefore,
(PO)ac=(IC)max2–√×VCC2–√=(IC)max×VCC2(PO)ac=(IC)max2×VCC2=(IC)max×VCC2
Now overall maximum efficiency
ηoverall=(PO)ac(Pin)dcηoverall=(PO)ac(Pin)dc
=(IC)max×VCC2×π2(IC)max×VCC=(IC)max×VCC2×π2(IC)max×VCC
=π4=0.785=78.5%=π4=0.785=78.5%
The collector efficiency would be the same.
Hence the class B push-pull amplifier improves the efficiency than the class A push-pull amplifier.
The above circuit employs a NPN transistor and a PNP transistor connected in push pull
configuration. When the input signal is applied, during the positive half cycle of the input signal,
the NPN transistor conducts and the PNP transistor cuts off. During the negative half cycle, the NPN
transistor cuts off and the PNP transistor conducts. In this way, the NPN transistor amplifies during
positive half cycle of the input, while PNP transistor amplifies during negative half cycle of the input.
As the transistors are both complement to each other, yet act symmetrically while being connected
in push pull configuration of class B, this circuit is termed as Complementary symmetry push pull
class B amplifier.
Advantages
The advantages of Complementary symmetry push pull class B amplifier are as follows.
As there is no need of center tapped transformers, the weight and cost are reduced.
Equal and opposite input signal voltages are not required.
81
Disadvantages
The disadvantages of Complementary symmetry push pull class B amplifier are as follows.
It is difficult to get a pair of transistors (NPN and PNP) that have similar characteristics.
We require both positive and negative supply voltages.
Cross-over Distortion
In the push-pull configuration, the two identical transistors get into conduction, one after the other
and the output produced will be the combination of both. When the signal changes or crosses over
from one transistor to the other at the zero voltage point, it produces an amount of distortion to the
output wave shape. For a transistor in order to conduct, the base emitter junction should cross 0.7v,
the cut off voltage. The time taken for a transistor to get ON from OFF or to get OFF from ON state
is called the transition period. At the zero voltage point, the transition period of switching over the
transistors from one to the other, has its effect which leads to the instances where both thetransistors
are OFF at a time. Such instances can be called as Flat spot or Dead band on the outputwave shape.
The above figure clearly shows the cross over distortion which is prominent in the output waveform.
This is the main disadvantage. This cross over distortion effect also reduces the overall peak to peak
value of the output waveform which in turn reduces the maximum power output. This can be more
clearly understood through the non-linear characteristic of the waveform as shown below.
It is understood that this cross-over distortion is less pronounced for large input signals, where as it
causes severe disturbance for small input signals. This cross over distortion can be eliminated if the
conduction of the amplifier is more than one half cycle, so that both the transistors won’t be OFF at
the same time. This idea leads to the invention of class AB amplifier, which is the combination of
both class A and class B amplifiers, as discussed below.
82
Therefore, in class AB amplifier design, each of the push-pull transistors is conducting for slightly
more than the half cycle of conduction in class B, but much less than the full cycle of conduction of
class A. The conduction angle of class AB amplifier is somewhere between 180o to 360o depending
upon the operating point selected. This is understood with the help of below figure.
The small bias voltage given using diodes D1 and D2, as shown in the above figure, helps the operating
point to be above the cutoff point. Hence the output waveform of class AB results as seenin the above
figure. The crossover distortion created by class B is overcome by this class AB, as well the
inefficiencies of class A and B don’t affect the circuit.
So, the class AB is a good compromise between class A and class B in terms of efficiency and
linearity having the efficiency reaching about 50% to 60%. The class A, B and AB amplifiers are
called as linear amplifiers because the output signal amplitude and phase are linearly related to the
input signal amplitude and phase.
83
This kind of biasing gives a much improved efficiency of around 80% to the amplifier, but introduces
heavy distortion in the output signal. Using the class C amplifier, the pulses produced at its output
can be converted to complete sine wave of a particular frequency by using LC circuits in its collector
circuit.
84
Chapter-4
FEEDBACK AMPLIFIERS
Concepts of feedback: Classification of feedback amplifiers, general characteristics of Negative
feedback amplifiers, effect of feedback on amplifier characteristics, voltage series, voltage shunt,
current series and current shunt feedback configurations, simple problems; Oscillators: Condition for
Oscillations, RC type Oscillators RC phase shift and Wien-bridge Oscillators, LC type Oscillators,
generalized analysis of LC Oscillators, Hartley and Colpitts oscillators.
VOLTAGE AMPLIFIER:
The above figure shows a Thevenin’s equivalent circuit of an amplifier. If the input resistance of the
amplifier Ri is large compared with the source resistance Rs, then Vi = Vs. If the external load RL is
large compared with the output resistance R0 of the amplifier, then V0 = AV VS .This type
of amplifier provides a voltage output proportional to the input voltage & the proportionality factor
doesn’t depend on the magnitudes of the source and load resistances. Hence, this amplifier is known
as voltage amplifier. An ideal voltage amplifier must have infinite resistance Ri and zero output
resistance.
85
CURRENT AMPLIFIER:
Above figure shows a Norton’s equivalent circuit of a current amplifier. If the input resistance of
the amplifier Ri is very low compared to the source resistance RS, then Ii = IS. If the output resistance
of the amplifier R0 is very large compared to external load RL, then IL = AiIi = Ai IS. This amplifier
provides an output current proportional to the signal current and the proportionally is dependent
of the source and load resistance. Hence, this amplifier is called a current amplifier. An ideal current
amplifier must have zero input resistance & infinite output resistance.
TRANSCONDUCTANCE AMPLIFIER:
The above figure shows the equivalent circuit of a transconductance amplifier. In this circuit, the
output current I0 is proportional to the signal voltage VS and the proportionality factor is independent
of the magnitudes of source and load resistances. An ideal transconductance amplifier must have an
infinite resistance Ri & infinite output resistance R0.
TRANSRESISTANCE AMPLIFIER:
Figure above shows the equivalent circuit of a transconductance amplifier. Here, the output voltage
V0 is proportional to the signal current IS and the proportionality factor is independent of magnitudes
of source and loads resistances. If RS >>Ri , then Ii = IS , Output voltage V0 = RmIS
An ideal transconductance amplifier must have zero input resistance and zero output resistance.
86
RL
All the input of the amplifier, the feedback signal is combined with the source signal through a unit
called mixer. The signal source shown in the above figure can be either a voltage source VS or a
current source. The feedback connection has three networks.
1. Sampling network
2. Feedback network
3. Mixer network
SAMPLING NETWORK:
There are two ways to sample the output, depending on the required feedback parameter. The output
voltage is sampled by connecting the feedback network in shunt with the output. This is called as
voltage sampling.
87
FEEDBACK NETWORK:
This is usually a passive two-port network consisting of resistors, capacitors and inductors. In case
of a voltage shunt feedback, it provides a fraction of the output voltage as feedback signal Vf to the
input of the mixer.
MIXER:
There are two ways of mixing the feedback signal with the input signal with the input signal as shown
in figure . below.
When the feedback voltage is applied in series with the input voltage through the feedback network
as shown in figure 6.7 (a) above, it is called series mixing. Otherwise, when the feedback voltage is
applied in parallel to the input of the amplifier as shown in figure (b) above, it is called shunt
feedback.
GAIN OR TRANSFER RATIO:
The ratio of the output signal to the input signal of the basic amplifier is represented by the symbol
A , with proper suffix representing the different quantities.
TYPES OF FEEDBACK:
Feedback amplifiers can be classified as positive or negative feedback depending on how the
feedback signal gets added to the incoming signal. If the feedback signal is of the same sign as the
incoming signal, they get added & this is called as positive feedback. On the other hand, if the
feedback signal is in phase inverse with the incoming signal, they get subtracted from each other; it
will be called as negative feedback amplifier. Positive feedback is employed in oscillators whereas
negative feedback is used in amplifiers.
88
The overall gain of the two stage amplifier is reduced by the factor 1 + A1A2β. In addition the
noise output is reduced by the additional factor A1 which is the gain that precedes the introduction
of noise. In a single stage amplifier, noise will be reduced by the factor 1/(1 + Aβ) just like distortion.
But if signal-to-noise ratio has to improve, we have to increase the signal level at the input by the
factor (1 + Aβ) to bring back the signal level to the same value as obtained without feedback. If we
can assume that noise does not further increase when we increase the signal input, we can conclude
that noise is reduced by the factor 1/(1+Aβ) due to feedback while the signal level is maintained
constant.
OSCILLATORS:
An oscillator generates output without any ac input signal. An electronic oscillator is a circuit which
converts dc energy into ac at a very high frequency. An amplifier with a positive feedback can be
understood as an oscillator.
91
The frequency, waveform, and magnitude of a.c. power generated by an amplifier, is controlled by
the a.c. signal voltage applied at the input, whereas those for an oscillator are controlled by the
components in the circuit itself, which means no external controlling voltage is required.
Classification of Oscillators
Electronic oscillators are classified mainly into the following two categories −
Sinusoidal Oscillators − The oscillators that produce an output having a sine waveform are
called sinusoidal or harmonic oscillators. Such oscillators can provide output at frequencies
ranging from 20 Hz to 1 GHz.
Sinusoidal Oscillators
Sinusoidal oscillators can be classified in the following categories −
Tuned Circuit Oscillators − These oscillators use a tuned-circuit consisting of inductors
(L) and capacitors (C) and are used to generate high-frequency signals. Thus they are also
known as radio frequency R.F. oscillators. Such oscillators are Hartley, Colpitts, Clapp-
oscillators etc.
RC Oscillators − There oscillators use resistors and capacitors and are used to generate low
or audio-frequency signals. Thus they are also known as audio-frequency (A.F.) oscillators.
Such oscillators are Phase –shift and Wein-bridge oscillators.
Crystal Oscillators − These oscillators use quartz crystals and are used to generate highly
stabilized output signal with frequencies up to 10 MHz. The Piezo oscillator is an example of
a crystal oscillator.
Negative-resistance Oscillator − These oscillators use negative-resistance characteristic of
the devices such as tunnel devices. A tuned diode oscillator is an example of a negative-
resistance oscillator.
Damped Oscillations
The electrical oscillations whose amplitude goes on decreasing with time are called as Damped
Oscillations. The frequency of the damped oscillations may remain constant depending upon the
circuit parameters.
Damped oscillations are generally produced by the oscillatory circuits that produce power losses and
doesn’t compensate if required.
Undamped Oscillations
The electrical oscillations whose amplitude remains constant with time are called as Undamped
Oscillations. The frequency of the Undamped oscillations remains constant.
93
Undamped oscillations are generally produced by the oscillatory circuits that produce no power losses
and follow compensation techniques if any power losses occur. An Oscillator circuit is a complete
set of all the parts of circuit which helps to produce the oscillations. These oscillations should sustain
and should be Undamped as just discussed before. Let us try to analyze a practical Oscillator circuit
to have a better understanding on how an Oscillator circuit works.
From the above figure, the gain of the amplifier is represented as A. The gain of the amplifier is the
ratio of output voltage Vo to the input voltage Vi. The feedback network extracts a voltage Vf = β Vo
from the output Vo of the amplifier.
This voltage is added for positive feedback and subtracted for negative feedback, from the signal
voltage Vs.
So, for a positive feedback,
Vi = Vs + Vf = Vs + β Vo
The quantity β = Vf/Vo is called as feedback ratio or feedback fraction.
The output Vo must be equal to the input voltage (Vs + βVo) multiplied by the gain A of the
amplifier.
Hence,
(Vs+βVo)A=Vo(Vs+βVo)A=Vo Or
AVs+AβVo=VoAVs+AβVo=Vo Or
AVs=Vo(1−Aβ)AVs=Vo(1−Aβ)
Therefore , VoVs=A1−AβVoVs=A1−Aβ
Let Af be the overall gain (gain with the feedback) of the amplifier. This is defined as the ratio of
output voltage Vo to the applied signal voltage Vs, i.e.,
Af=OutputVoltageInputSignal
Voltage=VoVsAf=OutputVoltageInputSignalVoltage=VoVs
from the above two equations, we can understand that, the equation of gain of the feedback
amplifier with positive feedback is given by
Af=A1−AβAf=A1−Aβ
Where Aβ is the feedback factor or the loop gain.
95
If Aβ = 1, Af = ∞. Thus the gain becomes infinity, i.e., there is output without any input. In another
words, the amplifier works as an Oscillator.
The condition Aβ = 1 is called as Barkhausen Criterion of oscillations. This is a very important
factor to be always kept in mind, in the concept of Oscillators.
Tuned circuit oscillators are the circuits that produce oscillations with the help of tuning circuits.
The tuning circuits onsists of an inductance L and a capacitor C. These are also known as LC
oscillators, resonant circuit oscillators or tank circuit oscillators.
The tuned circuit oscillators are used to produce an output with frequencies ranging from 1 MHz to
500 MHz Hence these are also known as R.F. Oscillators. A BJT or a FET is used as an amplifier
with tuned circuit oscillators. With an amplifier and an LC tank circuit, we can feedback a signal
with right amplitude and phase to maintain oscillations.
Tuned base Oscillator − It uses inductive feedback. But the LC circuit is in the base circuit.
Construction
In the circuit diagram of a Hartley oscillator shown below, the resistors R1, R2and Re provide
necessary bias condition for the circuit. The capacitor Ce provides a.c. ground thereby providing any
signal degeneration. This also provides temperature stabilization. The capacitors Cc and Cb are
employed to block d.c. and to provide an a.c. path. The radio frequency choke (R.F.C) offers very
high impedance to high frequency currents which means it shorts for d.c. and opens for a.c. Hence
it provides d.c. load for collector and keeps a.c. currents out of d.c. supply source
96
Tank Circuit
The frequency determining network is a parallel resonant circuit which consists of the inductorsL1
and L2 along with a variable capacitor C. The junction of L1and L2 are earthed. The coil L1 has its
one end connected to base via Cc and the other to emitter via Ce. So, L2 is in the output circuit. Both
the coils L1 and L2 are inductively coupled and together form an Auto-transformer. The following
circuit diagram shows the arrangement of a Hartley oscillator. The tank circuit is shunt fed in this
circuit. It can also be a series-fed.
Operation
When the collector supply is given, a transient current is produced in the oscillatory or tank circuit.
The oscillatory current in the tank circuit produces a.c. voltage across L1. The auto- transformer
made by the inductive coupling of L1 and L2 helps in determining the frequency and establishes the
feedback. As the CE configured transistor provides 180o phase shift, another 180o phase shift is
provided by the transformer, which makes 360o phase shift between the inputand output voltages.
This makes the feedback positive which is essential for the condition of oscillations. When the loop
gain |βA| of the amplifier is greater than one, oscillations aresustained in the circuit.
Frequency
The equation for frequency of Hartley oscillator is given as
f=12πLTC−−−−√f=12πLTC
LT=L1+L2+2MLT=L1+L2+2M
Here, LT is the total cumulatively coupled inductance; L1 and L2 represent inductances of 1st and
2nd coils; and M represents mutual inductance. Mutual inductance is calculated when two windings
are considered.
97
Advantages
The advantages of Hartley oscillator are
Instead of using a large transformer, a single coil can be used as an auto-transformer.
Frequency can be varied by employing either a variable capacitor or a variable inductor.
Less number of components are sufficient.
The amplitude of the output remains constant over a fixed frequency range.
Disadvantages
The disadvantages of Hartley oscillator are
Construction
Let us first take a look at the circuit diagram of a Colpitts oscillator.
98
The resistors R1, R2 and Re provide necessary bias condition for the circuit. The capacitor Ce
provides a.c. ground thereby providing any signal degeneration. This also provides temperature
stabilization. The capacitors Cc and Cb are employed to block d.c. and to provide an a.c. path. The
radio frequency choke (R.F.C) offers very high impedance to high frequency currents which means
it shorts for d.c. and opens for a.c. Hence it provides d.c. load for collector and keeps a.c. currents
out of d.c. supply source.
Tank Circuit
The frequency determining network is a parallel resonant circuit which consists of variable capacitors
C1 and C2 along with an inductor L. The junction of C1and C2 are earthed. The capacitor C1 has its
one end connected to base via Cc and the other to emitter via Ce. the voltage developed across C1
provides the regenerative feedback required for the sustained oscillations.
Operation
When the collector supply is given, a transient current is produced in the oscillatory or tank circuit.
The oscillatory current in the tank circuit produces a.c. voltage across C1 which are applied to the
base emitter junction and appear in the amplified form in the collector circuit and supply losses to
the tank circuit. If terminal 1 is at positive potential with respect to terminal 3 at any instant, then
terminal 2 will be at negative potential with respect to 3 at that instant because terminal 3 is grounded.
Therefore, points 1 and 2 are out of phase by 180o. As the CE configured transistor provides 180o
phase shift, it makes 360ophase shift between the input and output voltages. Hence, feedback is
properly phased to produce continuous Undamped oscillations. When the loop gain
|βA| of the amplifier is greater than one, oscillations are sustained in the circuit.
Frequency
The equation for frequency of Colpitts oscillator is given as
f=12πLCT−−−−√f=12πLCT
CT is the total capacitance of C1 and C2 connected in series.
1CT=1C1+1C21CT=1C1+1C2
CT=C1×C2C1+C2CT=C1×C2C1+C2
Advantages
The advantages of Colpitts oscillator are as follows −
The Colpitts oscillator is designed to eliminate the disadvantages of Hartley oscillator and is known
to have no specific disadvantages. Hence there are many applications of a colpitts oscillator.
Applications
The applications of Colpitts oscillator are as follows −
Drawbacks of LC circuits
Though they have few applications, the LC circuits have few drawbacks such as
Frequency instability
Waveform is poor
Cannot be used for low frequencies
Inductors are bulky and expensive
We have another type of oscillator circuits, which are made by replacing the inductors with resistors.
By doing so, the frequency stability is improved and a good quality waveform is obtained. These
oscillators can also produce lower frequencies. As well, the circuit becomes neither bulkynor
expensive. All the drawbacks of LC oscillator circuits are thus eliminated in RC oscillator circuits.
Hence the need for RC oscillator circuits arise. These are also called as Phase–shift Oscillators.
The output voltage V1’ across the resistor R leads the input voltage applied input V1 by some phase
angle ɸo. If R were reduced to zero, V1’ will lead the V1 by 90o i.e., ɸo = 90o. However, adjusting R
to zero would be impracticable, because it would lead to no voltage across R. Therefore, in practice,
R is varied to such a value that makes V1’ to lead V1 by 60o. The following circuit diagramshows the
three sections of the RC network.
Each section produces a phase shift of 60o. Consequently, a total phase shift of 180o is produced,
i.e., voltage V2 leads the voltage V1 by 180o.
Construction
The phase-shift oscillator circuit consists of a single transistor amplifier section and a RC phase- shift
network. The phase shift network in this circuit, consists of three RC sections. At the resonant
frequency fo, the phase shift in each RC section is 60o so that the total phase shift produced by RC
network is 180o. The following circuit diagram shows the arrangement of an RC phase-shiftoscillator.
101
The circuit when switched ON oscillates at the resonant frequency fo. The output Eo of the amplifier
is fed back to RC feedback network. This network produces a phase shift of 180o and a voltage
Ei appears at its output. This voltage is applied to the transistor amplifier.
Advantages
The advantages of RC phase shift oscillator are as follows −
Construction
The circuit construction of Wien bridge oscillator can be explained as below. It is a two-stage
amplifier with RC bridge circuit. The bridge circuit has the arms R1C1, R3, R2C2 and the tungsten
lamp Lp. Resistance R3 and the lamp Lp are used to stabilize the amplitude of the output. The following
circuit diagram shows the arrangement of a Wien bridge oscillator.
102
The transistor T1 serves as an oscillator and an amplifier while the other transistor T2 serves as an
inverter. The inverter operation provides a phase shift of 180o. This circuit provides positive
feedback through R1C1, C2R2 to the transistor T1 and negative feedback through the voltage divider
to the input of transistor T2. The frequency of oscillations is determined by the series element
R1C1 and parallel element R2C2 of the bridge.
f=12πR1C1R2C2−−−−−−−−−√f=12πR1C1R2C2
If R1 = R2 and C1 = C2 = C
Then,
f=12πRCf=12πRC
Now, we can simplify the above circuit as follows −
The oscillator consists of two stages of RC coupled amplifier and a feedback network. The voltage
across the parallel combination of R and C is fed to the input of amplifier 1. The net phase shift
through the two amplifiers is zero. The usual idea of connecting the output of amplifier 2 to amplifier
1 to provide signal regeneration for oscillator is not applicable here as the amplifier 1 willamplify
signals over a wide range of frequencies and hence direct coupling would result in poor frequency
stability. By adding Wien bridge feedback network, the oscillator becomes sensitive to a particular
frequency and hence frequency stability is achieved.
Operation
When the circuit is switched ON, the bridge circuit produces oscillations of the frequency stated
above. The two transistors produce a total phase shift of 360o so that proper positive feedback is
ensured. The negative feedback in the circuit ensures constant output. This is achieved by
temperature sensitive tungsten lamp Lp. Its resistance increases with current. If the amplitude of the
output increases, more current is produced and more negative feedback is achieved. Due to this, the
output would return to the original value. Whereas, if the output tends to decrease, reverse action
would take place.
103
Advantages
The advantages of Wien bridge oscillator are as follows −
The circuit provides good frequency stability.
It provides constant output.
The operation of circuit is quite easy.
The overall gain is high because of two transistors.
The frequency of oscillations can be changed easily.
The amplitude stability of the output voltage can be maintained more
accurately, byreplacing R2 with a thermistor.
Disadvantages
The disadvantages of Wien bridge oscillator are as follows −
The circuit cannot generate very high frequencies.
Two transistors and number of components are required for the circuit construction.
104
Chapter-5
OPERATIOANL AMPLIFIERS
Ideal op-amp, Output offset voltage, input bias current, input offset current, slew rate, gain
bandwidth product, Inverting and non-inverting amplifier, Differentiator, integrator, Square-
wave and triangular-wave generators.
Introduction to Operational amplifiers:
An electronic circuit is a group of electronic components connected for a specific purpose.
A simple electronic circuit can be designed easily because it requires few discrete electronic
components and connections. However, designing a complex electronic circuit is difficult, as it
requires more number of discrete electronic components and their connections. It is also time
taking to build such complex circuits and their reliability is also less. These difficulties can be
overcome with Integrated Circuits.
Note that the common mode gain, AcAc of an op-amp is the ratio of the common mode
output voltage and the common mode input voltage.
Slew Rate
Slew rate of an op-amp is defined as the maximum rate of change of the output voltage dueto a
step input voltage.
Mathematically, slew rate (SR) can be represented as −
SR=MaximumofdV0dtSR=MaximumofdV0dt
Where, V0V0 is the output voltage. In general, slew rate is measured in
either V/μSecV/μSec or V/mSecV/mSec.
Types of Operational Amplifiers
An op-amp is represented with a triangle symbol having two inputs and one output.
Op-amps are of two types: Ideal Op-Amp and Practical Op-Amp.
They are discussed in detail as given below −
Ideal Op-Amp
An ideal op-amp exists only in theory, and does not exist practically. The equivalentcircuit
of an ideal op-amp is shown in the figure given below −
Practical Op-Amp
Practically, op-amps are not ideal and deviate from their ideal characteristics because of some
imperfections during manufacturing. The equivalent circuit of a practical op-amp is shown in
the following figure −
107
When you choose a practical op-amp, you should check whether it satisfies the following
conditions −
Input impedance, ZiZi should be as high as possible.
Output impedance, Z0Z0 should be as low as possible.
Open loop voltage gain, AvAv should be as high as possible.
Output offset voltage should be as low as possible.
A circuit is said to be linear, if there exists a linear relationship between its input and the output.
Similarly, a circuit is said to be non-linear, if there exists a non-linear relationship between its
input and output. Op-amps can be used in both linear and non-linear applications. The following
are the basic applications of op-amp −
Inverting Amplifier
Non-inverting Amplifier
Voltage follower
Inverting Amplifier
An inverting amplifier takes the input through its inverting terminal through a resistor R1R1,and
produces its amplified version as the output. This amplifier not only amplifies the input but also
inverts it (changes its sign).
108
Note that for an op-amp, the voltage at the inverting input terminal is equal to the voltage at its
non-inverting input terminal. Physically, there is no short between those two terminalsbut
virtually, they are in short with each other. In the circuit shown above, the non- inverting input
terminal is connected to ground. That means zero volts is applied at the non- inverting input
terminal of the op-amp. According to the virtual short concept, the voltage at the inverting input
terminal of an op-amp will be zero volts.
The nodal equation at this terminal's node is as shown below −
0−ViR1+0−V0Rf=00−ViR1+0−V0Rf=0
=>−ViR1=V0Rf=>−ViR1=V0Rf
=>V0=(−RfR1)Vt=>V0=(−RfR1)Vt
=>V0Vi=−RfR1=>V0Vi=−RfR1
The ratio of the output voltage V0V0 and the input voltage ViVi is the voltage-gain or gain of the
amplifier. Therefore, the gain of inverting amplifier is equal to −RfR1−RfR1.
Note that the gain of the inverting amplifier is having a negative sign. It indicates that there exists
a 1800 phase difference between the input and the output.
Non-Inverting Amplifier
A non-inverting amplifier takes the input through its non-inverting terminal, and producesits
amplified version as the output. As the name suggests, this amplifier just amplifies the input,
without inverting or changing the sign of the output. The circuit diagram of a non- inverting
amplifier is shown in the following figure −
In the above circuit, the input voltage ViVi is directly applied to the non-inverting input terminal
of op-amp. So, the voltage at the non-inverting input terminal of the op-amp willbe ViVi. By
using voltage division principle, we can calculate the voltage at the inverting input terminal of
the op-amp as shown below −
=>V1=V0(R1R1+Rf)=>V1=V0(R1R1+Rf)
According to the virtual short concept, the voltage at the inverting input terminal of an op-amp
is same as that of the voltage at its non-inverting input terminal.
=>V1=Vi=>V1=Vi
=>V0(R1R1+Rf)=Vi=>V0(R1R1+Rf)=Vi
=>V0Vi=R1+RfR1=>V0Vi=R1+RfR1
=>V0Vi=1+RfR1=>V0Vi=1+RfR1
109
Now, the ratio of output voltage V0V0 and input voltage ViVi or the voltage-gain or gain ofthe
non-inverting amplifier is equal to 1+RfR11+RfR1. Note that the gain of the non- inverting
amplifier is having a positive sign. It indicates that there is no phase difference between the input
and the output.
Integrator and Differentiator:
The electronic circuits which perform the mathematical operations such as differentiation and
integration are called as differentiator and integrator, respectively. This chapter discusses in detail
about op-amp based differentiator and integrator. Please note that these also come under linear
applications of op-amp.
Differentiator
A differentiator is an electronic circuit that produces an output equal to the first derivativeof
its input. This section discusses about the op-amp based differentiator in detail.
An op-amp based differentiator produces an output, which is equal to the differential ofinput
voltage that is applied to its inverting terminal. The circuit diagram of an op-amp based
differentiator is shown in the following figure −
In the above circuit, the non-inverting input terminal of the op-amp is connected to ground.That
means zero volts is applied to its non-inverting input terminal.
According to the virtual short concept, the voltage at the inverting input terminal of opampwill
be equal to the voltage present at its non-inverting input terminal. So, the voltage at the inverting
input terminal of op-amp will be zero volts.
The nodal equation at the inverting input terminal's node is −
Cd(0−Vi)dt+0−V0R=0Cd(0−Vi)dt+0−V0R=0
=>−CdVidt=V0R=>−CdVidt=V0R
=>V0=−RCdVidt=>V0=−RCdVidtIf
RC=1secRC=1sec, then the output voltage V0V0 will be −
V0=−dVidtV0=−dVidt
Thus, the op-amp based differentiator circuit shown above will produce an output, which is the
differential of input voltage ViVi, when the magnitudes of impedances of resistor and capacitor
are reciprocal to each other.
Note that the output voltage V0V0 is having a negative sign, which indicates that there exists a
1800 phase difference between the input and the output.
Integrator
An integrator is an electronic circuit that produces an output that is the integration of the
applied input. This section discusses about the op-amp based integrator.
110
An op-amp based integrator produces an output, which is an integral of the input voltage applied
to its inverting terminal. The circuit diagram of an op-amp based integrator is shown in the
following figure −
In the circuit shown above, the non-inverting input terminal of the op-amp is connected to ground.
That means zero volts is applied to its non-inverting input terminal. Accordingto virtual
short concept, the voltage at the inverting input terminal of op-amp will be equal to the voltage
present at its non-inverting input terminal. So, the voltage at the invertinginput terminal of op-
amp will be zero volts.
The nodal equation at the inverting input terminal is −
0−ViR+Cd(0−V0)dt=00−ViR+Cd(0−V0)dt=0
=>−ViR=CdV0dt=>−ViR=CdV0dt
=>dV0dt=−ViRC=>dV0dt=−ViRC
=>dV0=(−ViRC)dt=>dV0=(−ViRC)dt
Integrating both sides of the equation shown above, we get −
∫dV0=∫(−ViRC)dt∫dV0=∫(−ViRC)dt
=>V0=−1RC∫Vtdt=>V0=−1RC∫Vtdt
If RC=1secRC=1sec, then the output voltage, V0V0 will be −
V0=−∫VidtV0=−∫Vidt
So, the op-amp based integrator circuit discussed above will produce an output, which is the
integral of input voltage ViVi, when the magnitude of impedances of resistor and capacitor are
reciprocal to each other.
Note − The output voltage, V0V0 is having a negative sign, which indicates that there exists1800
phase difference between the input and the output.
Waveform Generators:
A waveform generator is an electronic circuit, which generates a standard wave. There aretwo
types of op-amp based waveform generators −
Observe that in the circuit diagram shown above, the resistor R1R1 is connected between the
inverting input terminal of the op-amp and its output of op-amp. So, the resistor R1R1 isused
in the negative feedback. Similarly, the resistor R2R2 is connected between the noninverting
input terminal of the op-amp and its output. So, the resistor R2R2 is used inthe positive
feedback path. A capacitor C is connected between the inverting input terminal of the op-amp
and ground. So, the voltage across capacitor C will be the input voltage at this inverting terminal
of op-amp. Similarly, a resistor R3R3 is connected between the non- inverting input terminal
of the op-amp and ground. So, the voltage acrossresistor R3R3 will be the input voltage
at this non-inverting terminal of the op-amp.
The operation of a square wave generator is explained below −
Assume, there is no charge stored in the capacitor initially. Then, the voltage present at
the inverting terminal of the op-amp is zero volts. But, there is some offset voltageat non-
inverting terminal of op-amp. Due to this, the value present at the output of above circuit
will be +Vsat+Vsat.
Now, the capacitor C starts charging through a resistor R1R1. The value present at the
output of the above circuit will change to −Vsat−Vsat, when the voltage across the
capacitor C reaches just greater than the voltage (positive value) across resistor R3R3.
The capacitor C starts discharging through a resistor R1R1, when the output of above
circuit is −Vsat−Vsat. The value present at the output of above circuit will change to
+Vsat+Vsat,when the voltage across capacitor C reaches just less than (more negative)
the voltage (negative value) across resistor R3R3.
Thus, the circuit shown in the above diagram will produce a square wave at the output as shown
in the following figure −
From the above figure we can observe that the output of square wave generator will haveone
of the two values: +Vsat+Vsat and −Vsat−Vsat. So, the output remains at one value for some
duration and then transitions to another value and remains there for some duration. In this way, it
continues.
112
The block diagram of a triangular wave generator contains mainly two blocks: a squarewave
generator and an integrator. These two blocks are cascaded. That means, the output of square
wave generator is applied as an input of integrator. Note that the integration of a square wave is
nothing but a triangular wave. The circuit diagram of an op-amp based triangular wave generator
is shown in the following figure −
We have already seen the circuit diagrams of a square wave generator and an integrator. Observe
that we got the above circuit diagram of an op-amp based triangular wave generator by replacing
the blocks with the respective circuit diagrams in the block diagram of a triangular wave
generator.
BIBLIOGRAPHY
Agarwal, A., & Lang, J. (2005). Foundations of analog and digital electronic circuits.
Elsevier.
Ahmed, S. S. T., & Patil, K. K. (2016, March). Novel breast cancer detection technique for
TMS-India with dynamic analysis approach. In 2016 International Conference on Circuit,
Power and Computing Technologies (ICCPCT) (pp. 1-5). IEEE.
Ahmed, S. S. T., Thanuja, K., Guptha, N. S., & Narasimha, S. (2016, January).
Telemedicine approach for remote patient monitoring system using smart phones with an
economical hardware kit. In 2016 international conference on computing technologies and
intelligent data engineering (ICCTIDE'16) (pp. 1-4). IEEE.
Ahmed, S. T. (2017, June). A study on multi objective optimal clustering techniques for
medical datasets. In 2017 international conference on intelligent computing and control
systems (ICICCS) (pp. 174-177). IEEE.
Ahmed, S. T., & Basha, S. M. (2022). Information and Communication Theory-Source
Coding Techniques-Part II. MileStone Research Publications.
Ahmed, S. T., & Patil, K. K. (2016, October). An investigative study on motifs extracted
features on real time big-data signals. In 2016 International Conference on Emerging
Technological Trends (ICETT) (pp. 1-4). IEEE.
Ahmed, S. T., & Sankar, S. (2020). Investigative protocol design of layer optimized image
compression in telemedicine environment. Procedia Computer Science, 167, 2617-2622.
Ahmed, S. T., & Syed Mohamed, E. (2021). Phonocardiography (PCG) Signal
Optimization and Compression for Low Line Transmission in Telemedicine. In Advances
in Automation, Signal Processing, Instrumentation, and Control (pp. 1127-1137). Springer,
Singapore.
Ahmed, S. T., Ashwini, S., Divya, C., Shetty, M., Anderi, P., & Singh, A. K. (2018). A
hybrid and optimized resource scheduling technique using map reduce for larger
instruction sets. International Journal of Engineering & Technology, 7(2.33), 843-846.
i
Ahmed, S. T., Basha, S. M., Arumugam, S. R., & Kodabagi, M. M. (2021). PATTERN
RECOGNITION: AN INTRODUCTION. MileStone Research Publications.
Ahmed, S. T., Basha, S. M., Arumugam, S. R., & Patil, K. K. (2021). Big Data Analytics
and Cloud Computing: A Beginner's Guide. MileStone Research Publications.
Ahmed, S. T., Koti, M. S., Muthukumaran, V., & Joseph, R. B. (2022). Interdependent
Attribute Interference Fuzzy Neural Network-Based Alzheimer Disease
Evaluation. International Journal of Fuzzy System Applications (IJFSA), 11(3), 1-13.
Ahmed, S. T., Kumar, V. V., Singh, K. K., Singh, A., Muthukumaran, V., & Gupta, D.
(2022). 6G enabled federated learning for secure IoMT resource recommendation and
propagation analysis. Computers and Electrical Engineering, 102, 108210.
Ahmed, S. T., Priyanka, H. K., Attar, S., & Patted, A. (2017, June). Cataract density ratio
analysis under color image processing approach. In 2017 International Conference on
Intelligent Computing and Control Systems (ICICCS) (pp. 178-180). IEEE.
Ahmed, S. T., Sandhya, M., & Sankar, S. (2019). A dynamic MooM dataset processing
under TelMED protocol design for QoS improvisation of telemedicine
environment. Journal of medical systems, 43(8), 1-12.
Ahmed, S. T., Sandhya, M., & Sankar, S. (2019). An optimized RTSRV machine learning
algorithm for biomedical signal transmission and regeneration for telemedicine
environment. Procedia Computer Science, 152, 140-149.
Ahmed, S. T., Sandhya, M., & Sankar, S. (2020). TelMED: dynamic user clustering
resource allocation technique for MooM datasets under optimizing telemedicine
network. Wireless Personal Communications, 112(2), 1061-1077.
Ahmed, S. T., Sankar, S., & Sandhya, M. (2021). Multi-objective optimal medical data
informatics standardization and processing technique for telemedicine via machine
learning approach. Journal of Ambient Intelligence and Humanized Computing, 12(5),
5349-5358.
Ahmed, S. T., Singh, D. K., Basha, S. M., Nasr, E. A., Kamrani, A. K., & Aboudaif, M. K.
(2021). Neural Network Based Mental Depression Identification and Sentiments
Classification Technique From Speech Signals: A COVID-19 Focused Pandemic
Study. Frontiers in public health, 9.
Ahmed, S. T., Sreedhar Kumar, S., Anusha, B., Bhumika, P., Gunashree, M., & Ishwarya,
B. (2018, November). A Generalized Study on Data Mining and Clustering Algorithms.
In International Conference On Computational Vision and Bio Inspired Computing (pp.
1121-1129). Springer, Cham.
Ahmed, S., Guptha, N., Fathima, A., & Ashwini, S. (2021). Multi-View Feature Clustering
Technique for Detection and Classification of Human Actions.
Al-Shammari, N. K., Almansour, H. B., & Syed, M. B. (2021). Development of an
Automatic Contactless Thermometer Alert System Based on GPS and Population
Density. Engineering, Technology & Applied Science Research, 11(2), 7006-7010.
Al-Shammari, N. K., Alshammari, A. S., Albadarn, S. M., Ahmed, S. T., Basha, S. M.,
Alzamil, A. A., & Gabr, A. M. (2021). Development of soft actuators for stroke
rehabilitation using deep learning.
Al-Shammari, N. K., Alzamil, A. A., Albadarn, M., Ahmed, S. A., Syed, M. B.,
Alshammari, A. S., & Gabr, A. M. (2021). Cardiac Stroke Prediction Framework using
ii
Hybrid Optimization Algorithm under DNN. Engineering, Technology & Applied Science
Research, 11(4), 7436-7441.
Al-Shammari, N. K., Syed, T. H., & Syed, M. B. (2021). An Edge–IoT Framework and
Prototype based on Blockchain for Smart Healthcare Applications. Engineering,
Technology & Applied Science Research, 11(4), 7326-7331.
Al-Turjman, F. (Ed.). (2019). Artificial intelligence in IoT. Springer.
Annema, A. J., Nauta, B., Van Langevelde, R., & Tuinhout, H. (2005). Analog circuits in
ultra-deep-submicron CMOS. IEEE journal of solid-state circuits, 40(1), 132-143.
Ashley, K. L. (2002). Analog electronics with LabVIEW. Prentice Hall Professional.
Bandyopadhyay, S. (2020). Straintronics: Digital and analog electronics with strain-
switched nanomagnets. IEEE Open Journal of Nanotechnology, 1, 57-64.
Barnaal, D. (1989). Analog Electronics for Scientific Application. Waveland Press.
Basha, S. M., & Rajput, D. S. (2017, December). Evaluating the impact of feature selection
on overall performance of sentiment analysis. In Proceedings of the 2017 International
Conference on Information Technology (pp. 96-102).
Basha, S. M., & Rajput, D. S. (2018, November). Evaluating the Importance of each
Feature in Classification task. In 2018 8th International Conference on Communication
Systems and Network Technologies (CSNT) (pp. 151-155). IEEE.
Basha, S. M., & Rajput, D. S. (2018). A supervised aspect level sentiment model to predict
overall sentiment on tweeter documents. International Journal of Metadata, Semantics and
Ontologies, 13(1), 33-41.
Basha, S. M., & Rajput, D. S. (2018). Fitting a Neural Network Classification Model in
MATLAB and R for Tweeter Data set. In Proceedings of International Conference on
Recent Advancement on Computer and Communication (pp. 11-18). Springer, Singapore.
Basha, S. M., & Rajput, D. S. (2018). Parsing based sarcasm detection from literal language
in tweets. Recent Patents on Computer Science, 11(1), 62-69.
Basha, S. M., & Rajput, D. S. (2018). Sentiment analysis: using artificial neural fuzzy
inference system. In Handbook of Research on Pattern Engineering System Development
for Big Data Analytics (pp. 130-152). IGI Global.
Basha, S. M., & Rajput, D. S. (2019). A roadmap towards implementing parallel aspect
level sentiment analysis. Multimedia Tools and Applications, 78(20), 29463-29492.
Basha, S. M., & Rajput, D. S. (2019). An innovative topic-based customer complaints
sentiment classification system. International Journal of Business Innovation and
Research, 20(3), 375-391.
Basha, S. M., & Rajput, D. S. (2019). Aspects of Deep Learning: Hyper-Parameter Tuning,
Regularization, and Normalization. In Intelligent Systems (pp. 171-186). Apple Academic
Press.
Basha, S. M., & Rajput, D. S. (2019). Survey on Evaluating the Performance of Machine
Learning Algorithms: Past Contributions and Future Roadmap. In Deep Learning and
iii
Parallel Computing Environment for Bioengineering Systems (pp. 153-164). Academic
Press.
Basha, S. M., Bagyalakshmi, K., Ramesh, C., Rahim, R., Manikandan, R., & Kumar, A.
(2019). Comparative Study on Performance of Document Classification Using Supervised
Machine Learning Algorithms: KNIME. International Journal on Emerging
Technologies, 10(1), 148-153.
Basha, S. M., Balaji, H., Iyengar, N. C. S., & Caytiles, R. D. (2017). A soft computing
approach to provide recommendation on PIMA diabetes. Heart, 106, 19-32.
Basha, S. M., Janet, J., & Balakrishnan, S. (2020). A study on privacy-preserving models
using blockchain technology for IoT. Blockchain, Big Data and Machine Learning, 265-
290.
Basha, S. M., Khare, A., & Gadipalli, J. (2018). Training and deploying churn prediction
model using machine learning algorithms. IJERCSE, 5(4), 59-64.
Basha, S. M., Poluru, R. K., Janet, J., Balakrishnan, S., Santhosh, D. D., & Kousalya, A.
(2020). A Case Study on Data Vulnerabilities in Software Development Lifecycle Model.
In Impact of Digital Transformation on Security Policies and Standards (pp. 13-32). IGI
Global.
Basha, S. M., Priyadharsheni, J. M., Ram, S., & Iyengar, N. C. S. A Study on Natural
Language Processing approaches for Text2Image using Machine Learning Algorithms.
Basha, S. M., Rajput, D. S., & Iyengar, N. C. S. (2019). Conceptual approach to predict
loan defaults using decision trees. In Sentiment Analysis and Knowledge Discovery in
Contemporary Business (pp. 148-161). IGI Global.
Basha, S. M., Rajput, D. S., & Vandhan, V. (2018). Impact of gradient ascent and boosting
algorithm in classification. International Journal of Intelligent Engineering and Systems
(IJIES), 11(1), 41-49.
Basha, S. M., Rajput, D. S., Bhushan, S. B., Poluru, R. K., Patan, R., Manikandan, R., &
Kumar, A. (2019). Recent Trends in Sustainable Big Data Predictive Analytics: Past
Contributions and Future Roadmap. International Journal on Emerging
Technologies, 10(2), 50-59.
Basha, S. M., Rajput, D. S., Iyengar, N. C. S. N., & Caytiles, D. R. (2018). A novel
approach to perform analysis and prediction on breast cancer dataset using R. International
Journal of Grid and Distributed Computing, 11(2), 41-54.
Basha, S. M., Rajput, D. S., Janet, J., Somula, R. S., & Ram, S. (2020). Principles and
Practices of Making Agriculture Sustainable: Crop Yield prediction using Random
Forest. Scalable Computing: Practice and Experience, 21(4), 591-599.
Basha, S. M., Rajput, D. S., Poluru, R. K., Bhushan, S. B., & Basha, S. A. K. (2018).
Evaluating the performance of supervised classification models: decision tree and Naïve
Bayes using KNIME. International Journal of Engineering & Technology, 7(4.5), 248-253.
Basha, S. M., Rajput, D. S., Thabitha, T. P., Srikanth, P., & Kumar, C. P. (2019).
Classification of sentiments from movie reviews using KNIME. In Proceedings of the 2nd
iv
International Conference on Data Engineering and Communication Technology (pp. 633-
639). Springer, Singapore.
Basha, S. M., Zhenning, Y., Rajput, D. S., Caytiles, R. D., & Iyengar, N. C. S. (2017).
Comparative study on performance analysis of time series predictive models. International
Journal of Grid and Distributed Computing, 10(8), 37-48.
Basha, S. M., Zhenning, Y., Rajput, D. S., Iyengar, N. C. S. N., & Caytiles, D. R. (2017).
Weighted fuzzy rule based sentiment prediction analysis on tweets. International Journal
of Grid and Distributed Computing, 10(6), 41-54.
Basha, S. M., Zhenning, Y., Rajput, D. S., SN, I. N. C., & Caytiles, R. D. (2017). Domain
specific predictive analytics: a case study with R. International Journal of Multimedia and
Ubiquitous Engineering, 12(6), 13-22.
Bestelink, E., Niang, K. M., Bairaktaris, G., Maiolo, L., Maita, F., Ali, K., ... & Sporea,
R. A. (2020). Compact source-gated transistor analog circuits for ubiquitous
sensors. IEEE Sensors Journal, 20(24), 14903-14913.
Bhuyan, M. H., Khan, S. S. A., & Rahman, M. Z. (2014). Teaching analog electronics
course for electrical engineering students in cognitive domain. Journal of Electrical
Engineering, the Institute of Engineers Bangladesh (IEB-EE), 40(1-2), 52-58.
Conti, S., Pimpolari, L., Calabrese, G., Worsley, R., Majee, S., Polyushkin, D. K., ... &
Fiori, G. (2020). Low-voltage 2D materials-based printed field-effect transistors for
integrated digital and analog electronics on paper. Nature communications, 11(1), 1-9.
Crecraft, D., & Gergely, S. (2002). Analog Electronics: circuits, systems and signal
processing. Elsevier.
Dutta, S., Manideep, B. C., Basha, S. M., Caytiles, R. D., & Iyengar, N. C. S. N. (2018).
Classification of diabetic retinopathy images by using deep learning models. International
Journal of Grid and Distributed Computing, 11(1), 89-106.
Fathima, S. N., & Ahmed, S. T. Freeware Power Generation Structural Implementation
Strategy using Solar Panels in Parallel Approach.
Fernandez-Canque, H. L. (2016). Analog Electronics Applications: Fundamentals of
Design and Analysis. CRC Press.
Fernandez-Canque, H. L. (2016). Analog Electronics Applications: Fundamentals of
Design and Analysis. CRC Press.
Fiori, G., Neumaier, D., Szafranek, B. N., & Iannaccone, G. (2014). Bilayer graphene
transistors for analog electronics. IEEE Transactions on Electron Devices, 61(3), 729-
733.
Franco, S. (2002). Design with operational amplifiers and analog integrated circuits (Vol.
1988). New York: McGraw-Hill.
Gunashree, M., Ahmed, S. T., Sindhuja, M., Bhumika, P., Anusha, B., & Ishwarya, B.
(2020). A New Approach of Multilevel Unsupervised Clustering for Detecting Replication
Level in Large Image Set. Procedia Computer Science, 171, 1624-1633.
v
Hamilton, S. (2007). An Analog Electronics Companion: basic circuit design for
engineers and scientists. Cambridge University Press.
Hernández-Jayo, U., & García-Zubía, J. (2011). A remote and reconfigurable analog
electronics laboratory based on IVI an LXI technologies. Remote Engineering and
Virtual Instrumentation (REV'2011).
Hickman, I. (1999). Analog circuits cookbook. Elsevier.
Hickman, I. (2013). Analog Electronics: Analog Circuitry Explained. Newnes.
Kallam, S., Basha, S. M., Rajput, D. S., Patan, R., Balamurugan, B., & Basha, S. A. K.
(2018, June). Evaluating the performance of deep learning techniques on classification
using tensor flow application. In 2018 International Conference on Advances in
Computing and Communication Engineering (ICACCE) (pp. 331-335). IEEE.
Kandaswamy, A., & PITTET, A. (2009). Analog Electronics. PHI Learning Pvt. Ltd..
Khadse, V. P., Basha, S. M., Iyengar, N., & Caytiles, R. (2018). Recommendation Engine
for Predicting Best Rated Movies. International Journal of Advanced Science and
Technology, 110, 65-76.
Khaturia, D., Basha, S. M., Iyengar, N., & Caytiles, R. (2018). A Comparative study on
Airline Recommendation System Using Sentimental Analysis on Customer
Tweets. International Journal of Advanced Science and Technology, 111, 107-114.
Kinnera, V. D. R., Basha, S. M., & Iyengar, N. C. S. (2018). Analyze and Visualize Online
Job Posting using KNIME.
Kumar Raja, D. R., & Pushpa, S. (2010). A survey on privacy preserving data mining
techniques. Int J Appl Eng Res, 10.
Kumar Raja, D. R., Hemanth Kumar, G., Basha, S. M., & Ahmed, S. T. (2022).
Recommendations based on Integrated Matrix Time Decomposition and Clustering
Optimization. International Journal of Performability Engineering, 18(4).
Kumar, H. (2019). The Emergence of Artificial Intelligence in Education: at Present and
in Future. Parichay: Maharaja Surajmal Institute Journal of Applied Research, 29.
Kumar, K. V. R., Kumar, K. D., Poluru, R. K., Basha, S. M., & Reddy, M. P. K. (2020).
Internet of things and fog computing applications in intelligent transportation systems.
In Architecture and Security Issues in Fog Computing Applications (pp. 131-150). IGI
Global.
Kumar, S. S., Ahmed, S. T., Vigneshwaran, P., Sandeep, H., & Singh, H. M. (2021). Two
phase cluster validation approach towards measuring cluster quality in unstructured and
structured numerical datasets. Journal of Ambient Intelligence and Humanized
Computing, 12(7), 7581-7594.
LK, S. S., Ahmed, S. T., Anitha, K., & Pushpa, M. K. (2021, November). COVID-19
Outbreak Based Coronary Heart Diseases (CHD) Prediction Using SVM and Risk Factor
Validation. In 2021 Innovations in Power and Advanced Computing Technologies (i-
PACT) (pp. 1-5). IEEE.
LK, S. S., Rana, M., Ahmed, S. T., & Anitha, K. (2021, November). Real-Time IoT Based
Temperature and NPK Monitoring System Sugarcane-Crop Yield for Increasing. In 2021
Innovations in Power and Advanced Computing Technologies (i-PACT) (pp. 1-5). IEEE.
vi
Magdalena, R., Serrano, A. J., MartÍn-Guerrero, J. D., Rosado, A., & Martinez, M.
(2008). A teaching laboratory in analog electronics: Changes to address the bologna
requirements. IEEE Transactions on Education, 51(4), 456-460.
Maheswari, L. K., & Anand, M. M. S. (2009). Analog electronics. PHI Learning Pvt.
Ltd..
Malcher, A., & Falkowski, P. (2014). Analog reconfigurable circuits. International
Journal of Electronics and Telecommunications, 60(1), 15-26.
Mantri, A., Dutt, S., Gupta, J. P., & Chitkara, M. (2008). Design and evaluation of a
PBL-based course in analog electronics. IEEE Transactions on Education, 51(4), 432-
438.
Millman, J., & Halkias, C. C. (1972). Integrated electronics: analog and digital circuits
and systems. Tata McGraw-Hill Education: New Delhi, 44, 45.
MisbahNoorain, N., Ahmed, S. T., Shenoy, H. G., & Ariff, S. (2021, January). Glacier
Monitoring Using Sensor Techniques Powered by Renewable Energy Resources: A
Prototype. In ICASISET 2020: Proceedings of the First International Conference on
Advanced Scientific Innovation in Science, Engineering and Technology, ICASISET
2020, 16-17 May 2020, Chennai, India (p. 367). European Alliance for Innovation.
Murmann, B. (2006). Digitally assisted analog circuits. Ieee Micro, 26(2), 38-47.
Parveen, A., Ahmed, S. T., Gulmeher, R., & Fatima, R. (2021). VANET’s Security,
Privacy and Authenticity: A Study.
Patil, K. K., & Ahmed, S. T. (2014, October). Digital telemammography services for rural
India, software components and design protocol. In 2014 International Conference on
Advances in Electronics Computers and Communications (pp. 1-5). IEEE.
Pavithra, S., Sharma, V., & Ahmed, S. T. Condensed-Sphere Ship Detection on Space
Borne Optical Image Using Machine Learning Approach.
Pease, R. (1991). Troubleshooting analog circuits. Newnes.
Periasamy, K., Periasamy, S., Velayutham, S., Zhang, Z., Ahmed, S. T., & Jayapalan, A.
(2021). A proactive model to predict osteoporosis: An artificial immune system
approach. Expert Systems.
Peyton, A., Walsh, V., & Walsh, Y. (1993). Analog electronics with op-amps: a source
book of practical circuits. Cambridge University Press.
Pittet, A., & Kandaswamy, A. (2009). Analog Electronics. Prentice-Hall of India.
Poluru, R. K., Bhushan, S. B., Muzamil, B. S., Rayani, P. K., & Reddy, P. K. (2019).
Applications of Domain-Specific Predictive Analytics Applied to Big Data. In Sentiment
Analysis and Knowledge Discovery in Contemporary Business (pp. 289-306). IGI Global.
Poluru, R. K., Reddy, M., Basha, S. M., Patan, R., & Kallam, S. (2020). Enhanced adaptive
distributed energy-efficient clustering (EADEEC) for wireless sensor networks. Recent
Advances in Computer Science and Communications (Formerly: Recent Patents on
Computer Science), 13(2), 168-172.
Pooja, P., Sharma, V., & Ahmed, S. T. A Novel Approach for Trust-based Friend
Recommendation in Online Social Network.
vii
Pota, H. R. (1997). Computer-aided analog electronics teaching. IEEE Transactions on
Education, 40(1), 22-35.
Pruthvi, P. R., Patil, U. K., & Ahmed, S. T. (2016). An SVM Approach to Liver Lesion
Border Extraction for Liver Cancer Analysis. American Journal Of Computer Science And
Information Technolog, 4(1).
Raja, D. K., & Pushpa, S. (2017). Feature level review table generation for E-Commerce
websites to produce qualitative rating of the products. Future Computing and Informatics
Journal, 2(2), 118-124.
Raja, D. K., & Pushpa, S. (2019). Diversifying personalized mobile multimedia application
recommendations through the Latent Dirichlet Allocation and clustering
optimization. Multimedia Tools and Applications, 78(17), 24047-24066.
Raja, D. K., Kumar, G. H., & Muppalaneni, N. B. (2022, April). Data Analysis on Wireless
Services using Twitter Data set. In 2022 6th International Conference on Trends in
Electronics and Informatics (ICOEI) (pp. 1670-1673). IEEE.
Raja, D. K., Pushpa, S., & Kumar, B. N. (2016, February). Multidimensional distributed
opinion extraction for sentiment analysis-a novel approach. In 2016 2nd International
Conference on Advances in Electrical, Electronics, Information, Communication and Bio-
Informatics (AEEICB) (pp. 35-39). IEEE.
Rajput, D. S., & Ahmed, S. T. (2022). Evaluating the Performance of Delay Tolerant in
Network Routing Protocols. International Journal of Computational Learning &
Intelligence, 1(1).
Rajput, D. S., Basha, S. M., Xin, Q., Gadekallu, T. R., Kaluri, R., Lakshmanna, K., &
Maddikunta, P. K. R. (2021). Providing diagnosis on diabetes using cloud computing
environment to the people living in rural areas of India. Journal of Ambient Intelligence
and Humanized Computing, 1-12.
Rajput, D. S., Thakur, R. S., & Basha, S. M. (Eds.). (2018). Sentiment Analysis and
Knowledge Discovery in Contemporary Business. IGI Global.
Ramaiah, N. S., & Ahmed, S. T. (2022). An IoT-Based Treatment Optimization and
Priority Assignment Using Machine Learning. ECS Transactions, 107(1), 1487.
Ramírez-Echeverry, J. J., Olarte, A., & García-Carrillo, A. (2014, April). Work in
progress-Role of learning strategies in Electrical Circuits and Analog Electronics courses.
In 2014 IEEE Global Engineering Education Conference (EDUCON) (pp. 1051-1054).
IEEE.
Saggio, G. (2014). Principles of analog electronics. CRC Press.
Sahana, V., Patil, U. K., & Ahmed, S. T. Evaluation of Road Condition in Dense Fog using
in-vehicle Cameras.
Sathiyamoorthi, V., Ilavarasi, A. K., Murugeswari, K., Ahmed, S. T., Devi, B. A., &
Kalipindi, M. (2021). A deep convolutional neural network based computer aided
diagnosis system for the prediction of Alzheimer's disease in MRI
images. Measurement, 171, 108838.
Singh, K. D., & Ahmed, S. T. (2020, July). Systematic Linear Word String Recognition
and Evaluation Technique. In 2020 International Conference on Communication and
Signal Processing (ICCSP) (pp. 0545-0548). IEEE.
viii
Sokolov, D., Dubikhin, V., Khomenko, V., Lloyd, D., Mokhov, A., & Yakovlev, A.
(2017, March). Benefits of asynchronous control for analog electronics: Multiphase buck
case study. In Design, Automation & Test in Europe Conference & Exhibition (DATE),
2017 (pp. 1751-1756). IEEE.
Sreedhar Kumar, S., Ahmed, S. T., & NishaBhai, V. B. Type of Supervised Text
Classification System for Unstructured Text Comments using Probability Theory
Technique. International Journal of Recent Technology and Engineering (IJRTE), 8(10).
Sreedhar Kumar, S., Ahmed, S. T., Mercy Flora, P., Hemanth, L. S., Aishwarya, J.,
GopalNaik, R., & Fathima, A. (2021, January). An Improved Approach of Unstructured
Text Document Classification Using Predetermined Text Model and Probability
Technique. In ICASISET 2020: Proceedings of the First International Conference on
Advanced Scientific Innovation in Science, Engineering and Technology, ICASISET
2020, 16-17 May 2020, Chennai, India (p. 378). European Alliance for Innovation.
Swamy, R., Ahmed, S. T., Thanuja, K., Ashwini, S., Siddiqha, S., & Fathima, A. (2021).
Diagnosing the level of Glaucoma from Fundus Image Using Empirical Wavelet
Transform.
Syed Thouheed Ahmed, S., Sandhya, M., & Shankar, S. (2019). ICT’s role in building and
understanding indian telemedicine environment: A study. In Information and
communication technology for competitive strategies (pp. 391-397). Springer, Singapore.
Teja, K. S., Pravalika, S., Varshitha, G., Basha, S. M., Sriman, N. C., Iyengar, N., &
Caytiles, R. D. (2018). Data Exploration on Overall Suicides Cases Registered Across
India. International Journal of u-and e-Service, Science and Technology, 11(2), 13-28.
Terry, S. C., Blalock, B. J., Jackson, J. R., Chen, S., Mojarradi, M. M., & Kolawa, E. A.
(2003, July). Development of robust analog electronics at the University of Tennessee for
NASA/JPL extreme environment applications. In Proceedings of the 15th Biennial
University/Government/Industry Microelectronics Symposium (Cat. No.
03CH37488) (pp. 124-127). IEEE.
Theetchenya, S., Ramasubbareddy, S., Sankar, S., & Basha, S. M. (2021). Hybrid approach
for content-based image retrieval. International Journal of Data Science, 6(1), 45-56.
Thouheed Ahmed, S., & Sandhya, M. (2019). Real-time biomedical recursive images
detection algorithm for Indian telemedicine environment. In Cognitive informatics and soft
computing (pp. 723-731). Springer, Singapore.
Turchetta, R. (Ed.). (2017). Analog electronics for radiation detection. CRC Press.
Van De Bogart, K. L. (2017). Investigating student learning of analog electronics. The
University of Maine.
Wu, Y., Farmer, D. B., Xia, F., & Avouris, P. (2013). Graphene electronics: Materials,
devices, and circuits. Proceedings of the IEEE, 101(7), 1620-1637.
ix
Textbook on
Analog Electronic Circuits
Principles & Fundamentals
Kumar Raja D R
Syed Thouheed Ahmed
Syed Muzamil Basha
ISBN: 978-93-5636-178-2