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10100

This document contains VHDL code that defines a testbench and entity for testing a 10100 binary sequence detector. The testbench instantiates the 10100 component and defines stimulus processes to input different binary sequences via the din port. It also contains the VHDL code for the 10100 entity which implements a finite state machine with 5 states to detect the 10100 sequence and output a signal on dout.

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Đạt Nguyễn
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21 views7 pages

10100

This document contains VHDL code that defines a testbench and entity for testing a 10100 binary sequence detector. The testbench instantiates the 10100 component and defines stimulus processes to input different binary sequences via the din port. It also contains the VHDL code for the 10100 entity which implements a finite state machine with 5 states to detect the 10100 sequence and output a signal on dout.

Uploaded by

Đạt Nguyễn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY 10100_tb IS

END 10100_tb;

ARCHITECTURE behavior OF 10100_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT 10100

PORT(

clk : IN std_logic;

reset : IN std_logic;

din : IN std_logic;

dout : OUT std_logic

);

END COMPONENT;

--Inputs

signal clk : std_logic := '0';

signal reset : std_logic := '0';


signal din : std_logic := '0';

--Outputs

signal dout : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: da PORT MAP (

clk => clk,

reset => reset,

din => din,

dout => dout

);

-- Clock process definitions

clk_process : process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

-- Stimulus process

stim_proc: process

begin
reset <= '1';

wait for 100 ns;

reset <= '0';

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '0';


wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;

din <= '0';

wait for 10 ns;

din <= '1';

wait for 10 ns;


wait;

end process;

END behavior;

--file chương trình--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity 10100 is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

din : in STD_LOGIC;

dout : out STD_LOGIC);

end 10100;

architecture Behavioral of 10100 is

type state_t is (S0, S1, S2, S3, S4);

signal state: state_t;

signal sequence_detected: boolean := false;

begin

process (clk, reset)

begin

if reset = '1' then

dout <= '0';

state <= S0;

sequence_detected <= false;


elsif rising_edge(clk) then

case state is

when S0 =>

if din = '0' then

state <= S0;

dout <= '0';

else

state <= S1;

dout <= '0';

end if;

when S1 =>

if din = '0' then

state <= S2;

dout <= '0';

else

state <= S1;

dout <= '0';

end if;

when S2 =>

if din = '1' then

state <= S3;

dout <= '0';

else

state <= S0;

dout <= '0';

end if;

when S3 =>

if din = '0' then

state <= S4;


dout <= '0';

else

state <= S1;

dout <= '0';

end if;

when S4 =>

if din = '1' then

state <= S3;

dout <= '0';

else

state <= S0;

dout <= '1';

end if;

when others =>

state <= S0;

dout <= '0';

end case;

end if;

end process;

end Behavioral;

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