Module-4
a.
Explain with a neat diagram, VHDL program structure. (06 Marks)
b. Construct SR gates latch using NAND gates and derive the charecternstiescquation for the
same. (08 Marks)
c. Explain T-fliplop with characteristics equation. (06 Marks)
OR
8 a. Explain with neat diagram, working ofJK flipflop and deriye its characteristic equation.
(08 Marks)
b. Write VHDL code for 4 bit adder. (06 Marks)
c. Explain the application of SR latch in switeh debouncing technique. (06 Marks)
Module-4
7 a. Explain the structure of VHDL program. Write VHDL code for 4-bit parallel adder using
full adder as component. (08 Marks)
b With necessary diagrams, Explain switch debouncing with an S-R latch. (06 Marks)
C. Explain D flip-flop with the help of timing diagram. (06 Marks)
OR
a
Give the implementation of T-flip-flop from D flip-fop. (04 Mars)
b. Explain master-slave J-K flip-flop operation. (08 Marks)
C. Derive the characteristic equations for the following flip-flops:
S-R flip-flop
ii) D-flip flop
ii) T-fip-flop
iv) J-K flip-flop. (08 Marks)
Module-4
7 What are the three different models for writing a module body in VHDL? Give example for
any one model. (06Mark)
b. Derive characteris tic cquation for JK, T, D and SR flip flop. (08 Mak)
Give VHDL code for 4:1 mutiplexer using conditional assign statement. 06 Marks)
OR
8 Using structural model, write VHDL code for Half Adder. (06 Marks)
b
Derive the excitation table for JK and SR flip flop. How SR flip flop is covorted to T flip
flop? (08 Marks)
With logic diagram, xplain JK flip flop. (06 Marks)
Module-4
7 a. What is VHDL? Show how to model the 4-to-l multiplexcr using a VHDL conditoat
assignment statcment. (06 VMarks)
Derive the characteristic cquat ion for S-R flip-flop and J-K flip-lop in product-of suns
form. 06 Mark
What is D flip-flop? lllustrate the opcration of the clear and preset inputs in D-ip-tiop i
timing diagram. (O8 Nlark)
OR
W6 Marks)
8 Show how to construct a VHDL module using an entity architecture pajt
b. Explain switch debouncing with an S-R latch. 6Marks)
What is T lip-flop? Show how to convert D-flip-flop into T-flip-flop (08 Marks)
Module-4
7 a Given that A - "00101101" and B ="10011". Determine the valuc of F
F<=not B&*01|" or A&"" and "1"&A (04 arks)
b Write the complete VHDL code for 4 bit binary adder. (08 Marks)
C. Explain how the VHDL code can be compiled simulated and synthesized ywt eNample
Q8 Marks)
OR
Explain T Flip Flop with truth table. (07 Marks)
b. Explain Master-Slave JK lip flop with neat diagram. (08 Marks)
Write short notes on switch debouncing with an SR Latch. (0S Marks)
Moduje-4
7 a
Write a VHDL module that implemcasa halfadder, a full adder, a half substractor and a
full substractor. (10 Marks)
b Write a VHDL module for 8 to IMUX (05 Marks)
C. Drawthc circuit represented by ahe followitg HDL statements.
F<=E and 1;
|<=G or H:
G<= A and B;
H<=not Cand D: (05 Marks)
OR
a
Explain the working oSR Leh withncat circuit diagram, truth table and timing diagram.
(10 Marks)
b
With a neat logie diagramm. truth table and timing diagram, cxplain the working of J-K
Master Skave
fhp-tlop. (10 Marks)
Module oy.
Explain aith a neat diagtom, VHDL Pavyfa
Strucfaee. OGmay
VHoL Proram sruchue
Giy ard adhitechuee
brity
fhhitechuk chitecheee
mod-a mod .
mod
han we deseibe aSyste in VHOL, e mut
Speciy Cn oahy ard an arckiteCtue at the top level
and alS Spe+ty an archfechuse fr <ach (ornponnt
module)
thot as the pait q the Systems.
A vHOL modue mest have al inputs Aoutpu'
des eilbecd in erty declalaf l qpecihying ta intona
opekahdn the modle uig alchtechue delalai
Genelal forrnt al anthy de laloton.
eny gnhty -name is
Caaut (inteatace -signal-de cloaio hon)
arcl (entNI( eni noma;
Genatal furnat fo rchitechue
arhitechue Grchitec hesenae
[declatoton
besnn
orditechwe bod.
forctitet hue) fastitechwse ramil;
Con Struct SR2 qatey hteh uSihg NNO qates arc
Sane?
desive the chalarteeisies quattog
S- , 2-4 g-0, memory.
S=0, R=4, G-1,90
Case 3; Not usec
Not usec
memn.
Chalacteai shc table chalateisie Kq)
R n
Gplein -fhofop wth chal actesishe s gucitn)
iS also Hnon as 'hoggle tipl
amadifccfon ol he kfiptoç
by conneckng
12K oq-fhee.
rusn toalde toy 1-fip fro p.
K CIK
4
Chanctejshe Rae.
oo
Chaiacteisic Squaton
Giplain oth neat diagans, soorki 3k fkp fig
Ond deive its chalacteiic quahv? cema.
mmony
c|k-, 3:1, keo, G: 4,8-0.
clk-, J=0, k= 1, Q0,g:4.
J=+, k- 1, ©,4,o|... 4,0, 5,0...
Truth table
chal actelinhic tabe
CiK Gnt}
chalacteiic q)
wite VHnL Code for 4 bit addes? osmaks.
port (AB; in bitVecho (3 to onto o).;
: out bitNector(3 downto o);
Co Out bit ):
achitechue Shushg of addeil is.
(omponent fulladdee.
port (xy, Cin: in it
(out, Sum;out bit)
Qnc (oponent.
Signal C: bitvector ( foant 1),
-Foo ; ulloddel Qotmap (6to), sl,cG,c9,St
fAs: Aull aclelee portnap (),90), c), c) SC
A:Aalacdel portmap (Aa),B0J,cco),). SA
fa3:lodeA portnmop (A), Bc), c(),co
apolicahog o SR ktch
explain theAec hiqe. oGmay
dotyounciy
Mechancal Sstch îs
de bownciry suitches ahen
Contart tercl to Vibrae
oponl Or Clas , tte Suortch
Sevea 4ne before
r bounce hen & closed
Sethirg daun to their fhal postton.
noigiangihn, anel this Dorse Con ntet{ue
with the proper opescton a loc Cicut
Mhe int the Suitch ig fig helao iS cONnec
(ogic 4(t1).
to Cotarts a lb 6SSuee that en the Suoitch S
ba tuieen a o t e lath inpts sR wlalwayg
(oqc o, and the \tch OuTput ll not Chg
Sote
U
Sioith
Swid
ata
Page
Palexonse,
Flap(tata ipyop 5LROnt
D Rip
&n
CLK
lCLK DOn+
Ont
1
( Qnt D
STDI
Avai.lable: D £E
D TL T
anlSrafn
0
1
1
Do
DO
Data, SMAt
Poga
HDL
Fotmat d ADL
discápin anguage
HDL - Haxduens sped
L- Vexy hih
VHDL Cincu
hosdaaste deiptien language
Module Name o, the nAedule paxamelon uy
iabut vaiablo
Qutut vauxiable
End module;
TeAt Ciucit
A Tesf
CKT
(OR)
Modue Teat cKT (A,B,Y)
inhut A, B;
OR 'GY,A,B)
End odule
y
Deta
Fepe,
Medule CKTI (A,B,c,D,E,E,G,H,Y)i
input A, B,C,D,E,E,GH
NoR gi( ,A,
NeND4 a , C D);
OR 9(Ws,E,F)
Maáule CKTA (A,B,C,X,Y);
inhut A,B,c
OR gL (w,A,B)
OR 4ala, B,B.c)i
NOR 3(X,, w
NAND 44, w )
End ne&nle
3.
D
ws,w); (Y s XOR
wyD 44u AND
ws,DD; $A
AND
A,) wwe, 9NOR
(wA,BY QLNOR
A,B,CD; inptt
BCiD,
)S (A, CKTQI Module
ET K
X
0 a 0
X
0X
o
