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portant Note 1. On: CBC SISGHENE 21EC32 oe hird Semester B.E. Degree Examination, Jan./Feb. 2023 Digital System Design_using Verilog ‘Max. Marks: 100 m-éach module. Module-1 7 What are combinational circuits?"Give example. Explain c6mbinational circuit with block diagram, (04 Marks) Define canonical form represéntation and solve the following equation using canonical form i) P= fla.b,c) = ab + ac's+ be (08 Marks) (08 Marks) OR Define KeMap solve the followingcexpression using K — Map. i) KAfiw, x, y, 2) =Zm(O, 1,4, 579, 11, 13, 15) ii) _D=fa,b, 0, d)=2m0, 1, 24, 5, 6, 8,9, 12, 13614) (10 Marks) Define Quine-McClusky method and solve, thes following Booléan- expression using Quine-MeClusky method - i) D=fta, b, ©, d) = 3m, 1, 2, 3, 6, 7, 8,9, 2415) ii) K= fw, x, y, 2) =2m(1, 3, 13, 15) awe, 10, 11) (10 Marks) Explain binary*Adders with -migpsand logical representation of equations for SUM and CARRY. (06 Marks) Explaist carry look ahead Adder with General and Sigma block. (06 Marks) Explain working of decimal adder with neat block diagram (take example of BCD addition) ~ (08 Marks) OR’ ‘What are compafatoY circuits? Explain 2-bit magnitude comparators. (08 Marks) Realize the Boolean expression using.3 : 8 decoder and two OR gates i) fi(xo, Xi,.0)= Em(1, 2, 4, 5) ii) f(x, x1, Xé) =Zm(1, 5, 7). (06 Marks) Implement D = (w, x, y, 2)= Zm(0, 1, 2, 4, 5, 7, 8, 9, 12, 13) using 8:1 MUX. (06 Marks) Sie Module-3 Write a note on Mastér Slave JK Flip-Flops with function table and timing diagram. a (08 Marks) What are Edge Triggered Flip-Flops. Explain positive edge Triggered and negative edge Triggered Flip-Flops. (06 Marks) Write characteristic equation for : i) JK Flip-Flop ii) SR Flip-Flop. (06 Marks) << Lof2 10 21EC32 OR a a. Define Counters. Explain Binary Ripple counter with feat diagram. (08 Marks) b. What are Registers? Explain any two classification fegisters with neat block diagram. (06 Marks) c. Design synchronous MOD-6 counter using clocked JK Flip-Flops for sequences 0-2-3-6-5-1. (06 Marks) a, Define HDL and types of HDL. Give structure of verilog mos (06 Marks) b. Explain verilog logical operators with example. (06 Marks) c. i) Write a note on verilog Datatype & ii) Write verilog code for 8x MUX. (08 Marks) OR a. Give classification of Styles(Types) of description with example. (08 Marks) b.. Write verilog code for Full Adder. (06 Marks) ¢. Write a note on Arithmetic and shift, Rotate relational operators with example. (6 Marks) -Module-5 a &:noté on structure of Behavioural Description with example. (08 Marks) b ote on Signal Assignnientjand Variable Assighmént with example. (06 Marks) c. Write a note on sequential statement with examples,“ <> ; (06 Marks) a (06 Marks) ». Explain structural,description with exam = (08 Marks) ¢. Explain structural description of 3-bitRipple Carry Adder. (06 Marks) 20f2 2 CMRIT LIBRARY BANGALORE - 560 037 CECSISCHENE = ird Semester B.E. Degree examination. Jan./Feb. 2023 Digital System Design 18EC34 Max. Marks: 100 ipiswer any FIVE full questions, chogsiig ONE full question fromn.each module. on Mbditle-1 © Convert the Boolean expression to €ahngnical SOP form, f= (xy +2) (y+xZ). (04 Marks) A switching circuit has four inputs A, B, C and D, and o} ut Y. The inputs A and B represent the bits of the numbeNj, whereas the inputs € and D represent the bits of the number Na The output i tobe igh only ithe product Ny = Nz i Tess than 2, Draw the truth table and obtain the Maxterm expression. (06 Marks) Simplify {{A, B, C, E (5, 7, 9, 12, 13, $4, 5, 20, 21, 22, 23, 25, 29, 31) using a S-varible K-map, and the simplified SOP ‘expiession (10 Marks) i ie) Jean expression to canonieal POS form f= (a+b’)(a+e). (04 Marks) eee ‘obtain the simplifi )S expression for Ae =(A+B+ ©) (B#DJTA+C)(B+C). LY (06 Marks) Simplify fa, b, c, d) = 29, 1213) 15) +d (1, 4, ee 11, 14), using QM technique out of several possible solutions, select solution which*vafibe implementediusing only one AND gate and one OR gate. Re ty (10 Marks) z © ° # = 3 a Drawthe cir % 4 decoder haga erable input ance high outs, Give ts th e table. ~~ (04 Marks) b. Construct a 1651 multiplexer usiigbnly 4 * 1 mulkiplesers. (06 Marks) Four chairs A, B, C and D are’laced in a row. When.the chair is empty, it is logic - 0, and when/the,ghair is occupiedsit is logic ~ 1. Design and implement a circuit using 8 * 1 multiplexer IC such that bsiever the adjacent chairs are occupied, the output should go appeal i i 2 Q 4 i é i g high: (10 Marks) 2 ~OR 4° a, Implement a singlé bit binary codparatr circuit using basic gates, and give its truth table. ge 4 Ga (04 Marks) oe b, _Implementthe fnultiple output fnction using a single 3 x 8 decoder IC and additional gates. os fi (@, b, c) =Z(1, 4, 5, 7), f (azb, c) =x (2, 3, 6, 7) (06 Marks) 3 ¢. Derive the expressions a she the complete logic circuit ofa 4-bit look-ahead carry adder. 2 (10 Marks) 5 : Module-3 = 5 a. Draw the ciroyit fated SR latch using NAND gates, and give its truth able. (04 Marks) b. Construct a 4sbit parallel in serial out shift register using negative edge triggered D flip-flops. (06 Marks) 1of3 18EC34 ©, (10 Marks) OR 6 &. Give the compass) etween combinationghgeduential circuits, with one example for each we mash (cantar b. Derive the characteristics equations of SRahd JK flip-flops. (06 Marks) c. Design asbi? binary ripple up-counter using positive edge triggered JK flip-flops. Neatly draw the*timing diagrams, showinghits complete count sequence. Mention the changes to be madesin,the above counter, using thesame flip-flops sogtghit becomes a down-counter. (10 Marks) 7 eeramATY {GALORE - 560.037 t Fig Q7(a) (08 Marks) b. Design a 35bit Synchronous coumter having the repetitive count sequence of 0, 1, 2, 3, 3, 7 using JK flip Hips. Check whether the counter is self correcting. (12 Marks) OR 8 a. Designa mod — ayifbronous binary counter, having the count sequence 0 to 4 and repeat, using D ~ flip- (08 Marks) b. Design a Medly circuit for the state diagram shown in Fig Q8(b), Using JK flip-flops. Use the assignments: A = 00, B= 01 and C= 11. Ay” 20f3 18EC34 (12 Marks) diagram that will deteét-a serial input sequence of 10110 with overlap in a long uence. when the correet input pattern is detected, the output should go high. (10 Marks) b. Design a Mealy'State diagram for the social circuit that coverts a serial excess ~ 3 code to serial BCDycode. The machine has to réturn to the beginning after four bits. The output should. |20uhigh if the input is not a valid’ excess — 3 codes. (10 Marks) ‘ ay SO = © SY ? OR a. Draw the block diagram of postive binary divide? © divide ang raven by a 4-bit divisor to obtain a 4-bit quotient and 4-bit remgindér. Explain the operation briefly. © Ss (10 Marks) S ¢ b. Design a control circuit for a 4-bit serialadder using two sl ister and a full adder. After receiving the statfisignal, the control circuit should give out {Our shift signals and then stop. When the additiois complete, the contents of one of the registers should be replaced by the sum, Draw the State diagram and ‘ait ‘ion table. Design“and realize the circuit using D flip- flops. ; (10 Marks) a. Construct a Mealy S Module F p CMRIT LIBRARY BANGALORE - 560 037 CB COPS HEN Es $ | S 17EC34 jird Semester B.E. Degree cate ation, Jan./Feb. 2023 Digital Ele ics wa lax. Marks: 100 Shing ONE fall. suesion ro each module. a. Construct a truth table and write ® Boolean expression forthe problem statement: An output variable Y is true when thé value of the inputs exceeds?3. Design the logic circuit for the obtained expression (0 Marks) b. What do you mean n bya SOP a POS? Explaijiwith an example. (04 Marks) €. Simplify s= fla, b,6)*E0, 1, 3, 4, 5,6) wsingX-map and draw the logic digram using NAND gates for Syed expression. (06 Marks) & Simpl K-map method. K = flwy, xy, 2) = 200, 1, 3, 4, §, 7,9, 12, 13) + dQ, 8, 10, using QM-method. D =a, , d) = X00, Lae7, 8, 9, 14, 15). Verify the same using K-map method. © S (10 Marks) . SY a Pond Module-2 4. Implement fi(a, b, ©) =E(022, 6) and (a, (1, 3, 7) using 74138, 3:8 decoder IC. (06 Marks) b. With a neat circuit diagram, explain the Baty look ahead ddder with relevant expressions. 4 i (06 Marks) c. Design 2-bit inpiraor using suit ates. (08 Marks) or a Reale Mptintion y= racp= (0, 1, 3, 36,7, 9, 10, 11, 13, 15) using 8:1 Mux. ul, De raw the logic circuit for obtained expressio: (10 Marks) (0 Marks) b. What is'an Encoder? Desfaathnd explain 4:2opriority encoder. (10 Marks) YS . Module-3 ‘x Explain the working of Master-Slave JK-FF with the help of logic diagram. (08 Marks) b. Obtain the charagteristic equations for J-K and T-Flip-Flops (FF). (06 Marks) ©. What is race tround condition” and how it is overcome? Explain with the help of logic diagram. ‘ (06 Marks) OR a. Explain the working Ge SR-latch with the help of logie circuit, Draw the timing diagrams also. (10 Marks) b. Explain the working of +ve edge triggered D-flip-flop with functional table, Draw the timing diagrams of the same. (10 Marks) ? Lof2 17EC34 Modi EN a. Design 4-bit ripple up counter using positive edge RQ Teeter and draw the truth table and timing diagram of the same. (10 Marks) b. Explain the working of 4-bit of twisted ring courier, ith necessary logic diagram, truth table and timing diagrams, oo (Qo Marks) or What is register? Explain 4-bit eriakin,sejt-out unidirectional shift Pegister withthe help of diagram. (Qo Marks) b. Design MOD-6 synchronous counter usifig SR flip-flops (10 Marks) OV dule- a. What are Mealy and Moore Med@ls? Explain. (08 Marks) b. Design 3-bit synchronous u . (12 Marks) ine oy on a. Analyze the followdgp sequential circuit of Find 10(a), by writing input and output equations, sat tele Sd sate diagram (12 Marks) ~ ne: 2V a, astate oni diagram wither example (08 Marks) CMRIT LIBRARY 2of2 BANGALORE - 560 037 nk pages. will be treated as malpractice. — BS answers, compu fication, app 2. Any revealing of tant Note : 1. On completing y CXS Scialils 18EC34 Semester B.E. Degree Examination, June/July 2024 gital System Design Max. Marks: 100 Note: Answer any FIVE full questions, choosing ONE full question from each module. Module. Design a combinational logic circuit’so that an output is-generated indicating when a majority of four inputs is true. (06 Marks) Place the following equations into the proper canonical form. i) flw, x, y,z)= Wx+yz ii) f(A, B,C, D)= A+B+C)A+D) (06 Marks) Using K-map determine ininimal sum of product expressions and implement the simplified equation using only NAND gates fw, x, y, z)=Zm(1, 2, 3, 4, 9) + Ed (10, 11, 12, 13, 14, 15) (08 Marks) oR Define the ‘following terms literal, canonical sum of products, Karnaugh Map, Prime implicatns. (04 Marks) Find the minimal sum of the following Boolean function using Quine McClusky method fw,%y, 2) = E(1, 3, 13, 15) + Ba(8/9, 10, 11) (08 Marks) Using K-map determine minimal-product of sum expression and implement the simplified equation using only NOR gates ffa, b, c, d) = #M@).4,5, 7, 8, 9, 11, 12,43, 15). (08 Marks) : Module. Implement following multiple output function using 74LS138 decoder F.(A,B, C)=Em(I, 4, 5, 7) F(A, B, C) = xin(2;3, 6, 7) (06 Marks) Explain 4-bit carry look ahead adder with necessary diagram and relevant expression. (10 Marks) Implement fla, b, ¢, d) = Em(0,'1,5, 6, 7, 9, 10, 15) usitig 8: | MUX with a, b, ¢ as seléct.lines (04 Marks) OR Implement full adder using 74138 decoder. (06 Marks) Design a 2-bit Magnitude comparator. (08 Marks) Design 4-line to 2 line priority uncoder which gives MSB the highest priority and LSB least priority. (06 Marks) Module-3 What is race around condition? Explain JK master slave flip-flop with diagram function table and timing diagram. (08 Marks) Explain the working of 4-bit Johnson counter using necessary diagram and waveform. (06 Marks) Explain with a neat diagram and truth table, a 4-bit SIPO shift register to store binary number 1010, (06 Marks) 1 of2 10 b, 18EC34 OR Explain the operation of switch debouncer using SR léteh with the help of circuit and waveform, (06 Marks) Explain the working of 3-bit Asynchronous up-down counter with necessary waveform and truth table. (10 Marks) Write the difference between combinational circuits and sequential circuits (04 Marks) Modul Design a synchronous Mod -6 counter using clocked D- Flip-Flop. (10 Marks) Design a Moore type sequence detector to detect a serial input sequence of 101. (10Marks) OR Construct the excitation table, transition table and state diagram for the sequential circuit shown in Fig Q8(a). al at Oas a Lh gle o Suut Fig Q8(a) (10 Marks) Design a synchronous decade counter using'I-flip flop and draw the logic diagram, (10 Marks) SURITLipp ary Module-5 RE - 560 ag, List the guidelines for construction of state graphs. (10 Marks) Design a sequential circuit £0 convert BCD to excess — 3 code with state table state graph and transition table (10 Marks) OR Explain with block diagram design of serial Adder with accumulator. (10 Marks) Explain with block diagram design of Binary multiplier. (10 Marks) tees 20f2 CHES ] 17EC34 ter B.E. Degree Examination, Dec.2023/Jan.2024 Digital Electronics Max. Marks: 100 Note: Answér any FIVE full questions, choosing ONE full question from each module. g Module-1 £ 1 a. Differentiate between : @ i) Combinational and sequential networks. & ii) Prime implicants and essential prime implicants. (04 Marks) g b. Simplify the given Boolean function using K-map method, Obtain minimal SOP expression ne fia, b,c, d) =m (0, 1, 24,5, 7, 9, 12). Draw the logic-diagram using only NAND gates. f= (06 Marks) a ¢. Construct a minimal stim for the following Boolean function using Q-M method and PI table 32 reduction, 22 fia, b, ¢, d) = Zim (1, 3, 13, 15) + Bd (8, 910511). (10 Marks) Be oR 3 2 a. Define the following terms: i) Literal_ ii) Maxterm iii) K-map _iv) Product term. z (04 Marks) a b. Transform the given Boolean fiinction and express the.fesult in decimal notation i) f(a,b,c) = (a +b) (b+ ¢) into maxterm canonical formula. ii) f{a,b, €) = ac + ab Fbe into minterm cationical formula. (06 Marks) ©. Obtain minimal expression for the given functions using K-map i) Minimal product for fla, b, ©, d) = IM (0, 1, 2, 4,5, 7, 9, 12) ii) Minimal sums for fla, b, c) = Zm(0, 2; 3, 4, 5, 7) (10 Marks) 2 3° a. What is magnitude comparator? Design a 1-bit magnitude comparator with the help of neat logic diagram. (06 Marks) b. Design binary full adder. Draw its logic diagram using 2 half adders and an OR gate. (06 Marks) c. Explain the working of bit look ahead carty.with relevant equations and logic diagram. (08 Marks) OR 4 @ Implement f(a, bye, d) = Zm(0, 155, 6 7, 9, 10, 15) using i) 8 x 1 MUX with a, b, ¢ as select lines ii) 4x 1 MUX with a, b as select lines. (08 Marks) b. Realize full subtractor using 3 ~ to ~ 8 line decoder with OR gates. (06 Marks) c. What is priority encoder? Design 4 ~ to —2 line priority encoder with MSB having highest priority and LSB having least priority. (06 Marks) Module-3 2 5 a. Explain the working of master-slave JK flip-flop. Draw the logie diagram using only NAND & gates. : ‘i (08 Marks) b. Explain the operation of switch debouncer circuit using SR latch. Draw necessary waveforms. : (06 Marks) ¢. Obtain characteristic equation for SR and T flip-flops. (06 Marks) 1of2 10 17EC34 or : Explain the working of positive-edge triggered D ‘flip-flop. with the help of neat logic diagram and truth table. (08 Marks) Explain the following timing considerations: ? i) Propagation delay in SR latch ii) Setup and hold time in'gated D latch... Draw necessary waveforms. (06 Marks) Discuss the working principle of gated SR latch with logic diagram and function table. (06 Marks) ‘Modute-~ Explain the operation of SISO arid)SIPO shift registers with an example for each. Draw the logic diagram using 4 clocked D'flip-flops. (06 Marks) Design a 3-bit binary ripplé up counter using positive edge triggered T flip-flops with counting sequence and state diagram. (06 Marks) Design Mod-6 synchronous counter using clocked SR flip-flops for the sequence 0,2,3,6,5, 1 (08 Marks) oR Explain the operation of universal shift register with a neat logic diagram and mode control table. (06 Marks) Design a’4-bit Johnson counter using clocked D flip-flops. (06 Marks) Design a 3+bit synchronous down counter using clocked JK flip-flop. (08 Marks) Module-5 Differentiate between Moore and Mealy model of sequential network. (04 Marks) Construct Mealy state diagram that will detect the input sequence 10110. When input pattern is detected, Z is asserted high. (06 Marks) Design a sequential circuit for the state diagram shown below: Consider the states as 00 — A. O1—B, 10~C and 11 ~D. Use SR flip-flop. (10 Marks) Fig.Q.9(c) Define the following terms: i) State variable ii) Excitation variable iii) Next state iv) Input variable (04 Marks) Design a cyclic Mod4 synchronous binary up counter using D flip-flops. If the input variable x = 0, it remains'in the same state. Otherwise moves to next state. Obtain state table, transition table, excitation table. Draw the logic diagram. (10 Marks) Construct a Moore"machine that counts the occurrences of a sequence ‘abb’ in any input string over {a,b}: (06 Marks) CMRIT LIBRARY BANGALORE - 960 037 wee 20f2 CBESISCRENE LLL 21EC32 semester B.E. Degree Examination, Dec.2023/Jan.2024 Lgroral System Design using Verilog Max. Marks: 100 Note: Answer any FIVE full questions, choosing ONE full question from each module. Module-1 1a. Define the following terms with an example (i) Maxterms (ii) Miniterms (iii) Combinational logic circuit (06 Marks) b. Place the following equations into the proper canonical form (i) P=fla,b, €)= ab’ + ac’ + be (ii) J= (A,B,C, D)=(A+B'+C)(A'+ D) (06 Marks) €. Design a combinational circuit to output the 2°s complement of a 4-bit binary number (08 Marks) OR 2 a. Simplify the following Boolean function by using QM. method: S= flw, x, y, 2) = E(1, 3, 13, 15) + DalB, 9, 10, 11) (08 Marks) b. Obtain the simplified expression for the given four-variable equation using K-map and identify prime implicant and essential prime implicant K= fw, x, y, 2)=5(0, 1,4, 5,9, 11, 13, 15) (06 Marks) ¢. Explain briefly K-map, incompletely specified functions, essential prime implicant. (06 Marks) Module-2 3° a, Implement ffa, b, c,d) = Em(O, 1, 5, 6, 7, 9, 10, 15) using i) 8: 1 MUX with a, b, eas select lines ii) 4 : 1 MUX with a, b as select lines (08 Marks) b. Explain the carry look ahead adder with necessary diagram and relevant expressions. (06 Marks) c. Design 4:2 line priority encoder which gives MSB the highest priority and LSB least priority. (06 Marks) OR 4 a. Design 2-bit comparator using gates. (08 Marks) b. Explain the structure of programmable logic arrays with an example (06 Marks) ¢. List the applications of decoder. Implement a full adder circuit using 3:8 decoder. (06 Marks) Module-3 5 a, Explain Master-Slave SR flipflop with necessary truth table and timing waveforms. (06 Marks) Find characteristic equations for J-K and T flip-flops with the help of funetion tables. (06 Marks) ©. Deseribe with neat diagrams the working and truth table of twisted ring counter and Mod-4 ring counter. (08 Marks) Lof2 Important Note = 1 10 a, b, 21EC32 OR Explain serial-in serial out and serial-in parallel out unidirectional shift register with neat diagrams. (06 Marks) Explain 4 bit synchronous binary counter with necessary timing waveforms, (06 Marks) Design a synchronous Mod-6 counter using clocked JK flipflops. (08 Marks) Module-4 Describe the structure of the vetilog module with an example, (06 Marks) Briefly explain the different data types in verilog. (08 Marks) Write a verilog data flow description for full adder cireuit (06 Marks) oR Write a verilog code for 2:1 miltiplexer with active low enable. (06 Marks) ant declaration is done is verilog, (06 Marks) Discuss the shift operators and bitwise logical operators in verilog with examples. (08 Marks) Explain with an example how signal declaration and con: Module-5 Explain if-else structure and design a behavioral description ofa D-latch using if statement, (06 Marks) Realize 3:8 decoder using verilog behavioral description, (06 Marks) Write a verilog description of a 4 x 4 bit Booth algorithm. (08 Marks) CMRIT LIBRARY OR BANGALORE - 564) 037 Write a structural description ofa Half adder by describing the built in gates in verilog. (06 Marks) Write a verilog structural description of ripple carry adder (06 Marks) Realize binary up/down counter using verilog behavioral description. (08 Marks) 1es on the remaining blank pages. identification, appeal to evaluator and /or equations writen eg, 42+8 ~ 50, will be treated as malpractice. G3CS Stilalls | 18EC34 ester B.E. Degree Examination, Dec.2023/Jan.2024 ital System Design “s Max. Marks: 100 Note: Answer any FIVE full questions, choosing ONE full question from each module. Module-1 Define combinational circuits, POS and SOP with an example, (06 Marks) Draw the truth table for three inputs with output high when MSB and LSB the input is high. ‘Also write the simplified switching equation for the output and realize the logic circuit for the simplified expression using basic gates. (06 Marks) Simplify the logic expression Y(A, B, C, D, E) =3im(5;7, 13, 15, 21, 24, 25, 26, 27) + d(23, 29, 31). Also write the logic circuit for the simplified expression using NAND gate. (08 Marks) oR Convert the'following expression into its canonical form. i) Y=(A+BC) ii) Y= ABC+AD) (06 Marks) Simplify by using K-map Y = xM(0, 4, 5, 7, 8/9, TH, 12, 13, 15)

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