EC 8095- VLSI Design Dept of ECE

EC8095: VLSI DESIGN

UNIT I: INTRODUCTION TO MOS TRANSISTOR

PART A
1. What are the advantages of SiO2 as a dielectric?
SiO2 has a relatively low loss & high dielectric strength, thus application of high gate fields
is possible.

2. State the 3 modes involved in the operation of an enhancement transistor

1. Accumulation mode 2.Depletion mode 3. Inversion mode.

3. What are the factors that influence the drain current?

The distance between source and drain
The channel width
The threshold voltage Vt
The thickness of the gate – insulating oxide layer
The dielectric constant of the gate insulator
The carrier (electron or hole) mobility, µ.

4. Define threshold voltage and state the parameters on which it is dependent on.
(April/May 2019)
Vt can be defined as the voltage applied between gate & source of an MOS device below
which Ids effectively drops to zero. It is a function of
 Gate conductor material
 Gate insulation material
 Gate insulator thickness - channel doping
 Impurities at the silicon insulator interface
 Voltage between the source and the substrate,Vsb.

5. Compare CMOS and BiCMOS technologies.(Nov/Dec 2018)

S.No CMOS Technology Bipolar Technology
.
1. Low static power dissipation High power dissipation
2. High input impedance Low input impedance
3. High packing density Low packing density
4. Low output drive current High output drive
current
5. Drain and source are It is unidirectional
interchangeable
6. High noise margin Low voltage swing
logic

6. Define Body effect. (Nov/Dec 2016)

The threshold voltage Vt is not constant with respect to the voltage difference between the
substrate and the source of the MOS transistor.
So, when several MOS devices are connected in series, the threshold voltage is increased due
to voltage difference between the substrate and the source. This effect of body or substrate
voltage is called body effect.

7. State channel length modulation? Write down the equation for describing the
channel length modulation effect in NMOS transistors. (May/June 2016), (April /
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May 2017)
When an MOS device is in saturation, the effective channel length is decreased such that,
Leff = L - Lshort .Where Lshort= √ 2(εsi/qNa) (Vds – (Vgs – Vt))
The reduction in channel length increases the W/L ratio, thereby increasing β as the drain
voltage increases.

8. Define rise time(tr ).

Tr is the time for a waveform to rise from 10% to 90% of its steady state value.

9. Define noise margin (May/June 2014). Illustrate how it can be obtained from the
transfer characteristics of a CMOS Inverter.(Nov/Dec 2016)
Noise margin is a parameter that allows us to determine the allowable noise voltage on the
input of a gate so that the output will not be affected. The 2 common parameters are N MH&
NML Where
NML = | VILmax – VOLmax| and NMH = | VOHmin – VIHmin|
VIHmin=minimum HIGH input voltage
VILmax = maximum LOW i/p voltage
VOHmin = minimum HIGH o/p voltage
VOLmax= maximum LOW o/p voltage

10. Define fall time ( tf)

Time for a waveform to fall from 90% to 10% of its steady state value.

11. Define delay time,td.

Time difference between input transition and 50% output level .This is the time taken for a
logic transition to pass from input to output. Fig 4.18 (a) Page 207 Weste.

12. Discuss any two layout design rules?(May/June 2014)

The two main approaches for describing layout rules are (i)micron rule (ii) μ- based rules.
Micron design rules give a list of minimum feature sizes and spacing for all the masks
required in a given process. λ- based design rules are based on a single parameter, ‘λ’ which
characterizes the linear feature- the resolution of the complete wafer implementation process

13. Draw the DC transfer characteristics of CMOS inverter? (Nov/Dec 2013),

(April/May 2015), (Nov/Dec 2018)

14. What are the advantages of twin tub process?

Used for protection against latch-up.
Provides separate optimization of p-type & n-type transistors

15. What is BiCMOS?

BiCMOS is the combination of bipolar & CMOS transistors.
To reduce the delay times of the highly loaded signals (microprocessor busses) and to provide
better performance for analog functions the bipolar devices (npn or pnp) can be added to
MOS transistors or vice versa.
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16. What are the advantages of SOI process?

There is no latch-up.
There are no body-effect problems
No field-inversion problems
Lower substrate capacitances provide the possibility for faster cirecuits.
17. What is the objective of the layout rules?(Nov ‘2012)
To obtain a circuit with optimum yield in as small an area as possible without compromising
reliability of the circuit.

18. What are the types of layout design rules?

Micron rule,
Lambda based rule.

19. What is passivation or overglass?

This is a protective glass layer that covers the final chip. Openings are required at pads and
any internal test points.

20. What are the types of oxidation?

 Wet Oxidation: The oxidizing atmosphere contains water vapour
 Dry Oxidation: The oxidizing atmosphere is pure oxygen

21. What are the advantages of EBL pattern generation?

EBL: Electron Beam Lithography
Patterns are derived directly from digital data
There are no intermediate hardware images
Different patterns may be accommodated in different sections of the wafer without difficulty.
Changes to patterns can be implemented quickly.

22. What are the types of etching process?

Isotrophicetch, fullyanisotrophicetch, Preferential etch.

23. What is a thinox?

Thinox is an active mask formed which defines the areas where thin oxide are needed to
implement transistor gates and allow implantation to form P or N-type diffusions for
transistor source/drain regions.

24. What are the non –ideal I-V effects?(May/June 2014)

Velocity Saturation, Channel Length Modulation,Body Effect,Leakage and Temperature
Sensitivity

25. What is propagation delay time t pd? / Define propagation delay of a CMOS inverter.
(May/June 2014), May/June 2016 ), (April / May 2017)

It is the maximum time from the input crossing 50% to the output crossing 50%. It is also
called as Max-time.

26. What is contamination delay time tcd?

It is the minimum time from the input crossing 50% to the output crossing 50%. It is also
called as Min-Time.

27. Give the types of scaling in CMOS technology. (Nov/Dec 2013)

Transistor scaling, Interconnect scaling

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28. Define scaling? What are the advantages of scaling? (Nov/Dec 2013), (April/May
2015), (Nov/Dec 2018)
Scaling of MOS transistor is concerned with systematic reduction of overall dimensions of
the devices as allowed by the available technology, while preserving the geometric ratios
found in the larger devices.

29. What is a stick diagram? (Nov/Dec 2014)

Stick diagrams are commonly used to represent the topology of CMOS integrated circuits.
With a little annotation (FET width and length) they provide adequate information to guide
layout and mask generation.

30. Define lambda based design rules used for layout. (April/May 2015)
λ- based design rules are based on a single parameter, ‘λ’ which characterizes the linear
feature- the resolution of the complete wafer implementation process.

31. What do you mean by design margin?(May/June 2014)

Design Margin required as there are three sources of variation- two environmental and one
Manufacturing which are given as below, Supply Voltage, Operating temperature Process
variation

32. What is threshold voltage?

The threshold voltage is defined as the values of Vgsbelow which Ids becomes zero. In the real
transistor characteristics, sub-threshold current continues to flow for Vgs< Ids. The threshold
voltage varies with L,W, Vds and Vbs .

33. What is latch-up? How to prevent latch-up? (May/June 2016)

Latch-up is the shorting of the VDD & VSS lines in CMOS fabrication process due to
parasitic circuit effect. Latch-up results in chip self-destruction or system failure.
Latch-up can be prevented by usingLatch-up resistant CMOS process and Layout techniques.

34. Sketch the layout of a 2-input NAND gate. (NOV/DEC 2016)

35. Why nMOS transistor is selected as pull down transistor? / Why NMOS device
conducts strong zero and weak one? (Nov/Dec 2017), (Nov/Dec 2018)
When logic 1 is applied as input, nMOS transistor turns ON and PMOS transistor turns
OFF. Hence, the output should get charged to Vdd. But due to threshold voltage effect,
nMOS is not capable of passing Vdd/ good logical 1 at the output. Hence, the output will
be Vdd-Vth.When logic 0 is applied as input, nMOS transistor turns OFF and PMOS
transistor turns ON. Hence, the output should get discharged to ground level. But due to
threshold voltage effect, pMOS is not capable of passing good logical 0 at the output.
Hence, the output will be 0-|Vth|. Suppose, we need to design buffer, we cannot use the
above circuit, rather, we need to cascade two CMOS inverter itself which has pMOS tran-
sistor at its pull up and nMOS transistor at its pull down.Thus, in order to obtain good
logic 0 and logic 1 output, always pull up devices are PMOS and pull down devices
are NMOS.

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36. What is the need for demarcation line? (Nov/Dec 2017)

In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS
must lie on one side of the line and all nMOS will have to be on the other side.

37. What is velocity saturation effect? (Apr/May 2018)

Velocity saturation results in saturation of the current IDSIDS, but occurs mostly in short-
channel MOSFETs (the channel length being smaller than in the previous device).
The velocity of carriers are supposed to vary linearly with the applied electric field as the
mobility is considered to be a constant parameter. However, in a short channel, due to
excessive collisions suffered by the carriers, their velocity saturates after a critical electric
field.
Since current is the rate of flow of electrons, it also attains a saturated value once the
velocity saturates.

38. List the scaling principles? (Apr/May 2018)

There are three types of scaling
Constant Field Scaling :In constant field scaling the scaled devices are obtained by scaling
all dimensions of transistor, device voltages and the doping concentration densities by factor
Constant Voltage Scaling :In constant voltage scaling the supply voltage VDD is kept con-
stant while the process is scaled
Lateral Scaling : In lateral scaling only the gate length is scaled. This is also called as the
"gate shrinking".

39.What are critical paths?

Critical paths are logic paths that require attention to timing details. Designers use a
timing analyzer to find the slowest path in a logic design. Quick delay estimation is
essential to design critical paths.

40.List the levels affecting critical path.

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The architectural / micro architectural level, the logical level, the circuit level,and the
layout level.

41.What are the depending factors for delay of a logic gate?

a. Width of the transistors in the gate.
b. Capacitance of the load that must be driven.

42. How do you determine gate and diffusion capacitance?

Gate capacitance can be determined from the transistor width form the schematic and
diffusion capacitance depends on the layout.

43. Give the equation for elmore delay model./Define Elmore constant. (April / May
2017) (Nov/Dec 2017, Apr/May 2018)

NN
tpd= ∑ Rn-i Ci = ∑ Ci∑ Rj
i=1 j=1

Rn-i = Node in the ladder of resistance Rn-i between the node and a supply.

44. Define logical effort.

Logical effort is defined as the ratio of input capacitance of the gate to that of the input
capacitance of an inverter that can deliver the same output current. It is independent on
the size. It helps to estimate the delay of the entire path quickly based on the parasitic
and logical delay of the path.

45. What is electrical effort?

It is the ratio of load capacitance to input capacitance. It is also called as the fan-out. This
depends on the size.

46. What is parasitic delay?

The parasitic delay of the gate is the delay of the hate when it drives zero load. It can be
estimated with RC delay models.

47. Give the equations that express the delay of a logic gate.
d= f + p , p=> Parasitic delay, f => Effort delay/ Stagg effort
f d= g.h , g => Logical effort , h=> electrical effort/Fan-out
h=Cout / Cin, Cout => Capacitance of the external load being driven.
Cin=>Input capacitance of the gate.

48. What is path delay?

It is the sum of delays of each stage. It is the sum of the path effort delay Dfand path
parasitic delay P.
D=  di = Df+ P, where Df =  fi & P=  Pi

49. Give Elmore delay expression for propagation delay of an inverter.(May/June 2016)
Equivalent circuit of an inverter for the falling transition:

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tpdf=tpdr = 3RC

50. By what factor, gate capacitance must be scaled if constant electric field scaling is
employed? (April/May 2019)
Gate capacitance must be scaled by 1/S factor if constant electric field scaling is employed.
Here ‘S’ is the scaling factor.

51. Draw the stick diagram of static CMOS2-input NAND gate. (NOV/DEC 2018)

PART B-C311.1
1. (a) Explain the operation of a CMOS inverter clearly indicating the various regions of op-
eration.(12)
(b) List the advantages of Lambda based design rules as compared to micronbased design
rules.(4)
2. (a).Discuss the aspects of MOS transistor threshold voltage.(8)
(b) Derive the VTC of CMOS inverter. (8)
3. (a). Discuss the operation of CMOS inverter with diagrams.(8)
(b) Discuss the mead Conway design rules for the silicon gate NMOS process.(8)
4. Explain in detail about the ideal I-V characteristics and non ideal I-V characteristics of
NMOS and PMOS devices and derive its equation.(May/June 2013) (May/June 2016)
(Nov/Dec 2016)(Nov/Dec 2018)
5. (i) Draw and explain the n-well process (10)
(ii) Explain the twin tub process with a neat diagram (6)
6. (i) Discuss the origin of latch up problems in CMOS circuits with necessary diagrams.
Explain the remedial measures. (10)
(i)Explain the electrical properties of MOS transistor in detail (Nov/Dec 2013,
Nov/Dec2017, April/May 2019)
7. Briefly discuss about the CMOS process enhancements and layout design rules.
(May/June 2014)
8. Discuss the steps involved in IC fabrication process (16)
9. Describe n- well process in detail (16) (Nov/Dec 2016)
10. Explain with neat diagrams the SOI process and mention its advantages.(Nov’2012)
11. Discuss the CV characteristics and DC transfer characteristics of the CMOS.
(May/June2014)
12. Explain the various steps involved in the P-well CMOS process with necessarydia-
grams(Nov’2012)
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13. Explain in detail about the scaling concept of CMOS chips and reliability concept(May/
June2013), (April/May 2019)
14. (i) Describe the equation for source to drain current in the three regions of operation of a
MOS transistor and draw the VI characteristics.(May/June 2016)
(ii) Explain in detail about the body effect and its effect in NMOS and PMOS devices
(May/June 2013) (May/June 2016)
15. (i) Explain the DC characteristic of a CMOS inverter with necessary conditions for the
different regions of operation (Nov’2013), (May/June 2016), (April / May 2017)
(ii) Discuss the principles of constant field and lateral scaling. Write the effects of the
above scaling methods on device characteristics. (May/June 2016)
(iii) Draw the layout diagram for NAND and NOR gate. (April / May 2017)
17. Explain the need for scaling principles and fundamentals units of CMOS inverter. (April /
May 2017, Nov/Dec 2017)
18. Write the layout design rules and draw diagram for four input NAND and NOR gate.
(Nov/Dec 2017, Apr/May 2018)
19. Explain the dynamic behaviour of MOSFET with neat diagram. (Apr/May 2018)
20. (i) List out the goals of CMOS technology scaling. Explain How common electric field
scaling is superior than constant voltage scaling. (Nov/Dec 2018)
(ii)Derive the expression to obtain the minimum delay through the chain of CMOS
inverter.(Nov/Dec 2018)
21. (i) Explain the design techniques that are used for larger fan-in device to reduce delay.
(Nov/Dec 2018)
(ii)Draw the small signal model of device during cut-off, linear and saturation region.
(Nov/Dec 2018)
22. Derive an expression for Vin of a CMOS inverter to achieve the condition Vin=Vout.
Whatshould be the relation for βn=βp? (April/May 2019)
23. Derive an expression to show the drain current of MOS for various operating region. Ex-
plainone non-ideality for each operating region that changes the drain current.(Nov/Dec
2018)
24. Explain in detail the CMOS manufacturing process. (Nov/Dec 2018)
25. Obtain the logical effort and path efforts of the given circuit. (Apr/May 2018)

26. Design a 4 input NAND gate and obtain its delay during the transition from high to low.
(Apr/May 2018)
27. Discuss in detail about the various delay models in CMOS technology.
28. Explain the resistive and capacitive delay estimation of CMOS inverter
circuit(May/June2013), (April/May 2019)
29. Find the rising and falling propagation delays of an AND- OR- INVERT gate using the
Elmore delay model (Nov/Dec 2013)

UNIT II: COMBINATIONAL MOS LOGIC CIRCUITS

PART A- C311.2

1. Give the factors that give rise to static power dissipation.(Nov/Dec 2013)
Sub-threshold conduction through off transistors.Tunneling the current through gate ox-
ide.Leakage through reverse biased diodes.Contention current in the ratioed circuits.

2. Give the factors that produce dynamic power dissipation.(Nov/Dec 2013)

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Charging and discharging of load capacitance.

Short term current when both PMOS and NMOS networks are partially ON.

3. Give the formula for static power dissipation

Pstatic = Tstatic VDD

4. Write the formula for dynamic power dissipation.

Pdynamic=C VDD2 fsw
C=> Load capacitance
VDD=> High potential / power
fsw => average frequency

5. How do we reduce dynamic power?

Activity for reduction, Reduction of the inter connect switching capacitance and Choose
lower power supply /operating frequency.

6. State the types of power dissipation. (April/May 2015, Nov/Dec 2017, Apr/May 2018,
Nov/Dec 2018, April/May 2019)
Static power dissipation and Dynamic power dissipation
7. What is a transmission gate?
A transmission gate consists of an n- channel transistor and a p – channel transistor with
separate gate connections and common source and drain connections. It gives good
transmission of both logic 1 and logic 0.

8. Define Transistor Sizing problem. (May/ June 2014)

Transistor sizing, an important problem in designing high performance circuits, has
traditionally been formally defined as
Minimize Area or Power
Subject to Delay _ Tspec:

9. What does the two letters in units denote in SPICE?

The first character indicates the order of magnitude and the second letter indicates a unit
forhuman convenience and is ignored by SPICE.

10. What is a pass transistor? What are its advantages? (Nov 2013)
Pass transistor is similar to a buffer.Advantages of pass transistor are
i .Occupies less space, because any logical operation can be realized with lesser number of
MOS transistors
ii.No direct path between VDD and Gnd. So, amount of power dissipation is lesser
understand by condition.

11. Why is the transmission of logic 1 degraded as it passes through a nmos pass
transistor (Nov/Dec 2016)
When S = 1 (Vdd) , and Vin = 1 the pass transistor begins to conduct and charges the CL
towardsVdd.Initially Vin is at ahigher potential than Vout, the current flows through the
device. As voltage ot the load approaches Vdd – Vtn, the n- device begins to turn – off.
Vtnisthe n- transistor body effected threshold .Thus the transmission of logic 1 is
degraded.

12. List the various power losses in CMOS circuits? (May/June 2013)
Static power loss, Dynamic power loss

13. Write the equation for total static power dissipation.

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n
Ps = ∑ leakage current X supply voltage
1
n = no: of devices

14. What is meant by domino logic ?

Domino logic module consists of a PE logic block followed by an Inverter. This ensures
that all inputs to the next logic block are set to 0 after the precharge period. So, only the
possible transition during the evaluation period is the 0-1 transition.

15. Draw the structure & symbol of a CMOS tri - state inverter.

16. What are the disadvantages of CMOS transmission gates? Draw the symbol for
transmission gate.
Disadvantages of CMOS transmission gate are:
 Require more area than NMOS pass circuits
 Require complemented control signals

T.G symbol

17. List the disadvantages of dynamic logic.

(i) Logic function is implemented by the NMOS pull down network.
(ii) Less no. of transistors required.
(iii) Noise margin doesn’t depend on transistor ratios
(iv) Consumes only dynamic power.
(v) Faster switching speeds.
(vi)
18. What is a transmission gate? Realize a 2-input XOR gate using transmission gates.

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19. What is a pull – down device?

20. State any two criteria for low power logic design? (Nov/Dec 2013)
Supply voltage transistor sizing and clock gating

21. State the advantages of transmission gates. (April / May 2017)

The NMOS only pass transistor can only pass strong zero at the output where as it cannot
pass strong one. Similarly, PMOS only pass transistor can only pass strong one at the
output where as it cannot pass strong zero. The disadvantages of both PMOS and NMOS
pass transistor is overcome by transmission gate where it is able to produce both strong
one and strong zero at the output.

22. Draw the structure of 2:1 CMOS MUX.(Nov/Dec 2013)

23. Give a brief description about NAND implementation of a MUX circuit.

MUX consists of switched paths.NAND implementation uses depletion devices to short cir-
cuitundesired connections while using enhancement mode devices to form the switches that

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exert control. MUX is defined by the locations of the ion implants required to form the deple-
tion mode transistors.

24. List out the sources of static and dynamic power consumption.(Nov/Dec 2016)
CMOS devices have very low static power consumption, which is the result of leakage
current. But, when switching at a high frequency, dynamic power consumption can
contribute significantly to overall power consumption. Charging and discharging a
capacitive output load further increases this dynamic power consumption.

25. Draw the switch logic arrangement for CMOS 3-input NOR gate.

26. Draw 2-input MUX gate using transmission gates.

27. Why single phase dynamic logic structure cannot be cascaded? Justify. (May/June
2016)
Single phase dynamic logic structure cannot be cascaded. Because, a fundamental difficulty
with dynamic circuits is the monotonicity requirement. While a dynamic gate is in evaluation,
the inputs must be monotonically rising. Unfortunately, the output of a dynamic gate begins
HIGH and monotonically falls LOW during evaluation. This monotonically falling output X
is not a suitable input to a second dynamic gate expecting monotonically rising signals,
asshown in Figure. Dynamic gates sharing the same clock cannot be directly connected. This
problem is often overcome with domino logic.

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Figure:Incorrect connection of dynamic gate

28. Define power dissipation. (APRIL/MAY 2019)

Switching power is dissipated when charging or discharging internal and net
capacitances. Short-circuit power is the power dissipated by an instantaneous short-circuit
connection between the supply voltage and the ground at the time the gate switches state.

29. List the various power losses in CMOS circuits. (APRIL/MAY 2019)
Static power dissipation
Dynamic power dissipation

30. Draw a 2-input XOR using nMOS pass transistor logic.(APRIL/MAY 2019)

PART B- C311.2
1. What is meant by power dissipation? Derive an expression for static power dissipation
and dynamic power dissipation with necessary diagram and expressions.(Nov/Dec
2013) / (May/June 2014) (Nov/Dec 2016)
2. Explain low power design.(Nov/Dec 2017)
3. Draw a 3- input NAND gate with its gate and diffusion capacitance. Assume all diffusion
nodes are contacted.
4. What is a pass transistor? What are their limitations? Why? Explain how transmission
gates are built and their principle of operation. (16)
5. Construct a 8 to 1 multiplexer using CMOS devices. Give necessary explanation. (8)
6. Explain why the transmission gate of logic 1 is degraded as it passed through an MOS
pass transistor

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7. Design NAND gate using pseudo –nMOS Logic. (Nov/Dec 2013)

8. Implement the following function using CMOS
f(A,B,C) = A’BC + AB’C + ABC’ (8)
y= (A+B)(C+D) (8) (Nov/Dec 2013)
Z=[A(B+C)+DE]’ (Nov/Dec 2017, Apr/May 2018)
9. Describe the different methods of reducing static and dynamic Power dissipation in
CMOS circuits(May/June 2013)
10. Explain the domino and dual rail domino logic families with neat diagrams.(Nov’2012)
(Nov/Dec 2017)
11. Write a brief note on sequencing dynamic circuits (Nov’2012)
12. Briefly discuss about the classification of circuit families and comparison of circuit
families (May/June 2014)
13. (i) Draw the static CMOS logic circuit for the following expression
(a)Y=(A.B.C.D)’ (b)Y=(D(A+BC))’
(ii) Discuss in detail about the characteristics of transmission gate.(May/June 2016)
14. What are the sources of power dissipation in CMOS and discuss various design technique
to reduce power dissipation in CMOS? (May/June 2016)
15. (i) Explain about DCVSL logic with suitable example.
(ii) What is transmission gate? Explain the use of transmission gate. (April / May 2017)
(Nov/Dec 2017, Apr/May 2018)
16. Explain the static and dynamic power dissipation in CMOS circuits with necessary
diagrams and expressions. (April / May 2017)
17. Write short notes on i) Ratioedcircuits ii) Dynamic CMOS circuits. (Nov/Dec 2016)
18. Briefly discuss the signal integrity issues in dynamic logic design. Propose any two
solutions to overcome it. (Apr/May 2018,Nov/Dec 2018)
19. (i) Implement the equationX=[(A+B)CD]’ using complementary CMOS logic.(Nov/Dec
2018)
(1) Size the device so that the output resistance is the same as that of an inverter with an
NMOS W/L=4 and PMOS W/L=8.
(2) What are the input patterns that give the worst case t PHL and tPLH. Consider the effect
of the capacitance at the internal nodes.
(3) If P(A=1) = 0.5, P(B=1) = 0.2, P(C=1) = 0.3, P(D=1)=1, determine the power
dissipation in the logic gate. Assume VDD = 2.5V, Cout = 30fF and Fclk=250 MHz.
(ii) List out the limitations of pass transistor logic. Explain any two techniques used to
overcome the drawback of pass transistor logic design.(Nov/Dec 2018)
20. (1) Determine the truth table for the circuit shown Figure-3. What logic function does it
implement?
(2) If the PMOS were removed, would the circuit still function correctly? Does the PMOS
transistor serve any useful purpose?(Nov/Dec 2018)

24. Describe in detail about the transistor sizing for the performance in combinational
networks. (April/May 2019)
25. Realize a 2-input XOR using static CMOS, transmission gate and dynamic CMOS
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logic. Analyze the hardware complexity.(April/May 2019)

26.(a) Design a CMOS logic circuit for the given expression X = [(A+B).(C+D)]’ and
draw its stick diagram.

UNIT III: SEQUENTIAL CIRCUIT DESIGN

PART A- C311.3

1. Differentiate combinational and sequential logic circuits.

Combinational logic circuits have the property that the output of a logic block is only a
function of the current input values, assuming that enough time has elapsed for the logic
gates to settle. In sequential logic circuits, the output depends not only on the current
values of the input, but also on preceding input values- i.e., they have memory.

2. List the timing metrics for sequential circuits.

The three important timing parameters associated with a register are : setup time, hold
time and propagation delay.

3. How can memory elements be classified?

Memory elements be classified as:
 Foreground vs Background Memory
 Static vs Dynamic Memory
 Latches vs Registers
4. Draw the block diagram of a Finite State Machine

5. What is the importance of setup time, hold time and propagation delay associated
with a register?
Setup time is the time the data inputs must be valid before the clock transition. The hold
time is the time the data input must remain valid after the clock edge. Assuming that the
setup and hold times are met, the data at the input is copied to the output after a worst
case propagation delay, with reference to the clock edge.

6. How is a latch different from a register? (Nov/Dec 2014, Apr/May 2018)

A latch is level sensitive circuit that passes the D input to the Q output when the clock
signal is high. Contrary to level sensitive latches, edge triggered registers only sample the
input on a clock transition, that is 0 1 for a positive edge triggered register and 1 0
for a negative edge triggered register.

7. What is a flip-flop?
A flip flop is any bistable element formed by cross coupling of gates. A flip flop is useful
only if there exists a means to bring it from one state to the other.

8. What is meant by clock skew? (Apr/May 2018)

Variations can exist in the wires used to route two clock signals, or the load capacitance
can vary based on data stored in the connecting latches. This effect, known as clock skew,
is a major problem, causing the two clock signals to overlap.

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9. What is the major disadvantage of a static gate?

The major disadvantage of the static gate, however, is its complexity. When registers are
used in computational structures that are constantly clocked such as pipelined datapath,
the requirement that the memory should hold state for extended periods of time can be
significantly relaxed. This results in a class of circuits based on temporary storage of
charge on parasitic capacitors. The principle is exactly identical to the one used in
dynamic logic — charge stored on a capacitor can be used to represent a logic signal. The
absence of charge denotes a 0, while its presence stands for a stored 1. No capacitor is
ideal, unfortunately, and some charge leakage is always present. A stored value can hence
only be kept for a limited amount of time, typically in the range of milliseconds. If one
wants to preserve signal integrity, a periodic refresh of its value is necessary. Hence the
name dynamic storage.

10. What is the advantage of dual-edge triggered registers?

It is also possible to design sequential circuits that sample the input on both edges (rising
or falling). The advantage of this scheme is that a lower frequency clock (half of the
original rate) is distributed for the same functional throughput, resulting in power savings
in the clock distribution network.

11. Draw the Voltage Transfer Characteristics of two cascaded inverters.

12. What is meant by a ‘synchronous’ approach to system design?

All sequential circuits have one property in common—a well-defined ordering of the
switching events must be imposed if the circuit is to operate correctly. If this were not the
case, wrong data might be written into the memory elements, resulting in a functional
failure. The synchronous system approach, in which all memory elements in the system
are simultaneously updated using a globally distributed periodic synchronization signal
(that is, a global clock signal), represents an effective and popular way to enforce this
ordering. Functionality is ensured by imposing some strict contraints on the generation of
the clock signals and their distribution to the memory elements distributed over the chip;
non-compliance often leads to malfunction.

13. List the timing classification of digital systems.

In digital systems, signals can be classified depending on how they are related to a local
clock.Signals that transition only at predetermined periods in time can be classified as
synchronous, mesochronous, or plesiochronous with respect to a system clock. A signal
that can transition at arbitrary times is considered asynchronous.
Synchronous Interconnect: A synchronous signal is one that has the exact same

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EC 8095- VLSI Design Dept of ECE

frequency, and a known fixed phase offset with respect to the local clock. In such a timing
methodology, the signal is “synchronized” with the clock, and the data can be sampled
directly without any uncertainty.
Mesochronousinterconnect :Amesochronous signal is one that has the same frequency
but an unknown phase offset with respect to the local clock (“meso” from Greek is
middle). For example, if data is being passed between two different clock domains, then
the data signal transmitted fromthe first module can have an unknown phase relationship
to the clock of the receiving module. In such a system, it is not possible to directly sample
the output at the receivingmodule because of the uncertainty in the phase offset.
Plesiochronous Interconnect A plesiochronous signal is one that has nominally the
same, but slightly different frequency as the local clock (“plesio” from Greek is near). In
effect, the phase differencedrifts in time. This scenario can easily arise when two
interacting modules have independent clocks generated from separate crystal oscillator.
Asynchronous Interconnect: Asynchronous signals can transition at any arbitrary time,
and are not slaved to any local clock. As a result, it is not straightforward to map these
arbitrary transitions into a synchronized data stream.

14. Is D-flip-flop applicable for counter applications? Why?

D-latch is not an edge triggered storage element because the output changesaccording to
the input, ie, latch is transparent, when the clock is high. Due tothis transparency
property, it is unsuitable for counter applications.

15. What is meant by clock jitter? (Nov/Dec 2017)

Clock jitter refers to the temporal variation of the clock period at a given point — that is,
the clock period can reduce or expand on a cycle-by-cycle basis. It is strictly a temporal
uncertainty measure and is often specified at a given point on the chip. Jitter can be
measured and cited in one of many ways. Cycle-to-cycle jitter refers to time varying
deviation of a single clock period and for a given spatial location i is given as Tjitter,i(n)
= Ti, n+1 - Ti,n- TCLK, where Ti,nis the clock period for period n, Ti, n+1 is clock period
for period n+1, and TCLK is the nominal clock period.

16. What are synchronizers? (May/June 2014, May/June 2013)

Synchronizers are a necessity to protect us from their fatal effects. Originally, synchroniz-
ers were required when reading an asynchronous input (that is, an input not synchronized
with the clock so that it might change exactly when sampled). Now, with multiple clock
domains on the same chip, synchronizers are required when on-chip data crosses the
clock domain boundaries.

17. What is meant by pipelining? ( April / May 2017)

Pipelining allows different functional units of a system to run concurrently. Pipelining
cannot decrease the processing time required for a single task. The advantage of pipelin-
ing is that it increases the throughput of the system when processing a stream of tasks.

18. Draw the switch level schematic of multiplexer based nMOS latch using nMOS only
pass transistors for multiplexers. (May/June 2016)

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19. What is NORA CMOS? (Nov/Dec 2017)

NP Domino Logic (also called NORA logic)is used to solve the “erroneous evalu-
ation” problem in dynamic CMOS logic.
– Alternate stages of N logic with stages of P logic
• N logic stages use true clock, normal precharge and evaluation phases, with N logic
tree in the pull down leg. P logic stages use a complement clock, with P logic stage
tied above the output node.
• During prechargeclk is low (-clk is high) and the P-logic output precharges to
ground while N-logic outputs precharge to Vdd.
• During evaluate clk is high (-clk is low) and both type stages go through evaluation;
N-logic tree logically evaluates to ground while P-logic tree logically evaluates to
Vdd.
• Inverter outputs can be used to feed other N-blocks from N-blocks, or to feed other
Pblocks from P-blocks.

20. What is clocked CMOS Register? (May/June 2016)

The C2MOS Register

Figure shows an ingenious positive edge-triggered register, based on a master-slave

concept insensitive to clock overlap. This circuit is called the C 2MOS (Clocked CMOS)
register.
The overall circuit operates as a positive edge-triggered master-slave register —very sim-
ilar to the transmission-gate based register. However, there is an important difference:A
C2MOS register with CLK-CLK’ clocking is insensitive to overlap, as long as the rise and
fall times of the clockedgesaresufficientlysmall.

21. Compare and contrast synchronous design and asynchronous design. (April / May
2017)
Asynchronous design Synchronous Design
Clock pulse is given to first circuit and Simultaneous clock pulse is given to all
the output of first circuit acts as a clock the circuits.
to the next and so on.
Slow as compare to synchronous circuits Fast as compare to asynchronous circuits.
Circuit is simple as compared to Additional combinational circuit is
synchronous circuits. required for its designing. This circuit
becomes complex.
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22. What are the important properties of a Schmitt trigger.

A Schmitt trigger is a device with two important properties:
1. It responds to a slowly changing input waveform with a fast transition time at the
output.
2. The voltage-transfer characteristic of the device displays different switching
thresholds for positive- and negative-going input signals. The switching thresholds for
the low-to-high and highto-low transitions are called VM+ and VM- , respectively.
The hysteresis voltage is defined as the difference between the two.

23. List an application for sense amplifier.

Sense-amplifier circuits accept small input signals and amplify them to generate rail-
to-rail swings. Sense amplifier circuits are used extensively in memory cores and in
low swing bus drivers to amplify small voltage swings present in heavily loaded
wires.
24. Draw a simple circuit for a one-shot.
A simple circuit for one shot is as below:

25. List out the advantage of C2MOS logic based register over pass transistor logic
based master slave register.(Nov/Dec 2018)
The major advantage of C2MOS register is that it is insensitive to clock skew and
hence avoids race conditions.

PART B- C311.3
1. Highlight the difference between combinational and sequential logic circuits. Draw and
explain the block diagram of a Finite State Machine.
2. Explain the timing metrics for sequential circuits with neat diagrams.(Nov/Dec 2017)
3. Briefly explain the difference between Static and Dynamic Memory. Elaborate on the dif-
ferences between latches and registers with necessary timing diagrams. (Nov/Dec
2016)
4. Explain the Bistability Principle associated with static latches and registers.
5. How can we build latches using multiplexers? Explain their operation in detail.
6. What is the common approach for constructing an edge triggered register? Hence explain
the operation of a register based on master-slave configuration.
7. What is the drawback of transmission gate register? What is the approach to overcome it?
8. (i) What kinds of failures are caused by clock overlap? What is race condition?
(ii) What approach is adopted to overcome the above? Explain with neat schematics.
9. Explain the operation of Static SR flip flops built using NOR and NAND gates.
10. Explain the operation of a Dynamic Transmission Gate Edge Triggered Register.
11. How can one design a register that is insensitive to clock-skew?
12. Explain the concept of pipelining in connection with sequential circuit optimization.
13. Explain the NORA-CMOS logic style for pipelined structures. Is this topology race free?
(Nov/Dec2016)
14. Compare synchronous and asynchronous design.
15. Explain the methodology of sequential circuit design of latches and flip-flops(May/June
2014)
16. Discuss the operation of a pipeline concepts used in sequential circuits(May/June 2013)
17. Write a brief note on sequencing dynamic circuits(Nov’2012)
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EC 8095- VLSI Design Dept of ECE

18. i. Design D-flip-flop using transmission gate. (Nov/Dec 2013)Implement a 2- bit non-in-
verting dynamic shift register using pass transistor logic.
19. Explain the operation of master slave based edge triggered register(May/June 2016)
20. Discuss in detail about various pipelining approaches to optimise sequential cir-
cuits(May/June 2016)
21. (a)Explain the operation of true single phase clocked register(b)Draw and explain the op-
eration of conventional ,pulsed and resettable latches(APRIL/MAY 2017)
22. Explain the concept of timing issue and pipelining(APRIL/MAY 2017)
23. Discuss about the design of sequential dynamic circuits and its pipelining concept.
(Nov/Dec 2017)
24. Explain about the memory architecture and its control circuits in detail. (Apr/May 2018)
25. Discuss about the CMOS register concept and discuss master slave triggered register ex-
plain its operation with overlapping periods. (Apr/May 2018)
26. Explain the principle of a Pulse Register.
27. Describe the operation of a sense amplifier based register.
28. List out some non-bistable sequential circuits. Explain the implementation of aSchmitt
Trigger.
29. Explain the principle of monostable and astable sequential circuits.
30. (i)Identify the type of register for the circuit shown in the figure and express set up time,
hold time and propagation delay of register in terms of propagation delay of inverters and
transmission gates.(Nov/Dec 2018)

(ii)Implement the register in the above question using C 2MOS logic and explain how 0-0
and 1-1 overlap of clock signals are eliminated.
31. Design a D latch using transmission gates. Using which realize a two phase a non-over-
lapping master slave edge triggered D flip flop. (April/May 2019)

UNIT IV- DESIGNING ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

PART A- C311.4

1. Draw the truth table of a binary full adder and write the expressions for sum and
carry output.

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EC 8095- VLSI Design Dept of ECE

2. What is the worst case propagation delay in an N bit ripple carry adder?( Nov/Dec
2018)

3. Write the expressions for the intermediate signals: generate, delete and propagate
for a binary adder and express sum and carry out in terms of the above. (Apr/May
2018) , (April/May 2019)

4. Draw the topology of a four bit ripple carry adder.( Nov/Dec 2018)

5. Write the dependency relationship between carry signals in a carry lookaheadadder.

6. Write the inverting property associated with a full adder.

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EC 8095- VLSI Design Dept of ECE

7. What are the main stages of an array multiplier?

The main stages of an array multiplier are: partial product generation, partial product
accumulation and final addition.

8. What is meant by clustered voltage-scaling?

Clustered voltage-scaling is a method of distributing a wide range of supply voltages
inside a block. In this technique, each path starts with the high supply voltage and
switches to the low supply when delay slack is available.

9. Illustrate binary multiplication using a simple example. Specify the bit size of the in-
puts and the partial products.

10. What is booth’s recoding? Draw a partial product selection table for the same.
(April/May 2019)
Booth’s recoding reduces the number of partial products to at most half. It ensures that for
every two consecutive bits at most one bit will be 1 or -1. Reducing the number of partial
products is equivalent to reducing the number of additions, which leads to a speedup as
well as an area reduction.
Partial Product Selection Table
Multiplier Bits Recoded Bits
000 0
001 +Multiplicand
010 +Mutiplicand
011 +2xMultiplicand
100 -2xMultiplicand
101 -Multiplicand
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EC 8095- VLSI Design Dept of ECE

110 -Multiplicand
111 0

11. What is the necessity of a level converter? Draw a simple circuit of the same.
When combining multiple supply voltages on a die, level converters are required
whenever module at the lower power supply has to drive a gate at the higher voltage. If a
gate supplied by VDDL drives agate at VDDH, the PMOS transistor never turns off, resulting
in static current and reduced output swing. A level conversion performed at the
boundaries of supply voltage domains prevents these problems.

12. What method is adopted to reduce power in idle mode?

A common method to reduce power in idle mode is clock gating. In this method, the main
clock connection to a module is turned off (or gated) whenever the block is idle. However
clock gating does not reduce leakage current in idle mode.

13. List the different considerations for designing a Ripple carry adder.
i. Propogation delay of ripple carry adder is linearly proportional to N.
ii. It is important to optimize tcarry than tsum.
iii. Inverting all i/ps to a full adder results in inverted values for all o/ps.

14. What are the draw backs of a static adder circuit.

i. Consumes large area.
ii. Circuit is slow.

15. Draw the circuit of one bit programmable shifter

16. Tabulate various power minimization techniques in datapath structures.

Design Time Sleep Mode Run Time
Active Lower VDD, Multi Clock Gating Dynamic Voltage
VDD Scaling
Tansistor Sizing
Logic Optimization
Leakage Multi Vth Sleep transistors Variable Vth
Active Techniques VariableVth Active techniques

17. What is the advantage of Dynamic Supply Voltage Scaling (DVS)?

Lowering the clock frequency when executing the reduced workloads reduces the power
but does not save energy- every operation is still executed at the high voltage level.
However if both supply voltage and frequency are reduced simultaneously, the energy is
reduced. In order to maintain the required throughput for high workloads and minimize
energy for low workloads, both supply and frequency must be dynamically varied
according to the requirements application that is currently being executed. This technique
is called Dynamic Supply Voltage Scaling (DVS).

18. Draw the energy/operation versus throughput curve for constant and variable sup-
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EC 8095- VLSI Design Dept of ECE

ply voltage operation.

Constant Supply voltage
1 3.3V

Energy/operation
-10x
0.5 Energy
Reduction
Reduce VDD, slow
Circuits down

1.1V
0
0 0.5 1
Throughput ( fclk)

19. What are the parts of a DVS system? Also draw a figure for the same.
A practical implementation of the DVS system consists of the following:
 A processor that operate at a wide variety of supply voltages.
 A power regulation loop that sets the minimum voltage necessary for operation at a
desired frequency
 An operating system that calculates the desired frequencies to meet required through-
puts and task completion deadlines.

20. What is the total time delay for a ripple carry Adder.
Tadder = (N-1) tcarry+ tsum.

21. Illustrate threshold voltage control in an inverter.

Substrate bias is the control knob that allows us to vary the threshold voltages
dynamically. In order to do so, we have to operate the transistors as four- terminal
devices. Variable threshold voltage scheme can accomplish a variety of goals:
 It can lower the leakage in standby mode
 It can compensate for threshold voltage variations across the chip during normal oper-
ation of the circuit
 It can throttle the throughput of the circuit to lower both the active and leakage power
based on performance requirements

22. Write down the Expression for the total propogation delay in an n bit carry bypass
Adder.
Tp = tsetup + M tcarry+ (N/M-1) tbypass+ M tcarry + tsum.

23. What is the advantage of Dynamic adder design?

Reduced capacitance of dynamic circuitry results in substantial speed up over static
implementation.

24. Why is static adder circuit slow ?

A static adder ckt is slow as,
(i) Long chains of series PMOS transistors are present in both carry & Sum generation
circuit.
(ii) Intrinsic load capacitance of the C o signal is large & consists of 2 diffusion & 6
gate capacitances plus the wiring g capacitances.
(iii) Carry generation ckt requires 2 inverting stages per bit.
(iv) Sum generation ckt requires an extra logic stage

25. Draw the structure of a sleep transistor.

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EC 8095- VLSI Design Dept of ECE

26. Determine propagation delay of n-bit carry select adder.(May/June 2016)

tadd=tsetup+Mtcarry+(N/M)tmax+tsum
wheretsetup,tsum,tmax are fixed delays. N and M represents the total number of bits and no.of
bits per stage respectively. tcarryis the delay of carry through a single full adder cell.

27. How to design a high speed adder? (Nov/Dec 2017)

Linear dependenceof the adder speed and the number of bits makes the usage ofripple
adder impractical. So logic optimizations are necessary to design high speed adders in
which propagation delay is reduced compared to ripple adder.

28. Draw a bit sliced datapath organization / What is meant by bit-sliced data path
organization? List out the components of data path. (April / May 2017)
Datapaths are often arranged in bit sliced organization instead of operating on single-bit
digital signals. The data in a processor are arranged in a word based fashion. A 32 bit pro-
cessor operates as data words that are 32bits word wide. This is reflected in the organiza -
tion of datapath. Since the same operation frequently has to be performed on each bit of
the data word, the datapaths consist of 32 bit slices, each operating on single bit, hence
the term bit-sliced.

29. Give the application of high speed adder. (April / May 2017)
High speed Adders will reduce the hardware complexity and make justice with
Speed ,Power,Area and Accuracy metrics. Adders are one of the key components in
arithmetic circuits. Approximation can increase performance or reduce power consumption
with a simplified or inaccurate circuit in application contexts where strict requirements are
relaxed. The potential application is in the DSP application for portable devices such as cell
phones and laptops.

30. Write the principle of any one fast multiplier? (Nov/Dec 2016)
Booth multiplier is a radix -4 multiplication scheme , which examines 3 bits of the
multiplicand at a time to determine whether to add 0,1,-1,2,-2 of that rank of the multiplicand

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31. What is latency? (Nov/Dec 2017)

In sequential designs, each timing path is triggered by a clock signal that originates from
a source. The flops being triggered by the clock signal are known as sinks for the clock.
In general, clock latency (or clock insertion delay) is defined as the amount of time taken
by the clock signal in traveling from its source to the sinks. Clock latency comprises of
two components - clock source latency and clock network latency.

32. What are the timing parameters for electronic memories?

 The time it takes to retrieve data from memory is called the read access time, which is
equal to the time between the read request and the moment the data is available at the in-
put.
 The write access time is the time elapsed between a write request and the final writing
of the input data to the memory.
 Cycle time is the minimum time required between successive reads or writes.

34. How can memories be classified based on access pattern?

Most memories belong to the random access class, which means memory locations can be
read or written in a random order. Some memory types restrict the order of access, which
results in either faster access times, smaller area or a memory with special functionality.
Examples of such are the serial memories: FIFO,LIFO and shift register. Video memories
and CAM also belong to this class.

33. Draw the structure of 4 x 4 barrel shifter (Apr/May 2018)

35. List the memory classification based on memory functionality.

A distinction is made between read-only (ROM) and read- write (RWM)memories. RWM
memories offer both read and write functionality with comparable access times. They
may be either static or dynamic. They belong to the class of volatile memories.
ROM encodes the information into the circuit topology, for example, by adding or
removing transistors. Since this topology is hard wired, the data cannot be modified. They
belong to the class of non volatile memories.
There are also non volatile read write memories (NVRWM). Members of this family are
EPROM,E2PROM and flash memories.

36. What is the peculiarity of a CAM?

Content addressable memories represent an important class of non random access
memories. Instead of using an address to locate the data, a CAM uses a word of data itself
as input in a query style format. When the input data matches a data word stored in the
memory array, a MATCH flag is raised. The MATCH signal remains low if no data stored
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EC 8095- VLSI Design Dept of ECE

in the memory corresponds to the input word. They are an important component of cache
architecture of many microprocessors.

37. List the advantages of two phase clocking scheme.(Nov ’04)

(i) No chance of race conditions occurring in the circuit
(ii) No timing errors due to races or Hazards or clock skew
(iii) Two phase clocking schemes are popular due to its simplicity & reliability
(iv) Design procedures are also simple

38. What is the advantage of using a block address in memory design?

Using block address offers a dual advantage:
 The length of the local word and bit lines-that is the length of the lines within the
blocks- is kept within bounds, resulting in faster access times.
The block address can be used to activate only the addressed block. Non active blocks are
put in a power saving mode with sense amplifiers and row and column decoders disabled.
This results in a substantial power saving.

39. List out the advantages and limitations of 3T DRAM over 1T DRAM (Nov/Dec
2018)
The simplest DRAM cell is the 3T scheme. A 3T DRAM cell has a higher density than a
SRAM cell; moreover in a 3T DRAM, there is no constraint on device ratios and the read
operation is non-destructive. In this cell, the storage capacitance is the gate capacitance
of the readout device, so making this scheme attractive for embedded memory applica-
tions; however, a 3T DRAM shows still limited performance and low retention time to
severely limit its use in advanced integrated circuits.3T DRAM utilizes gate of the tran-
sistor and a capacitance to store the data value.

40. Draw the circuit 1 transistor DRAM cell. (April /May 2019)

PART B- C311.4
1. Explain worst case propagation delay of ripple carry adder with a suitable example.
2. What is the simplest approach to design a full adder circuit? What are its drawbacks?
3. Describe the implementation of a transmission gate based adder.
4. Describe the implementation of a Manchester Carry chain adder.
5. Describe the implementation of a carry bypass adder or carry skip adder.
6. Describe the implementation of a carry select adder.
7. (a)Explain the concept of a carry look ahead adder with neat diagram.(May/June 2014)
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EC 8095- VLSI Design Dept of ECE

(Nov/Dec 2016, Apr/May 2018)

(b) Discuss the details about speed and area trade off (April/May 2017)
8. Explain the concept of a high speed adder. (Nov/Dec 2016)
7. Illustrate the partial product generation logic associated with a multiplier.
8. Illustrate the various schemes for implementing partial product accumulation.
9. What are the methods adopted to perform division in a digital IC? Make a comparison
between them.
10. Explain the structure of a Barrel Shifter. (April/May 2015, Nov/Dec 2015)
11. What is the design approach in a logarithmic shifter?
12. Illustrate various Design-Time power reduction techniques.
13. Illustrate various Run-time power management schemes.
14. How can power be reduced in the standby mode?
15. Design a 16bit carry bypass and carry select adder and discuss their features. (May/June
2016)
16. Design a 4 X 4 array multiplier and write down the equation for delay. (May/June 2016)
17. Explain the operation of booth multiplication with suitable examples? Justify how booth
algorithms speed up the multiplication process. (Nov/Dec 2016)
18. Explain the concept of modified booth multiplier with suitable example(April/May 2017)
19. Draw the structure of ripple carry adder and explain its operation. How is the drawback in
ripple carry adder overcome by a carry look-ahead adder? (Nov/Dec 2017)
20. Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the number of
adders. Discuss it over Wallace multiplier. (Nov/Dec 2017, Apr/May 2018)
21. Construct a 6T based SRAM cell. Explain its read and write operations. What is the im-
portance of cell ratio and pull up ratio in 6T SRAM cell.( Nov/Dec 2018)
22. Design an 8 bit Brent Kung adder.( Nov/Dec 2018)
23. (i) Construct a 4x4 array type multiplier and find its critical path delay.( Nov/Dec 2018)
(ii)Design a 4 input 4 output barrel shift adder using NMOS logic
24. Elucidate in detail low power SRAM circuit.(April/May 2019)
25. Derive the necessary equations of a 4 bit carry lookahead adder and realize the carry out
expressions using Dynamic CMOS logic.(April/May 2019)
26. Design a 4 bit unsigned array multiplier and analyse its hardware complexity.(April/May
2019)
27. Apply radix-2 Booth encoding to realize a 4 bit signed array multiplier for (-10)*(-11).
(April/May 2019)
28. Explain a case study: Design as a trade off.
29. Describe the architecture of an N-word memory.
30. Explain the organization of a memory array.
31. Briefly explain the operation of various memory peripheral circuitries.

UNIT V: IMPLEMENTATION STRATEGIES AND TESTING

PART A- C311.5

1. What is an FPGA? (Nov/Dec 2014)

FPGA is Field Programmable Gate Array that consists of an array of anywhere from 64 to
1000s of logic gate groups that are sometimes called configurable logic blocks.

2. Compare FPGA and CPLD?

CPLD's have a much higher capacity than simple PLDs, permitting more complex logic
circuits to be programmed into them. A typical CPLD is equivalent of from 2 to 64 simple
PLDs. The development of these devices followed simple PLD as advances in technology
permitted higher density chips to be implemented. There are several forms of CPLD,
which vary in complexity and programming capability. CPLDs typically come in 44 to

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EC 8095- VLSI Design Dept of ECE

160 pin packages depending on the complexity.

FPGA are different from simple PLDs and CPLDs in their internal organization and have
the greatest logic capacity. FPGAs are consists of an array of anywhere from 64 to 1000s
of logic gate groups that are sometimes called logic blocks. Two basic classes of FPGAs
are fine grained and course grained .The course grained FPGA has large logic blocks and
fine grained FPGAs has much smaller logic blocks. FPGAs are come in packages up to
1000 pins or more.

3. List out three main parts of FPGA & what is PMS?

CLB-Configurable Logic Block
IOB-Input Output Block
PMS-Programmable Switch Matrix

4. What is JTAG?
Joint Test Action Group (JTAG)

5. State the Xilinx FPGA design flow.

 Specification
 VHDL description - Functional simulation
 Synthesis - Post-synthesis simulation
 Implementation - Timing simulation
 Configuration - On chip testing

6. Differentiate fine-grain and coarse-grain architecture of FPGA

Fine-grained Architecture Coarse-grained Architecture
Manipulate groups of bits via complex
Manipulate data at the bit level functional units such as ALUs
(arithmetic logic units) and multipliers
Designers can implement bit
Reconfigurable resources are wasted during
manipulation tasks without wasting
data manipulation
reconfigurable resources
For large and complex calculations
numerous fine-grained PEs are Fewer coarse-grained PEs are required to
required to implement a basic implement a basic computation
computation
Much slower clock rates Faster
Extremely costly relative to coarse-
Less Expensive
grained architectures
Supports partial array configuration and
Both partially and dynamically
is dynamically reconfigurable during
reconfigurable
application execution.

7. What are the different types of interconnections present in Xilinx FPGA?

Direct interconnect: Adjacent CLBs are wired together in the horizontal or vertical
direction. The most efficient interconnect.
General-purpose interconnect: used mainly for longer connections or for signals with a
moderate fan-out.
Long line interconnect: for time critical signals (e.g. clock signal need be distributed to
many CLBs)

8. What is meant by speed grading?

Most of the FPGA header short chip according to speed is called speed binning or speed
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EC 8095- VLSI Design Dept of ECE

grading. According to Xilinx FPGA product, The speed grade specify the transistor switching
speed that determines how quickly internal clocked circuits can be activated.

9. What is meant by BIDA?

The Bidirectional Interconnect Buffers(BIDA) restore the logic level and logic strength
on long interconnect paths.

10. Define segmented Channel routing?

FPGA is a channeled architecture. The logic modules which implement various types of
logic functions are placed in predefined rows. Channels are defined in between rows of logic
modules for routing of nets. The rows of logic modules are called tracks. The tracks are
divided into different segments which can be connected together by programming a
horizontal antifuse. Each input and output of a logic module is connected to a dedicated
vertical segment. Cross antifuses are located at the crossing of each horizontal and vertical
segment. Programming these antifuses produces a bi-directional connection between the
horizontal and vertical segments for routing of nets via channels. This structure of FPGA is
called segmented channel routing.
11. Differentiate between Altera MAX 9000 and Altera FLEX interconnects architec-
ture?
The MAX 9000 is a coarse-grained architecture. Complex PLDs with arrays that are
themselves arrays of macrocells have a dual-grain architecture. The FLEX architecture is of
finer grain than the MAX arrays because of the difference in programming technology. The
FLEX horizontal interconnect is much denser than the vertical interconnect creating an aspect
ratio of 10:1.

12. List the advantages of Global routing. (May/June 2014)

We typically global route the whole chip (or large pieces if it is a large chip) before detail
routing the whole chip (or the pieces). There are two types of areas to global route: inside the
flexible blocks and between blocks.
The goal of global routing is to provide complete instructions to the detailed router on
where to route every net. The objectives of global routing are one or more of the following:
 Minimize the total interconnect length.
 Maximize the probability that the detailed router can complete the routing.
 Minimize the critical path delay.

13. What is ULSI? (Nov/Dec 2017)

It is the short for ultra large scale integration, which refers loosely to placing more
than about one million circuit elements on a single chip. The Intel 486 and Pentium
microprocessors, for example, use ULSI technology.

14. List some typical defects in the manufacturing of IC.

a. Layer to layer shorts
b. Discontinuous wires
c. Thin – oxide shorts to substrate or well.
d. Nodes shorted to ground or power
e. Nodes shorted to each other

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f. Inputs floating
g. Outputs disconnected

15. Write the various ways of routing procedure. (Nov/Dec 2017, Apr/May 2018).
The routing problem is usually solved by use of a two-stage approach of global routing
followed by detailed routing. Global routing first partitions the routing region into tiles and
decides tile-to-tile paths for all nets while attempting to optimize some given objective
function (e.g., total wirelength and circuit timing). Then, guided by the paths obtained in
global routing, detailed routing assigns actual tracks and vias for nets

16. What are SA0 & SA1 faults.

When anode in a circuit is permanently at logic 1 or 0 due to thin oxide shorts ,ie the n –
transistor gate to Vss or the p – transistor gate to Vdd or meta to metal shorts. The SA0 or
SA1 Fault occurs.

17. Define observability and controllability.

Observability: The observability of a particular internal circuit node is the degree to
which one can observe that node at the outputs of an integrated circuit. Controllability : It is
the measure of the ease of setting an internal node to 1 or 0 state via primary inputs. A well
designed circuit should have all nodes easily controllable.

19. What is fault sampling?

Fault sampling is one of the approaches to fault analysis. It is used in the circuit where it
is impossible to fault every node in the circuit. In this approach, nodes are randomly selected
and faulted.

20. What is a sensitized path?

In D – alg one objective is to propagate a fault at a particular node to one or more primary
o/p This path to the o/p pin is called a sensitized path.

21. What are primary i/p’s and o/p’s?

A primary output(Po) is adirectly observable signal ,such as a pad or a scan o/p .A
primary input is one that can be directly set via a pad or some other means.

22. State the 3 types of fault simulation process.

1. Serial simulation 2. Parallel simulation 3. Concurrent simulation.

23. What is delay fault testing.

In the case of a high powered NAND gate composed of paralleled n - & p – transistors, if an
open ckt occurs the gate would still function but with increased pull down time. This is a delay
fault.

34. What is ILA testing.

An iterative logic array is a collection of identical logic modules . An ILA is C – testable if it
can be tested with a constant number of input vectors independent of the iteration count. An
ILA is I - testable if a particular fault that occurs in any module as a result of an applied input
vector is identical for all modules in an ILA.

35. What are the various connections of a Test Access Port. (TAP).
The TAP has 4 or 5 single bit connections. They are
 TCK(the test clock input) – used to clock tests into & out of chips.
 TMS ( The test mode select) – used to control test operations.
 TDI ( the test data input) – used to input test data to a chip.
 TDO ( test data output) used to output test data from a chip.
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It also has an optional signalTRST( The test Reset Signal) used to synchronously reset the
TAP controller: also used if a power – up reset signal is not available in the chip being tested.

36. What are the advantages & disadvantages of IDDQ.

As IDDQ is based on quiescent current measurement which is time consuming, the tests
must be run slower than normal ,thus increasing the test time. However this technique gives a
form of indirect massive observability at little overhead.

37. What is a TAP controller.

The TAP controller is a 16 state FSM that proceeds from state to state based on TCK &
TMS signals. It provides signals that control the test data registers & instruction registers.

38. Describe the test architecture of a boundary scan using TAP.

. Basic test architecture consists of
 The TAP interface pins
 A set of test data registers to collect datafrom chip
 An instruction register to enable test inputs
 A TAP controller, which interprets instructions & controls the flow of data.

39. What are boundary scan registers?

The boundary scan register is a special case of a data register. It allows circuit board
interconnections to be tested, external components tested, and the state of chip digital I/Os to
be sampled.

40. Explain BYPASS ,EXTEST, SAMPLE /PRELOAD.

The instruction registers has to decode 3 instructions they are.
BYPASS – This instruction is represented by an IR having all zeroes in it. It is
used to bypass any serial data registers in a chip with a 1 – bit register. This
allowsspecifis chips to be tested in a serial scan scan chain without having to
shift through the accumulated SR stages in all the chips.
EXTEST – This allows for the testing of off chip circuitry & is represented by all ones in the
IR.
SAMPLE /PRELOAD: - This instruction places the boundary scan register in the DR chain
and samples or preloads the chip i/os.

41. What is a test DR.

The test data registers are used to set the inputs of modules to be tested and to collect the
results of running tests.

42. What is the aim of adhoc test techniques?

Reducing the combinational explosion of testing

43. Distinguish functionality test and manufacturing test.(Nov’2012)

Functionality test is used to confirm the function of a chip as a whole whereas manufacturing
tests are used to verify that every gate operates as expected.

44. List the typical manufacturing defects.

Layer to layer shorts ,discontinuouswires,missing or damaged vias, shorts through the thin
gate oxide to the substrate or well

45. What is ATPG.

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Automatic Test Pattern Generation is a testing tool which can achieve excellent fault cover-
age

46. What is IDDQ testing.

It is a method of testing for bridging faults

47. What is the need for VLSI testing? (NOV/DEC’2018)(APR/MAY’2019)

The good reasons of testing are
1)Quality Assurance .
2)Verification and validating the product/application
before it goes live in the market.
3)Defect free and user friendly.
4)Meets the requirements.
48. Define boundary scan test.(NOV/DEC’2018)
Boundary scan is a method for testing interconnects (wire lines) on printed circuit
boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a
debugging method to watch integrated circuit pin states, measure voltage, or analyze sub-
blocks inside an integrated circuit.

49. Compare between Xilinx CLB interconnect and Altera LAB interconnect. (NOV/
DEC’2018).
The MAX 9000 is a coarse-grained architecture. Complex PLDs with arrays that are
themselves arrays of macrocells have a dual-grain architecture. The FLEX architecture is of
finer grain than the MAX arrays because of the difference in programming technology. The
FLEX horizontal interconnect is much denser than the vertical interconnect creating an aspect
ratio of 10:1.

50. State the principle behind manufacturing testing(APR/MAY’2019).

As the design is implemented and prototypes are built, test engineering creates and builds
the automated test capabilities to test the alpha, beta, and production units, so you can be
assured that each unit coming off of the production line matches your specifications.

51. State important blocks in FPGA architecture (APR/MAY’2019).

The general FPGA architecture consists of three types of modules. They are I/O blocks or
Pads, Switch Matrix/ Interconnection Wires and Configurable logic blocks (CLB). The basic
FPGA architecture has two dimensional arrays of logic blocks with a means for a user to ar-
range the interconnection between the logic blocks. The functions of an FPGA architecture
module are discussed below:
 CLB (Configurable Logic Block) includes digital logic, inputs, outputs. It implements the
user logic.
 Interconnects provide direction between the logic blocks to implement the user logic.
 Depending on the logic, switch matrix provides switching between interconnects.
 I/O Pads used for the outside world to communicate with different applications.

PART B- C311.5
1. (a) Explain the Configurable Logic Block and IO block of Xilinx XC4000 FPGA.
(b) List the features of Xilinx XC4000 FPGA.
2. With neat sketch explain the CLB,IOB and programmable interconnects of an FPGA
device (May/June 2016)
3. (a)Explain about building block architecture of FPGA (Nov/Dec 2017, Apr/May 2018)
(b)Write short notes on routing procedures involved in FPGA interconnects(April/May
2017)
4. Explain the different fault models.(Nov ‘2012)
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5. Explain how serial scan testing is implemented.

6. Design a block diagram of a test generator for an 8 x 4 K static RAM.
7. Explain the chip level test techniques.
8. Explain with diagram the design strategies for testing the CMOS devices.(Nov 08)
9. Discuss the 3 main strategies for testability.
10. i) Explain in detail Boundary – Scan test.(APR/MAY’2019)
ii) Enumerate on physical faults with examples.
11. i) Explain Built – in self test.(Nov ‘2012)
ii) Describe the testing techniques at chip level and at system level.
12. Explain the importance of system level test techniques.
13. Explain the Design For Testability (DFT) concepts.(NOV/DEC’2018)
14. Explain the following terms:(NOV/DEC’2018)
(i) Silicon debug principle(ii) Boundary – Scan technique.
15. Explain CLB of Xilinx 4000 architecture. (NOV/DEC’2018)
16. Explain logic verification in detail.(APR/MAY’2019)
17. Elucidate in detail the basic FPGA architecture (APR/MAY’2019).
18. Describe FPGA interconnect routing resources with neat diagram (APR/MAY’2019).

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