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Cmos Dec 2019

This document contains exam questions for a CMOS VLSI Circuits course. It is divided into three units. Unit I focuses on topics like parasitic extraction, power dissipation in CMOS inverters, photolithography, and solving node voltages. Unit II covers pseudo-NMOS logic, C2MOS logic, logical effort, latch-up, ratioed vs. ratioless logic, and domino logic. Unit III questions are on flip-flop max-delay constraints, TSPC latches and flip-flops, standard CMOS flip-flops using transmission gates, and global clock generation and distribution. Students are required to answer multiple questions from each unit covering the key concepts and analysis of the course

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Prabhodh Kulkarni
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113 views2 pages

Cmos Dec 2019

This document contains exam questions for a CMOS VLSI Circuits course. It is divided into three units. Unit I focuses on topics like parasitic extraction, power dissipation in CMOS inverters, photolithography, and solving node voltages. Unit II covers pseudo-NMOS logic, C2MOS logic, logical effort, latch-up, ratioed vs. ratioless logic, and domino logic. Unit III questions are on flip-flop max-delay constraints, TSPC latches and flip-flops, standard CMOS flip-flops using transmission gates, and global clock generation and distribution. Students are required to answer multiple questions from each unit covering the key concepts and analysis of the course

Uploaded by

Prabhodh Kulkarni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dec_2019 17EECC301

SRN

V Semester B.E. Examination


(Electronics & Communication Engineering)
CMOS VLSI Circuits (17EECC301)

Duration: 3 hours Max. Marks: 100


Note: i) Answer any TWO full questions from UNIT-I, any TWO full questions from UNIT-II
and any ONE full question from UNIT-III.

UNIT-I
1 a. What do you mean by the term ‘Parasitic Extraction’. Why is full custom flow not
practical for large design? (06marks)
b. Discuss the power dissipation components of a CMOS inverter. (06marks)
c. Explain the procedural steps in photo lithography for forming diffusion with neat
diagram. What is difference between positive and negative photo-resist? (08marks)
2 a. Estimate the charging and discharging time constant for an OAI-321 gate
implemented using fully CMOS logic. (06marks)
b. What is the difference between wet and dry oxidation? What is meant by self-
aligned CMOS process. (06marks)
c. Solve the node voltages in the arrangements given below if Vtn = 0.7V.(Ignore the
back gate effect)

Fig. Q2c (08marks)


3 a. Calculate the diffusion parasitic Cdb of the drain of unit sized contacted nMOS
transistor in a 130nm process, when the drain is at 0V and 1.8V. Assume the
substrate is grounded. The transistor characteristics are CJ = 0.98 fF/ µm2 , MJ =
0.36 , CJSW = 0.22 fF/ µm, CJSWG = 0.22 fF/ µm, MJSW = MJSWG = 0.1, ψ0 = 0.75V
at room temperature. (Area 5 λ X 4λ). (10marks)
b. The designer has a goal to achieve same transient performance as that of a
reference CMOS inverter. Accordingly, design a combinational circuit using fully
CMOS logic for the function F = (A+B(C+DE))'. (10marks)
UNIT-II
4 a. Consider a CMOS process with VDD = 5V, Vtn = 0.7V, Vtp = -0.8V, Kn' = 150
µA/ V2 , Kp' = 68 µA/ V2. Calculate VOH and VOL for a pseudo nMOS with (W/L)p
= 4 and (W/L)n = 6. What would you do to improve the design? (06marks)
b. Implement an AOI-221 gate using C2MOS logic, Explain its working. (06marks)

c. Consider the logic cascade shown in figure below. Use logical effort to find the (08marks)
capacitor and path electrical effort at each stage in the chain. Assume symmetric
gate with r = 2.5.

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Course Teacher Signature: ------------------------------- Scrutinizer Signature: -------------------------------------
Fig. Q6c

5 a. Discuss the latch-up process in CMOS inverter. (06marks)


b. Why is pseudo nMOS called ratioed logic and CMOS logic called ratioless logic? (06marks)
Analyze with appropriate equation and graph.
c. Explain how domino logic can overcome the cascading problem with an example. (08marks)
6 a. Sketch an optimized stick diagram for CMOS gate computing (10marks)
Y = ((A+B+C)D)1 .
b. I. Illustrate the CVSL working with example. (10marks)
II. Complementary Pass Logic(CPL).

UNIT-III
7 a. Illustrate the flip flop max-delay constraint with appropriate waveforms and (10marks)
equation.
b. Write short note on TSPC latch aaaand flip-flop. (10marks)

8 a. Explain the working of standard CMOS flip flop using transmission gate. (10marks)
b. Write a short note on global clock generation & distribution. (10marks)

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Course Teacher Signature: ------------------------------- Scrutinizer Signature: -------------------------------------

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