[ ] 1OECS6 Fifth Semester B.E. Degree Examination, Dec. 2013 / Jan 2014. Fundamentals of CMOS VLSI 2 time: 3 ns Mo. Marks-10 Note: Answer any FIVE full questions, sefecting atleast TWO questions from each par. i i PART-A £1 Explain the fabvicaion steps of CMOS P = el process with net diagram and wit the 4a mask sequence. (12 Marks) Ft Lint tresbold vot equations and emphasize each term (os Mart) 2a Write the CMOS inverter circuit and briefly explain. Write the CMOS VTC showing. regions A.B, C, D, E, Derive the expressions for output voltage in region “B". (10 Marks) bo. Write the circuit and layout for Y = AB+CD+E in CMOS style. (10 Marks) 3a Write the circuit and stick diagtam for CMOS trstate inverter. (04 Marks) b. Write the circuit of Bi CMOS NAND and NOR gate and briefly explain (08 Marks) ©. Explain the circuit of dynamic CMOS logic by taking an example of the function Y= AB=O+0 (08 Marks) 4a Define Sheet Resistance (Rs) and standard unit of capacitance (Cg). Calculate the on resistance of 4:1 nmos inverter with Rs Also estimate the total power dissipated if Von = SV (os starts) . Caleulate the capacitance in © Ci forthe given meal layer shown in fig.Q4(b), if feature size ~ Sum and felative value of metal to substrate = 0075 (os Maris) | Fig a4 <———5 —— Explain briefly the circuit of inverting and non ~ inverting super butte. co7Mans) PART-B Sa. Caleulate the OP voltage Vou in the creit given below far different values of Vs V (os Maris) “ino 3-3 Meus 0-6!10EC56 b. Design Bus Arbitration logic for n — line bus. ao. c. Consider 2, — based design rules and Sim technology. How many nmos 8:1 (7 “e and Z,, =2) cam be driven by a minimum size conductor which is 3 wide and lym thick? Assume Jy, = TmA/(qum)*, Ry= L0KO/ a, Yoo =5 V. (06 Marks) a. Discuss the 4 phase clocking scheme to avoid the problem of cascading in dynamic CMOS logic. (06 Marks) ‘What are the adder enhancement techniques? Briefly explain (04 Marks) ©. Write and explain 6 — bit earry select adder. (10 Marks) ‘a. Write and explain 4 Transistor dynamic and 6 Transistor static CMOS memory cell with sense amplifier , (12 Marks) b. Explain the one transistor dynamic memory cell emphasizing three plate capacitor. (08 Marks) Write short notes on a. Latch up. (07 Marks) . Nature of failures in CMOS, (06 Marks) . 1/0 pads. (07 Marks)| LOECS6 usy Time 1 b. 2st é E Sa & be Fifth Semester B.E. Degree Examination, December 2012 Fundamentals of CMOS VLSI Shs. Max. Marks:100 Note: Answer FIVE full questions, selecting ‘at least TWO questions from each part. PaRT-A Obtain the de tranefrcharaciratis of 8 CMOS favertr and ark al the reglon showing the sas of PMOS an NMOS. ‘ata Compare CMOS an bipolar eehnooges. (ot aes Dra the eu schema and stick diogram of CMOS 2 input NAND gate. oars) ‘Draw the layout for the schematic shown in the Fig.Q.2(c).. (10 Marks) it eg 85 bac Andi Zz SAG ac 4 yal Fi.d2%@ Explain the operation of CMOS dynamic logic. Also discuss the cascading problem of dynamic CMOS lo; (10 Marks) Realize Z= A(B+ O)+DE for clocked CMOS logic. (05 Marks) Find the equation for the node voltages Vj, V2, V5 during logic “1” transfer, when each pass transistor is driving another pass transistor, as shown in Fig.Q.3(c). Assume threshold voltage of each transistor is Vy, (05 Marks) Fig.Q.3(0) Lof2FFind the sealing factors for: i) Channel Resistance Ron ii) Current density J Derive the equation for rise time and fall time for CMOS inverter. Write a note on limitations of seating, Explain structured design of bus arbitration logie for n-line bus, PART-B Explain dynamic 4-bit shift register using CMOS logic. Design 4-bit ALU to implement addition, subtraction, EXOR, EXNOR, OR operations. With the neat diagram, explain Braun array multiplier, Explain the worki Explain one transistor dynamic memory cell with schematic and stick diagram, Discuss CMOS pseuido-statie memory cell with stick diagram. Explain sensitized path-based testing for combinational logic. Write a no g of three-transistor dynamic RAM cell fon ground rules for suecessfl design, 2of2 (06 Marks) (08 Marks) (06 Marks) (10 Mtarks) (10 Marks) and AND (10 Marks) (10 Marks) (06 Marks) (06 Marks) (08 Marks) (10 Marks) (10 Marks)USN l 6ECS6 h Semester B.E. Degree Examination, December 2012 Fundamentals of CMOS VLSI Time: 3 hrs. Max. Marks:100 Note: Answer FIVE full questions, selecting atleast TWO questions from each part. 1a. Explain with strueture the step-by-step flow of n-well fabrication process. (10 Marks) 'b. Explain the desian equations of MOS devices and VI characteristics for n and p devices, (a0 Marks) What are the different MOS layers? Draw the 2, based design rules for a transistor. (07 Marks) b. ANMOS transistor has a threshold voltage of 0.75V, the body effect co-efficient equal to 0.54 compute the threshold voltage for Vsn = SV and 26 =-0.6-V. (0S Marks) © Draw the circuit and stick diagrim of two input NAND gate using CMOS logic, use standard colour or monochrome codes. (08 Marks) 3a. Explain the Pseudo-NMOS logic, structure and their salient features with example.(08 Marks) b. Explain with the circuit the working principle of BiCMOS not gate and show the sub circuits of the output voltage, (08 Marks) MBE} (FE writen og, 42+ 50 wil be wate ws malpractice, on he romaining bank pas. Implement the complementary CMOS logic, for the expression Y Show the design step clearly. (04 Marks) 4 a. With a neat circuit diagram and waveform, explain the prineiple of operation of a dynamic logic and what are the advantages and disadvantages, (10 Marks) b. Explain with circuit diagram the super buflers with inverting type and non-inverting type of snmos, (10 Marks) PART-B 5a, Discuss the architectural issues to be followed in the design of a VLSI subsysters.(10 Marks) b, Design a 4:1 multiplexer using nmos logic and CMOS ogi (10 Marks) 6 a, Explain the important general consideration in CMOS design process. (07 Marks) b. Explain the implementation of ALU funetions with a standard adder. (08 Marks) ©, Define regularity in process illustration (0S Marks) 7a, Discuss the important factors of system timing consideration. (10 Marks) b. Draw the circuit and stick diagram. Explain n-MOS pseudo-static memory cell. (10 Marks) 8 Write short notes on a, VO Pads b. Test and testability ©. LSSD d. BIST (20 Marks)lespotann Nate 1. On corp USN Time: 50. il be reels malt ce 2am Fifth Semester B.E. Degree Examination, June 2012 Fundamentals of CMOS VLSI 3 hs. Max. Marks:100 Note: Answer FIVE full questions, selecting atleast TWO questions from each part. PART-A. Explain the nMOS fabrication process. with neat diagram. (10 Marks) Explain the influence of f/f on the DC transiee characteristics of inverter. (05 Marks) Discuss the difference in the thermal sequence between nMOS and CMOS processes, (05 Marks) Draw (he circuit schematic and stick digeram for CMOS 2 input NOR gate (7 Marks) With neat sketches, explain based design rules for pMOS, nMOS and nMOS depletion mode transistor. 6 Marks) List the colour, stick encoding, mask layout encoding, layers for a simple metal nMOS process. (07 Marks) Explain the operation of CMOS dynamic logic, Discuss the merits and demerits. (06 Marks) Realize Z=M(B+C)+ DE far a clocked CMOS logic (06 Marks) What are the properties of nMOS and pMOS switches? How is transmission gate usefil? (08 Marks) What are the scaling factors of i) Parasitic capacitance Cx ii) Power dissipation per unit arca P, (04 Marks) Caleulate the ON resistance for nMOS inverter with Ruy = 10 KO, Zru= 8 and Zpu = 1. (ot Marks) What are the possible effects of propagation delay in cascaded pass transistor chain and long polysilicon wires? (12 Marks) PART-B Explain how to implement the switch logic of four way multiplexer, using tsansmission gate. (0 Marks) Explain the dynamie 4-bit shift register, using nMOs logic. (10 Marks) Discuss the problems ascociated in VLSI desivo. (04 Mneks) Explain the design steps for a 4-bit adder 06 Marks) Explain 4-bi Braun mukiplice, with net disgram. (10 Marks) Explain the working of one transistor dynamic memory cell, with schematic and stick diagram. (06 Marks) Explain nMOS pseudo static memory cell, with stick diagram, (08 Marks) Explain the concept of system partitioning in VLSI chip westing. (06 Marks) Write short notes on : BICMOS logic CMOS inverter noise margin Buil in self test (BIST) Inpuoutput pac (20 Marksbe rated at mpc rw diagonal rss ines. the re a mponant Not: On completing your answer, ompuls Fifth Semester B.E. Degree Examination, December 2011 Fundamental of CMOS VLSI ‘Time: 3 hrs. Max. Marks:100 Note: Answer any FIVE full questions, selecting at least TWO questions from each part. PART-A 1a. Explain the nMOS enhancement mode transistor for different conditions of vs. (08 Marks) Describe in deuil BICMOS fabrication in aa n-well process. (osMart) What ae the advantages of BICMOS process over CMOS technology? (oeMarts 2. What is body effect? Which parameters are responsible fort? (ossarty An nMOS transistor is operating nective region wih following parameters Vos = 39V, Vn 1V, 100, tS 90 HAV? Find Ip ad drain source resistance. (aS Mary c. Explain in detail regions of operation and mid-point voltage equation for CMOS inverter. (or Marts) 3a List the 2-tased design rules for CMOS. cosaarts ‘b. Draw the stick diagram for nMOS EX-OR gate. (07 Marks) © Whatistansmission gate? And design stick diagram for amsmission gate. (O8Mari) 4. Whatisclocked CMOS gate? Where it is preferred? (oom & Two nMOS inverters ae cascaded to drive capacitive load C, = 16 C, as shown in Fig.Q.4(b).Caleulate pair delay Via t0 Vaa intermns of +. (06 Marks) Nine pe et a” = Fig.Q.4(6) ¢, Find the scaling factors for MOS circuits i) Forgatecapacitance —; —_ii) Channel resistance (Roa) ii) Salurtioncurent1d,) ; iv) Speed power product PT). (osMarts PART-B Sa Designbus arbitration logic for n-ne bus. comarts b. Explain two-phase clocking generator using D flip ~ flops. (10 Marks) 6 a. Explain the design steps for 4 bit adder. (08 Marks) Draw th baie arangerents of 4 tt serial parallel multi oman) 6 Diseuss the ming constraint for system timing considertons. formar) 7 a. Forsingle phase clock define following parameters i) Setup time (T.) ; i) Hold time (T,) ; ii) Clock to Q delay (Ty). (03 Marks) {How to read or wie and hold ke bit in SRAM cll? (Marts Explain the working of Itansstor DRAM cell. Give the difference between SRAM and DRAM (os Marts 4) a. Diseus the meaning of “REAL ESTATE” in VLSI design. (osmarts %. What ae the different ypes of UO pads? (tomar) 6. Liste ground rles fra systema design. Goma)nk pages. tes oh remaining 2. Any reveling of identification, appeal to evaluator andr equ writen , 428 ~ $0, wl be ated ws malpractice. ‘aaporant Note: 1. Or completing your answers, campus draw diagonal Fifth Semester B.E. Degree Examination, June/July 2011 Fundamentals of CMOS VLSI Time: 3 hrs. . Max. Marks:100 Note: Answer any FIVE full questions, selecting ‘at least TWO questions from each part. PART-A. 1 2 Deseribe in detail step-by-step procedure of P-well CMOS fabrication. (08 Maris) b. Explain the transfer plot of CMOS inverter with necessary expression for Vou in each region (08 Marks) ¢, Write a note on transmission Bate. (04 Marks) 2 & Draw circuit diagram and stick diagrams of two input NOR gate using CMOS logic use standard colour/monochrome codes. (8 Maris) . Explain 2 based design rules applicable to MOS layers and transistors. (8 Maris) © Write note on Double metal MOS process rules for contact cut, (04 Maris) 3 Explain the following logic structures with ther salient features: '% BICMOS logic —_b. Pseudo-nMOS logic. Pass transistor logic d. C7MOS logic. @0 Maris) 4 Define sheet resistance, standard unit of capacitance and delay unit of time. (96 faris) Explain cascaded inverters to drive large capacitive loads. Obtain an equation to find umber of stages, (es Maris © Discuss the following in seating of MOS cirouts 4) Limit of miniaturization if} Limits of interconnect and contact resistance. (06 Marks) PART-B S a. Explain the structured design of a parity generator with necessary blocks and stick diagram, Eg (10 Marks 'b. Explain domino CMOS logic with neat cirenit, (10 Mars) 6 a, List and explain the general considerations to be considered in Digital system design. (06 Marks) . Explain the design of datapath in 4-bit arithmetic processor with floor plan for 4-bit datapath, (10 Marks) Write MOS switch implementation of 4:4 crossbar switch. (04 Mar 7 a, What are timing considerations in system design? (06 Marks) b, Draw one-transistor dynamic memory cell circuit arrangement. What is the significance of creating capacitor by using a polysilicon plate over the diffusion area? (08 Maris) Explain six transistor static CMOS memory cell arrangement. (06 Marks) 8 a. Discuss the requirements of VO pads in a chip. 0S Marks) ', Explain the sensitized path based testing applied to combinational logic as an example, (0 Marks) ©. Write a note on scan design technique. (@S Maris)| TITEL O6ECs6 Fifth Semester B.E. Degree Examination, December 2010 Fundamentals of CMOS VLSI ‘Timo: 3 hrs. Max, Marks:100 Note:t. Answer any FIVE full questions, selecting aileast TWO questions from each of Part —A and Part - B. 2. Missing data may be assumed suitably. t i z PART 4 1a, What do you mean by static load inveners? Derive the output vltage for the pseudo invener by discussing its DC transfer characterises (08 Mars) b. Ina 0.5um process tp = 44.69 * 10? m/V, toe = 14.1nm and the (W/L) 2» ‘The NMos 3 hhas Vy ~ O.71V and Vp = 1.5. At what levels of Vas and igwill the MOSFET reach pinch, off mode? Hirt: (ea 9). (96 Marks) © What is the functionality of the circuit shown in fig. Q1(¢). Is it correct method to connect the circuit as shown in figure QU(c)? Justify your answer, (6 Mars) ~ 0p . “) * Fig. Qe) 72: 2a. Draw the Cmos circuit for half adder. (Hint : Sum ~ A © B, carry ~ AB, Inverted ip" are allowed), (08 Mars) +b. Draw the circuit diagram for the layout diagram shown in fig. Q2(b), (0 Maris) Ea or Fig. Q20) a Sa © Whatare the basic layers of MOS circuit? (04 Marks) 3a Explain the working principle of dyzamic CMOS logic and clocked CMOS logic of “Nand gate. (12 Marks) Implement the pass transistor logic circuit for the expression Y= A + BC, Show the design steps clearly. (09 Maris) 4 a Discuss the limitations of scaling, (10 Maris) b. Dative the expression for total delay for N stage of NMOS and CMOS inverters by assuming the widta factor f= «, (10 Marks) Lot206EC56 PART -B In the circuit shown in fig. Q5(@), find V1, V2, V3, V4 and ¥5. Justify your answer. (ouMar) Awe wo Wy + va v5 wot yt Fig Q5t@) v5 Explain NMOS and CMOS non ~ invering dynamic storage cell and draw the 3 ~ bit shift register using the CMOS dynamic storage cell a2 Merk Draw and explain the & — bit eamy select adder dividing it into m = 2 blocks. Celeulate the ‘completion time *T” by assuming the one adder delay is fs and one mux delay is 2ns (2Msrisy Draw the block diagram and clearly show the switch connections c perform tie logic operation of "OR" and "KOR" ina 3~ bit ALU using a standard adder clement. (0€ Marks) Explain fous transistor dynamic and six transiator static memory cells. Reason out the need for sense amplifier inthe cell array (14 Mars) Explain he CMOS psetso ~ static D flipflop. (05 Marks) What is multiplexed D flipflop? Explain the general method for testing with scan path approach, (os ars) ‘What are the three important seps in sensitized path bused testing? (06 Marts) Find the tet vectors to detect the stuck @ 0 and stuck @! faults of “and” gate at its input and output noce. Fig, 8). {05 Marks) Fig. O80) \ e b JImportant Note: 1. On cotpleting your answers, complsoriy daw dingons ross ines onthe remaining blank pages west as malpractice. i : ; : 4 i z & S 2 + i 3 Fifth Semester B.E. Degree Examination, May/June 2010 Fundamentals of CMOS VLSI Time: 3 brs. Max. Marks:100 Note: I. Answer any FIVE full questions, selecting ‘at least TWO questions from each part. 2. Draw neat diagrams. Explain the fabrication steps in (10 Marke) Obtain the de transfer characteristics of a CMOS inverter and mark all the regions showing the status of PMOS and NMOS. (10 Marks) Compare CMOS and bipolar technologies. (04 Marks) Explain the transmission gate operation. (04 Marks) Draw ?-based design rules for dauble metal CMOS process for layers and transistors. (8 Marks) Draw the circuit diagram and stick diagram for nand gate. (o4 Marks) Explain different types of pseudo - NMOS logic. (07 Marks) Explain CMOS domain logic and derive the evaluation voltage equation. (08 Marks) Explain 2-input x-nor gate in pass transistor logic (05 Marks) Explain the terms :i) Rise time ; ii) Fall time ; ili) Delay time. Derive the equations for fall time of CMOS inverter. (08 Maris) Provide scaling factors for gate area, gate delay, sat current, (05 Maris) Explain in brief the wiring capacitances. (06 Marks) PART-B Explain the restoring logic, in detail (04 Marks) How to implement the switch logic for 4-way multiplexer? Explain, (08 Marks) Explain the pre charge bus approach, used in system design. (08 Marke) Explain the 4 x 4 cross bar switch operation, Mention the salient features of sub system design process. (08 Marks) Explain the design steps for A 4-bit adder. (06 Marks) How can 4-bit ALU architecture be used to implement an adder? (05 Marks) Explain the read and write operations in dynamic memory cell. (06 Marks) Explain booth multiplier, with an example. (08 Marks) Explain different types of MO pads. (06 Marks) Write a note on testability and testing, (CO Marks) Explain the ground rubs for a system design. (Go Mans)gi T T “ (TOOT nae Fifth Semester B.E. Degree Examination, June-July 2009 Fundamentals of CMOS VLSI Note: 1Answer any FIVE full questions, selecting mea b, How is en nMOS transistor fabricated? Explain with neat sketches, (10 Marks: characteristics of a typical inverter. O6 Marks} © What is i-based design? What are the merits and demerits? (04 Marks) . Obtain the stick diagram and Layout of a two-way selector with enable. (06 Marks), aegp Define sheet resistance ard standard unit of capacitance DC, Hate the ON resistance for nmas imerter with Ky 10K, Zu 4 & Zye= 1. (06 Marts} Obiain the expression for total delay for N stages of nmos & emos inverters in tems of width factor Pand delay e, PART-B (0a Mtais) ‘What are the sealing fators for : Gute capacitance Cy Max. opersing frequency fy Current density J Power speed product Pr O8Ntars) ‘What are the properties of mos and pos switches? How is tansmission gute uses 6 Maris) Obtin the logic implementation ofa 4way multiplexer usingnmos switches. (oe ney Draw te basic form ofa two-phase clock generator and expliin (07 Mars) How to implement artmetic and logic operations with a standard adder? Explain arth the hip of logic expressions. (@s marks Explain structured design approach for a pacity generator. (Mana) Whats sructured design process? Explain, (osmans) Whot are the system timing considerations? (05 Matis) Show the functioning ofa single transistor pnémic memory cel (06 Mais) ‘Waite short notes oni 10 pads, ‘Test and testability Pseaito nos logic Bieros logic, (20 Mark)Time: 1a b, c 24 db. « 3a b c 4a b 5a. b. c. 6 a b, Ta b. 8 a » Fifth Semester B.k. Degree Exammation, Dec.U¥/Jan.10 Fundamentals of CMOS VLSI 3 hrs. Max. Marks:100 Note: Answer any FIVE full questions, selecting at least TWO questions front each part. PART-A Distinguish between enhancement and depletion mode operation of MOSFETs. (05 Marks) Explain with diagrams, the main steps in the twin-tub process. (10 Marks) Compare CMOS and Bipolar technologies. (05 Marks) List the expression for threshold voltage of an nMOS transistor and narrate the significance of each ferm in this equation, (08 Marks) Calculate the threshold voltage with ¢,=11.7¢ €,=3.9efor an nMOS transistor with Na=2x 10"/em’, x= 190°A, Assume Ons *-0.85v, Qe = 0, Ni= 1.45 x 10!/cm? (07 Marks) Discuss the effect of channel length modulation on the performance of an nMOS transistor. (05 Marks) List the color, stick encoding, mask layout encoding and CIF layers for the following layers used n VLSI technology i) n—diffusion ii) Poly silicon iii) Metal 1 iv) Impact (04 Marks) Write the stick diagram for a parity generator using nMOS logic. (03 Marks) Write the layout for the logic expression Y = A+BC using CMOS design. (08 Marks) Discuss the limits of scaling on : i) Supply voltage due to noise ii) Sub threshold current iii) Interconnects. (10 Marks) Realize a 2-input NAND gate for a clocked CMOS logic and also for CMOS domino logic. (10 Marks) Calculate the area capacitance of a multilayer structure shown in Fig.Q5(a), (08 Marks —Fiephmto— sh —y To ies Ty — Narrate the steps involved in calculating the sheet resistance of : i) Transistor channels ii) nMOS inverter ili) CMOS inverter (06 Marks) Derive expressions for rise time and fall time for 1:1 CMOS inverter. (06 Marks) Discuss the architectural issues to be followed in the design of a VLSI subsystem. (06 Marks) Design 4:1 MUX using transmission gates. (06 Marks) Discuss the timing constraints for both flip flops and latches. (03 Marks) Discuss Baugh-Worley method used for Two's complement multiplication. (12 Marks) Explain the working of 3TDRAM cell (08 Marks) Define noise margin for both high and low levels. (04 Marks) Discuss the meaning of “REAL ESTATE” in VLSI design. (08 Marks) Narrate the meaning of controllability and observability in VLSI chip testing. (08 Marks) teensusw | ] O6ECS6 Fifth Semester B.E. Degree Examination, Dee 08 / Jan 09 Fundamentals of CMOS VLSI Trae: 3 hes Max, Marks:100 Note: Answer any FIVE full questions, selecting at least TWO ‘from each part PART-A 1a. Explain the CMOS inverter transfer characteristics highlighting the regions of eperation of the MOS transistors (02 Marks) b, Describe with neat diagrams, the P well fabrication process. (08 Mars) 2a With neat diagram, explain & - based design rules for contact cuts and Vies. (12 Marks) . Draw the stick diagram for the NMOS implementation of the Boolean expression ¥-AB+C (08 Marks) 3° a. Discuss the merits and demerits of the following CMOS logie structures with a two input NAND gate realization as an example. i) Complementary CMOS logis ii) Pseudo NMOS logic :). Dynamic CMOS logic (15 Marks) b, Explain the operation of CMOS ‘Transmission gate (05 maria) 4a. For the given multilayer MOS structure, calculate the total capacitance in terms of Cg (Sum) Technology) (0 Maris) Given + Metal 1 wo substrate capacitance ~ 0.075 ( Relative capacitance) Polysilicon to substrate = 0.1 bb. Describe the delay unit + in terms of shect resistance and area capacitance, For the CMOS inverter pair shown, ealeulate the total delay. (do saris) Wao Nout06FC56 PART-B as ac dala oe — «eau eile mnsteinc aap casas By uy Leven number of I's ‘ nal ee 8, What is domino CMOS logic? How does it eliminate the issues related to cascading’? (dO Marks b. Explain the dynamic two bit shift register circuit using NMOS and CMOS logic. (10 Marks) 4. Discuss the various system timing constrains, (0S Marks) ', Explain the three transistor Dynamic RAM cel, (10 Marts) ©. Describe the CMOS Pseudo static D flip Nop ci (0s Barks) Write short notes on 4, Latch up phenomenon, b. BICMOS circuit ©. Level sensitive scan design 4. Built in Self Tes (BIST) eo Marks) 2of2