TECHNOLOGY, MESRA, RANCHI
BIRLA INSTITUTE OF
(MID SEMESTER EXAMINATION)
SEMESTER: V
SESSION: MO24
CLASS: DTECH
DRANCH: ECE
SUBJECT: EC319 VLSI SYSTENS FULL MARIKS: 25
TIME: 2:00 Hrs
INSTRUCTIONS: and total 25 marks.
5 questions ch of 5 marla
1. The questlon paper contains
2. Attempt all questkons.
may be assumed sultably. you have got the coTect queton paper.
3. The missing data, tf any, paper, be ure that halL
attempting the suppHed to the candidates In the exami nation
Tablernata handook/roh paper etc. to be
4. Before
CO
1 3
Vtnen 700 (2)
the following parameters: HIGHstate
ofa CMOS inverter spectfles the
Q.1(a) The data sheet 300 mV, Voun 100 mV, Calculate
mV, VoHtn 900 mV, Vume LOW-state nolse margin (NM). 1 2
notse margn (NMn) and the
(V) of a CMOS fnverter. Explain how its value s (3]
switching threshold inverter in 0.25
Q.1(b) Describe the
graphically. What (s the desired value of V for a CMOS
obtained
um process?
below. 2] 2,3
(Vo) and (Vow) of the low swing drver shown fn the Figure
Q.2(a) Write down the (V) is not rail-to-rail. Assume
A-0.
Explain why the output voltage swing
DD 2.5 V
V.
3 Ln
0.25nm
Vin Vout
2.5V C=100fF
Vmo=|Vpol=0.4V 2,3
[31 1
their curent equations,
regiors of operation of MOSFETS end suftable diagram.
Q.2(b) Write down
varous
modulatlon (CM) effect with
a
Explatn the channel length trarsition of 21
4
energy Evpo, taken from Voo during the 01
expression of
Q3(a) Deduce the (31 2 3
the output node.
product (PDP). Calculate
the power-delay product
the power-delay process having a load
Q.3(b) Brlefly explain Iwerter designed In a genertc 0.25-um CMOS
(PDP) of a CMOS fF.
capacitance C of6 (2) 2
Substantiate your answer
interConnect?Define its pltch
and aspectratlo.
What is an 1
a victim wire (3)
Q.4(a) 2
of the interconnect.
with a suttable diagramfeedthrough) Consider that a clock wire and clock in the
Q.4(b) Deffne crosstalk (clock What impact sfound on the victim wire if the a suitable
are routeed side-by-side. Substantiate your answer with
makes a high-to-low transition?
clock wre
dagram and explain it. 2] 2
mentioning each term n
depth? Formulate skin depth
What fs skin effect and skin 2
Q.s(a) minimum words. (p=2.7x10Gm) routed
through a 3]
(3) of aluminum wire 4px10 HÍm)
Q.5(b) Calculate the skin depth
the permeability free space (l.e., e
surrounding dielectric with
current at 1 GHz.
whlle carrying a
:25092024:::M
BIRLA INSTITUTE OF TECHNOLOGY, MESRA, RANCHI
(MID SEMESTER EXAMINATION)
CLASS: B.TECH. SEMESTER: V
BRANCH: ECE SESSION: MO/23
SUBJECT: EC319 VLSI SYSTEMS
TIME: 2:00 Hrs FULL MARKS: 25
INSTRUCTIONS:
1. The question paper contains 5 questions each of 5 marks and total 25 marks.
2. Attempt all questions.
3. The missing data, if any, may be assumed suitably.
4. Before attempting the question paper, be sure that you have got the correct question paper.
5. Tables/Data handbook/Graph paper etc. to be supplied to the candidates in the examination hall.
----------------------------------------------------------------------------------------------------------------------------------
Marks CO BL
Q.1(a) Tell the regions of operation of the MOSFETs of a static CMOS inverter for low input? [2] 1 1
Assume VDD = 1 V and Vtn = 0.4 V and Vtp = −0.4 V. Describe your answer with proper
justification.
Q.1(b) Describe the switching threshold (VM) of a CMOS inverter. Explain how its value is [2] 1 2
obtained graphically. What is the desired value of V M for a CMOS inverter in 0.25 μm
process?
Q.2(a) Consider the low swing driver of Figure shown below. Interpret the voltage swing [2] 1 2
on the output node (Vout)? Assume λ=0.
Q.2(b) Define propagation delays and rise and fall times for CMOS inverter circuit. [3] 1 1
Substantiate your answer with a suitable diagram.
Q.3(a) Deduce the expression of energy EVDD, taken from VDD during the 01 transition of [2] 1 4
the output node.
Q.3(b) Briefly explain power-delay product (PDP). Calculate power-delay product (PDP) of [3] 2 3
a CMOS inverter designed in a generic 0.25-μm CMOS process having a load
capacitance CL of 6 fF.
Q.4(a) Explain various noise sources in digital circuits. Substantiate your answer with [2] 2 4
suitable diagram.
Q.4(b) Estimate the largest dimension [i.e., max (W, H)] of an aluminum wire (ρ=2.7×10−8 [3] 2 5
Ω∙m) routed through a surrounding dielectric with permeability of free space (i.e.,
μ = 4π×10−7 H/m) while carrying a current at 1 GHz.
Q.5(a) Schematize input pad with electrostatic discharge (ESD) circuit. [2] 2 6
Q.5(b) Explain the purpose of each component and comment on the device length and oxide [3] 2 4
thickness of MOSFET used in that circuit.
:::::26/09/2023 M:::::
BIRLA INSTITUTE OF TECHNOLOGY, MESRA, RANCHI
(MID SEMESTER EXAMINATION)
CLASS: B.TECH. SEMESTER: V
BRANCH: ECE SESSION: MO/2022
SUBJECT: EC319 VLSI SYSTEMS
TIME: 2 HOURS FULL MARKS: 25
INSTRUCTIONS:
1. The total marks of the questions are 25.
2. Candidates attempt for all 25 marks.
3. Before attempting the question paper, be sure that you have got the correct question paper.
4. The missing data, if any, may be assumed suitably.
5. Tables/Data handbook/Graph paper etc. to be supplied to the candidates in the examination hall.
----------------------------------------------------------------------------------------------------------------------------------
Marks CO BL
Q1 (a) Describe switching threshold (VM) of a CMOS inverter. Explain how its value is [2] 1 2
obtained graphically. What is the desired value of VM for a CMOS inverter in 0.25
μm process.
Q1 (b) The data sheet of a CMOS inverter specifies the following parameters: VIHmin [3] 1 3
=700 mV, VOHmin = 900 mV, VILmax = 300 mV, VOLmax = 100 mV. Calculate the HIGH-
state noise margin (NMH) and the LOW-state noise margin (NML).
Q2 (a) Sketch gate to channel capacitance (CGC) as a function of degree of saturation [2] 1 3
and explain it.
Q2 (b) Define propagation delays and rise and fall times. Substantiate your answer with [3] 1 1
suitable diagram.
Q3 (a) Deduce the expression of energy EVDD, taken from VDD during the 01 transition [2] 1 3
of output node.
Q3 (b) An inverter implemented in a generic 0.25 μm CMOS process has load [3] 2 3
capacitance CL = 6 fF. Estimate the dynamic energy taken by it from the supply
voltage.
Q4 (a) Define pitch and crosstalk, which are related to interconnect. How many metal [2] 2 1
layers and poly layers are there in the generic 0.25 μm CMOS process?
Q4 (b) The generic 0.25 μm CMOS process uses SiO2 as dielectric material. In the same [3] 2 3
process if a 10 cm long, 1 μm wide and 1 μm thick aluminum wire is routed as
first metal layer then compute the area (parallel plate) capacitance of
interconnect. If the same process would use aerogel as dielectric material, what
would have been the value of area (parallel plate) capacitance of interconnect
of the same size
Q5 (a) Schematize input pad with electrostatic discharge (ESD) circuit. [2] 2 6
Q5 (b) Explain purpose of each component and comment on the device length and [3] 2 4
oxide thickness of MOSFET used in that circuit.
:::::: 01/10/2022 ::::::M
BIRLA INSTITUTE OF TECHNOLOGY, MESRA, RANCHI
(END SEMESTER EXAMINATION MO-2023)
CLASS: B.TECH. SEMESTER: V
BRANCH: ECE SESSION: MO/2023
SUBJECT: EC319 VLSI SYSTEMS
TIME: 3 HOURS FULL MARKS: 50
INSTRUCTIONS:
1. The question paper contains 5 questions each of 10 marks and total 50 marks.
2. Attempt all questions.
3. The missing data, if any, may be assumed suitably.
4. Tables/Data handbook/Graph paper etc., if applicable, will be supplied to the candidates.
------------------------------------------------------------------------------------------------------------------------------
CO BL
Q1 (a) Define LO-skewed, HI-skewed and unskewed inverters and sketch their transfer [5] 1 1,2,3
characteristics. Consider the following low swing driver consisting of NMOS devices M1
and M2. Assume an NWELL implementation. Assume that the inputs IN and (𝐼𝑁) ̅ have a
0 V to 2.5 V swing and that VIN = 0 V when 𝑉_(𝐼𝑁) ̅ = 2.5 V and vice-versa. Also assume
that there is no skew between IN and (𝐼𝑁) ̅ (i.e., the inverter delay to derive (𝐼𝑁) ̅ from
IN is zero). (a) To what voltage is the bulk terminal of M2 connected? (b) Briefly explain
its voltage swing on the output node as the inputs swing from 0 V to 2.5 V. Write the
low value and the high value.
Q1 (b) Write the expression of dynamic power consumption. Explain each term in it. Write the [5] 1 2,3
expression of Power-Delay Product (PDP) and Energy-Delay Product (EDP). Explain each
term in them.
Q2 (a) A wire, which is 10 cm long and 1 μm wide, is routed on the polycide, the sheet [5] 2 3
resistance of which is 4 Ohm-per-square. Compute the total resistance of the wire.
Consider 10 cm long and 1 μm wide aluminum wire routed as first metal layer. Assuming
130 nm CMOS process, where 1 μm thick fluorosilicate glass (FSG) (ε FSG = 3.6) is used as
dielectric material, compute the area (parallel-plate) capacitance of interconnect.
Q2 (b) Sketch gate-level schematics of a tristate buffer, which may be used in an output pad [5] 2 3
and explain its operation.
Q3 (a) Diagram a transistor-level circuit of 2-input NAND gate using Dynamic CMOS logic style. [5] 3 4
Cascade two dynamic inverters and criticize the same with suitable diagram.
Q3 (b) Point out the various issues in Dynamic Design and explain charge leakage with a [5] 3 4
suitable diagram.
PTO
Q4 (a) Schematize dynamic positive edge-triggered (master/slave) register. [5] 4 5
(i) Argue in favour of the dynamic positive edge-triggered (master/slave) register for
its advantages and applications.
(ii) Criticize the dynamic positive edge-triggered (master/slave) register for its
disadvantages.
Q4 (b) Schematize transistor-level circuit diagram of C2MOS (clocked CMOS) master-slave [5] 4 3,4,5
positive edge-triggered register and briefly explain its operation.
Q5 (a) A MOSFET is biased at a drain current of 0.5 mA. If μnCox = 100 μA/V2, W/L = 10, and λ [5] 5 5,6
= 0.1V −1, estimate its small-signal parameter gm.
Estimate the small-signal voltage gain of the CS stage shown in the given Figure if ID =
1 mA, μnCox = 100 μA/V2, VTH = 0.5 V, and λ = 0. Justify that M1 operates in saturation.
Q5 (b) Schematize CS stage with load resistor RD and source degeneration resistor RS. ignoring [5] 5 4,6
channel-length modulation effect. Schematize its small-signal model and deduce the
expression of its voltage gain if λ = 0.
::::::28/11/2023::::::M
BIRLA INSTITUTE OF TECHNOLOGY, MESRA, RANCHI
(END SEMESTER EXAMINATION)
CLASS: BTECH SEMESTER : V
BRANCH: ECE SESSION : MO/2022
SUBJECT: EC319 VLSI SYSTEMS
TIME: 3:00 Hours FULL MARKS: 50
INSTRUCTIONS:
1. The question paper contains 5 questions each of 10 marks and total 50 marks.
2. Attempt all questions.
3. The missing data, if any, may be assumed suitably.
4. Before attempting the question paper, be sure that you have got the correct question paper.
5. Tables/Data hand book/Graph paper etc. to be supplied to the candidates in the examination hall.
----------------------------------------------------------------------------------------------------------------------------------
CO BL
Q1 (a) Find the region of operation of the pMOSFET and nMOSFET shown below. [2] 1 2
Q1 (b) List various secondary effects in a short-channel MOSFETs? [3] 1 1
Q1 (c) Write the expression of dynamic power consumption. Explain each term in it. Write the [5] 1 3
expression of Power-Delay Product (PDP) and Energy-Delay Product (EDP). Explain each
term in them.
Q2 (a) A wire, which is 10 cm long and 1 μm wide, is routed on the polycide, the sheet [2] 2 3
resistance of which is 4 Ohm-per-square. Compute the total resistance of the wire.
Q2 (b) What is skin effect and skin depth? Express the equation of skin depth mentioning each [3] 2 2
term in minimum words.
Q2 (c) Explain how a Schmitt trigger circuit can guard against noise-induced false switching [5] 2 3
when used in an input pad. Substantiate your answer with suitable diagram.
Q3 (a) Explain why pseudo nMOS logic circuits are called ratioed circuits? [2] 3 4
Q3 (b) Diagram the transistor-level circuit diagram of an inverter and implement the same [3] 3 4
with Verilog HDL using switch-level modeling style.
Q3 (c) Using CMOS logic styles realize the Co (carry out) function, which is given by Co= [5] 3 4
A.B+Ci.(A+B), and SUM function, which is given by SUM = A.B.Ci + (A+B+Ci), where Ci is
the input carry.
Q4 (a) Schematize transistor-level circuit of CMOS positive-level-sensitive D latch with [2] 4 5
minimum number MOSFET.
Q4 (b) Schematize transistor-level implementation of SR flip-flop with NAND as well as NOR [3] 4 5
gate.
Q4 (c) Schematize multiplexer-based NMOS latch using NMOS-only pass transistors. Explain its [5] 4 5
advantages and disadvantages with proper reasoning.
PTO
Q5 (a) A MOSFET is biased at a drain current of 0.5 mA. If μn Cox = 100 μA/V2, W/L = 10, and λ [2] 5 5
= 0.1V −1, estimate its small-signal parameter gm.
Q5 (b) Estimate the small-signal voltage gain of the CS stage shown in Fig. 7.6 if ID = 1 mA, [3] 5 5
μnCox = 100 μA/V2, VTH = 0.5 V, and λ = 0. Verify that M1 operates in saturation.
Q5 (c) Schematize CS stage with load resistor RD and source degeneration resistor RS. [5] 5 6
Schematize its small signal model and derive the expression of its voltage gain.
:::::28/11/2022:::::M
BIRLA INSTITUTE OF TECHNOLOGY, MESRA, RANCHI
(END SEMESTER EXAMINATION MO-2024))
SEMESTER: V
CLASS: BTECH. SESSION: MO2024
BRANCH: ECE
SUBJECT: EC319 VMSI SYSTEMS
FULL MARKS: 50
TIWE: 3 HOURS
INSTRUCTIONS:
each of 10 mars anda total of 30 merks.
1. The questlon paper contalns 5 questlons
2. Attempt all questlons.
3. The mtssing data, f any, may be assumed sultably. be suppled to the canddetes.
4. TablessData handbook/Graph paper etc., appllcable, wll
Co BL
[5] 1 2.3
Q1 (0) velocity saturatlon, (tt) hot carrier
(a) Write the matn reason for the occurrence of (v)
injection, and (ti) mobilíty degradation. Explain the veloctty saturation
effect. Substanttate your answer with a suitable diagram.
irverter and explain 1 2,3
Q1 (b) Compute the total value of load capacitance (C) of a loaded
it with a suitable diagram.
the [5] 2 3, 6
Q2 (a) (0) A wire, which ts 10 cms long and 1 um wide, is routed on the polycide,
resistance of
sheet resistance of which 4 Ohm-per-square. Compute the total
the wire. (#) Wrte down the desired characteristics of the input pad. (i11)
Schemattze fnput pad electrostathc asehich (ESD) protectlon circuit. 3
Q2 (b) Sketch gate-level schematics of a trstate
may be used in an output [5]) 2
pad, and explain its operation.
NAND gate (S] 3 3
Q3 (a) Sketch the transistor-level circuit diagram of (i) a3-input pseudo-NMOS
ts encountered
and (f) a 4-input pseudo-NMOS NOR gate. (itt) What disadvantage
ate?
for all high input signals in the pseudo-NMOS NANDtransstor-level
Deduce the Boolean equations from the gven circult diagram. (5] 3 4
Q3 (b), (0)
below?
(t1) What function is realized by the circuit shown in Fig.
A
(1) What is the numerical value of Fwhen input signals A B0V are applled
application A B 1 V Assume that V0.4V.
after the
5) 4 5,6
Q4 (a () Schematize dynamic postve edge-triggered (master/slave) register.
(1) Argue in favour of the dynamic posittve edge-triggered (master/slave) register
for its advantages and applications. register for tts
(t) Criticize the dynamic positve edge-triggered (masterlslave)
disadvantages. PTO
4 4
Q4 (b) Explatn the approach of optimtzing sequentlal circutts with an example of
datapath for the computaton log( la+b|). Substantiate your answer with
suttable dtagram and pipelned computatton table for a brlef explanation.
[5) 5 2,3,5
Q5 (a) A MOSFET-based circutt ts gven below:
Voo
Vost
MOSFET. (} Determine
(0 In the given circuit, identify the diode-cconnected
MOSFET. () Estimate the
the region of operation of the diode-connected
resistance offered by this diode-connected NMOSFET, f A0. (tv) Express the
if=0. (v) Evaluate the voltage gaín of
output impedance of the given circuit
the given circuit if 0. 5 6
source degeneration resistor Ri)
Q5 (b) (Schemattze the CSstage with load resistor Ro andschematze
1gnoring the channel-length modulation effect, its small-signal model
anddderive the expression of its voltage gain f =0.
:25/11/2024:::M
