Date EXP.N0. Page No.
ARITHMETIC LOGIC UNIT
AIM : To design a 4 bit ALU Comprising only the AND ,OR ,XOR and ADD operations.
COMPONENTS :
1) 1-Bit ALU :4
2) Bit Switches : 11
3) Bit Displays : 5
4) Connecting Wires
THEORY :
The circuit functionality of 1 bit ALU is shown ,depending upon the control signal S1
and S0
The circuit operates as follows:
For S1=0 , S0= 0 ,the output is A AND B. For S1=0 , S0= 1 ,the output is A OR B.
For S1=1 , S0= 0 ,the output is A XOR B.
For S1=1 , S0= 1 ,the output is A ADD B.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
CIRCUIT DIAGRAM :
TRUTH TABLE :
S0 S1 Operation
0 0 AND
0 1 OR
1 0 XOR
1 1 ADD
PROCEDURE :
1) Start the Simulator as directed.
2) The pin configuration of a component is shown whenever the mouse is
hovered on any component of the palette .
3) For 1-bit ALU input Ao is in pin-9 ,Bo is in pin-10 , Co is in pin-11 (input
carry) .For Selection of operation , So is in pin-12 , S1 is in pin-13 , Output
F is in pin-8 and output carry is in pin-7.
4) Click on the 1-bit ALU component and then click on the position of the editor
window where you want to place it,Similarly add 3 more 1-bit ALU ,11 bit
Switches and 5 Bit Displays.
5) To connect any two components select the connection menu of the
palette and then click on target terminal.
6) According to circuit diagram ,connect all the components.
7) Now you give different inputs and check the result,the operations are
implemented using the truth table for 4-bit ALU given in the theory.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
OUTPUT :
Case 1:S1=0 and S0=0 , AND Operation
Case 2:S1=0 and S0=1, OR Operation
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering
Date EXP.N0. Page No.
Case 3: S1=1and S0=0 , XOR Operation
Case 4:S1=1 and S0=1 , ADD Operation
RESULT :
The construction of 4-bit ALU was completed successfully.
J.N.T.U.A College of Engineering (Autonomous), Pulivendula Department of Computer Science and Engineering