ee SYLLABUS Test and Testability - (EC822PF) UNIT - Need for testing, the problems i n digital Desi mixed analog/digital de: Sign testing, design for Fault in Digital Circuits + in testing, the problems in Analog Design testing, the problems in * test, printed-circuit board (PCB) testing, software testing, General Introduction, Controllabili y and Observability, Fault Models, stuck at faults, bridging faults, CMOS technology considerations, intermit tent faults. (Chapter - 1) UNIT =I General Introduction, to test pattern genration, test pattem generation, automatic test pate Developments following Roth's D-algoritham, UNIT- Il ‘Test Pattern generation for combinational logic circuits, Manual "m generation, boolen difference method, Roth's Dalgoritham, Pseudorandom test pattern generation. (Chapter - 2) Pseudorandom test patter generators, Design of test pattern generator using Linear feedback shift registers (LFSRs) and cellular automata(CAs), (Chapter - 3) UNIT- IV Design for Testability for combinational circuits : Basi the Reed Muller's expansion techniques, UNIT. V ic Concepts of testability, controllability and observability 'use of control logic and syndrome testable designs. (Chapter - 4) Making sequential circuits testable, testability insertion, full san DFT technique-Full scan insertion, structures, Full scan design and test, scan architectures-full scan design, shadow re methods, multiple scan design, other scan designs. (Chapter - 5) flipftop gister DFT, partial scan ayUNIT -I Introduction to Testing 1.1: Introduction of semiconductor. a> [INTU : Marks 6] The application of known input stimulus to a unit in a known state for predicting a known response is defined as testing. It is a simple concept that can be applied either to chips, boards and systems. The known response of the circuit is referred in testing definition compared against the ideal or expected response. Ans. 2 Infer dependency of input stimulus over testing process. {6G (ANTU : Marks 4) ‘Ans. : At any level the testing of circuitry can be ‘executed. For example, a circuitry from transistors to gates to macro cells to cores to chips to boards to systems, the testing can be applied. It is mandatory for any kind of testing that requires putting a known input stimulus into the input pin of unit that is to be tested. This input stimulus can be either applied in a simulator, on a tester, or from other logic within the system. The stimulus value depends on the type of system for which testing is to be done. For example, in a digital system, the applied stimulus is in the form of logic 1's and 0's. Such input applied to input pin of the circuit is known as vectors. Q.3 Show the way by which the expected response depends on a known state. SG [NTU : Marks 8] Ans. ; © When a test is carried it is mandatory to make it valid. For attaining this, the unit to be tested must be in a known state. Such testing doesn't require the type or nature of stimulus that is to be applied. In particular, when the intemal state of the circuitry is not known explicitly, there is possibility of applying any type of stimulus. The unit to be tested must act as a simple linear operator Example, when an input “A” is applied, they each time “B” occurs. The repeatable response of the unit under test Such repeatability of operations is known as determinism of a circuit, But, such conditions can't be maintained under the existence of randomness. A circuit can be kept in a known state by applying a set of initialization values. This will result in a known state unconditionally. Another way of creating a known state is to apply a hardware sevreset. This will make the circuit to be in a known logic state is termed as being deterministic # Another requirement for a test t be valid is expected response. The testing is used to evaluate a known expected response. Example, if the response cannot be evaluated, then there is no use in applying logic values ircuit. When such inputs have been initialized, is not known whether the response is truly toa cil then correct, + For digital systems, this determination requires having a preconceived notion of the system function. A specification for the given action and a truth table of logic gates are few examples for a known expected response. Such execution can be done by simulation of vectors, where to get a set of expected response vectors. These expected responses can be compared against the circuit response, The ability to evaluate the output response of the unit-under-test is generally referred to as observability. The ability to compare the cireuit response to a known expected value creates an access to the output. Similar problems of known input application persist in expected response also. The ‘output response must be detected. Such detection can be done directly or translated through “tested known —— a-y Test and g00 stru of ha ase Ans. stimu items dig ligt maxi resp repr .s F F les cu argood” logic, or through ay structure, ial logic access The output is detected and must be compared to a predetermined known value. A portion of cireuit can be ignored or masked, if the response has association with randomness or non-determinism, Q.4 Explain the process of test vector collection, ESP [NTU : Marks 7] the input is referred to as Logical 1's and 0's are the two items of input stimulus. These inputs when applied to a digital circuit, itis translated into voltage levels, Usually, digital testing has voltages of 0 V minimum and $ V maximum that represent a logic 0 and logic 1 respectively. While analog waveforms may be represented as functions of voltage or current. * Similarly, Ans. : © In electronics testing, stimulus or input stimulus when a group of inputs are applied to input pins of chip, then the stimulus is known as vectors. Example, the set of 1's and 0's applied to multiple chip pins at one clock cycle edge produces the stimulus which is referred to as vectors. A collection of vectors bundled tagether into a single file Q.5 Relate the input stimulus applied and response obtained. & pn rks 7) ‘Ans. : © The response or output response of a device during digital testing may be logic 1 or logic 0. In output, response, the concepts of unknown or indeterminate and high impedance must also exist. Such values are generally referred to as logic X’s and Z's, respectively. Voltage level evaluation is a commonly used IC testing. While, current measurement and time-based waveform analysis are commonly used techniques for description of output response. * When a testis carried it is mandatory to make it valid. For attaining this, the unit to be tested must be in a known state, Such testing doesn’t require the type or nature of stimulus that is to be applied. In particular, when the intemal state of the circuitry is not known explicitly, there is possibility of applying any type of stimulus. The unit to be tested must act as a simple linear operator. Example, when an input “A” is applied, then each time “B” occurs. The repeatable Introduction to Testing response of the unit under test is termed as being deterministic. Such repeatability of operations is as determinism of a circuit, But, such conditions can’t be maintained under the existence of randomness. A circuit can be kept in a known state by applying a set of initialization values. This will result in a known state unconditionally. Another way of creating a known state is to apply a hardware seUresct. This will make the circuit to be in a known logic state known 1.2: Testing Types Q6 Classify the testing. AEB (INTU : Marks 8] Ans. Testing is categorized into three main categories, based on the application of test. Functionality test, design verification and manufacturing test are the three domains of testing, Functionallty test * Functionality test uses a set of tests that verifies the intended function performed by a chip. It is used for verification of the logic function of a chip. Hence it is also known as logic verification test. Design verification * A set of tests that are performed on the first batch of chips from fabrication is known as design verification, ‘These tests are used to confirm that the chip operates as it was intended to perform. The existence of any sort of discrepancy can be easily identified using design verification. Hence, this test is used for debugging deviation of intended performance of a circuit. It is extensive than the logie verification tests because the chip can be tested at full speed in a system, When compared with functionality tests, the cost involved in the design testing process is high Manufacturing test * The functionality of every transistor, gate and storage clement in a chip is verified by a set of tests. Such test sets are referred as manufacturing tests. These tests are conducted on the chip by manufacturers, The chip is to be tested before it is being shipped to the customer. —— TECHNICAL PUBLICATIONS® - an up-trust for knowledge |Test and Testability The intact nature of silicon with chip is completely obtained during the testing and verification process Usually such tests are performed on manufactured chips only Q7 Explain the various levels at which testing IF performed. ae [JNTU : Marks 7] Ans. :« The yield of a particular IC is computed using the number of good die divided by the total numberof die per wafer during manufacturing process. Certain die on @ wafer may not work properly due to the complexity ofthe manufacturing process. Such malfunctions may be due to the impact of dust particles, small erystal imperfections, misalignment in photo masking. The resultant of malfunction can result as bridged connections or missing features. Hence, such imperfections in a chip are known ) ‘as fault, This fault has demanded manufacturing test of chip before a die shipped to a customer. Such test determines which dies are good in a manufacturing testing procedure. At various levels the testing of die or chip ean be performed. The following are levels at which testing can be executed. © Wafer level © Packaged chip level * Board level + System level Field level | 1.3: Need for Testing | Q.8 What are the compatible feature of test in testing platform ? BB [INTU : Marks 6) Ans. : ¢ The impact of extra logic for test on area is highly considered by design engineering. The test engineer needs to create a compatible feature of test set for testing platform. Apart from this cost of testing and performance after testing must be attained properly. The reasons for performing testing are specific customer quality assurance in environment and device reliability. requirement, competitive «To make the test cost effective, several test feature, can be included. Such process will increase the tey coverage and reduce the time it fakes to qualify th, part To enhance the testability of @ design, seven) features are added to test. Such process is known a, Design for Test (DFT). Thus, achievement of high quality metric, alleviate the ability t0 generate vector, reduction of testing time involved with vect generation and reduction of the Cost involved with the application of veetors can be obtained for an effective testing process. Q.9 Explain the role of testing. HS [INTU : Marks 8) ‘Ans. ; © When a product is designed and fabricated, then it must undergo a testing procedure before it is being supplied to the customer. If the product gets failed during the testing, then the cause for the failure must be analyzed. The reason for failure of a product during a test may be due to the following © Wrong test © Faulty fabrication process © Incorrect design ‘© Incomplete specification © When any of the above stated factors occurs, then testing procedure ends up with failure status. The testing procedure works in two phases. During phase 1, the detection of faulty occurrence condition is done and during pkase 2, a diagnostic function is executed. In phase 2, the reason for fault occurrence is examined and finds out the alternate ways to overcome the faulty condition. When such processes are properly carried out during a testing procedure, then the correctness and effectiveress of testing can be used to ensure the quality of products manufactured. These fault free products are termed as perfect products. There are certain cases in which the test procedure is good while the product fails. In such cases, the problem may be associated with any one of following processes namely fabrication, design or specification. SSS TECHNICAL PUBLICATIONS®. n up-thrus or knowledgeestan Testability | 14: Digital Design Testing 2.10 Explain the procedure for digital design testing. SSP [INTU : Marks 7] ans.: ¢ The digital design testing is done to define the logical relationship between input and output, The basic structure of digital design test holds digital stimulus generator, digital response capture and controller, The Fig. Q0.1 shows the structure of digital design testing system. Test equipment Oigta stubs |—L—___ senerater CConvaser i Denn i J+] response : captire Fig. 2.10.1 Digital design testing systems « The test equipment applies specific digital stimulus to IC pins. The inputs are applied directly to the pad of a die in case of wafer level testing. After the application of inputs, the response is captured based on stimulus. The response of the actual Circuit under Test (CUT) is then compared to the ideal response. Such response is referred.as fault free response that is stored within the tester. An IC passes a test, if the response of CUT is the same as the ideal. Whenever a variation or deviation in response from the ideal is observed, then the IC fails that particular test. * A test vector is a collection of logic values (0 s and 1s) that will be applied to the circuit under test. A test patter is a test vector with the addition of the expected output values from the circuit under test when the circuit is fault-free. A test set is a series of digital patterns. * At specific points in a time, the digital test vectors are applied. Such vectors are fixed within the software test program. The control of tester electronics and variation in time over vector-by-vector is done by digital test vectors. Apart from this, parametric testing Introduction to Testing of the IC input - output and power supply are also considered Q.11 List the test that are performed for logical testing. SG (INTU : Marks 8) © Ina digital testing environment, the controller cireuitry controls the test vector generator and test response capture electronics. When the correctness of logical function is to be ensured, then the test needs to perform intensive design testing with minimal time. For the logical testing of the IC, any of the following tests can, be performed. Ans. : Functional test ‘* The functionality of design will be thoroughly verified. The intended operation of the design will be ensured But for complex digital circuits and systems, such functional extremely time verification can be consuming and expensive Structural test ‘The testing approach concentrates on design in such a ‘Way as to stimulate faults that may exist in the design due to fabrication defects. The test results are compared with fault free circuit output. The digital vectors applied to the design will produce a different ‘output at primary output port. The results will have a deviation from fault free circuit. This demands suitable fault models to be created for modeling fabrication defects. Identifying the correct set of digital vectors to the actual fabricated circuit has to be done. Thus, digital vectors are obtained using these models. ' : | 1.5: Types of Analog Testing Q.12 Outline the various methods deployed for analog testing. JE (NTU : Marks 7] ‘Ans. : © The universal adoption of electronic switching for wireless communication system, analog testing has ‘grabbed an increased importance. Apart from this, in most other applications such as consumer high fidelity electronics, automotive electronics, and personal computer multimedia units for sound effects, intemet telephony, digital compact disc playing, etc., the system ee TECHNICAL PUBLICATIONS® - an upshust or nowldgeTest and Testability test engineer needs to give more importance to the DSP analog test methods. Such tests are used for most of the analog tests. Analog circuit tests can be classified into three categories namely design characterization, diagnostics and production test * Design characterization © It is the procedure to determine whether the design meets specifications. © Diagnostics co When a device fails a test, then the cause for device failure is determined using diagnostic test. «© Production test © As the name indicates, this test is used for large volumes of linear or mixed-signal circuits. ‘Analog Design Testing |/ 9 1.6: Problems Q13 Explain the fault modeling problems in analog design testing. EB [NTU : Marks 7] ‘Ans. : © Analog circuit testing is non-deterministc test ‘The testing process is statistical. Analog design testing must have the ability to deal with electrical noise. Usually, a considerable proportion of total testing costs are occupied by analog testing. Hence, the testing cost is gradually increasing in nature. Fault modeling problem. * Though analog testing offers many benefits, certain difficulties are also observed with respect to analog testing. The fault derivation and modeling procedure creates the difference between analog structural test and functional test © The generation of fault lists using component deviations is often performed in functional tests. Such test assumes components are faulty. But the structural test uses manufacturing defect statistics for identifying the fault starus. This is because analog circuits have complex relations between input and output signals ‘© In most cases, analog circuits are non-linear systems because the circuits are built using MOSFET. Deterministic models are inefficient for analog ae circuits. Therefore, signals are specified by @ nomina value, along with an acceptable range of values around the nominal value. Simulation and measurement inaccuracies and Ic manufacturing process variations determine the acceptable signal value tolerances, The secure prediction of fault coverage in a given test set i no known using statistical distributions of analog faults Introduction to Testing Simulation error «Expected analog circuit signal values are computed by simulation. But the accuracy is limited by the numerical accuracy of its simulation algorithm and simulation assumptions. At times, process variations introduce a range of behavior deviation even in good circuits. Q.14 Summarize the problems of analog tester. U@P [INTU : Marks 7) ‘Ans, : © Analog offsets, the effect of the load of the measurement probe on the analog circuit behavior, and the impedance of the analog probe cause measurement error in an analog tester. Apart from these, random noise is another problem with analog testers. Thus, bandwidth and measurement accuracy are limited in an analog tester. ‘© The propagation of internal analog signals to output pins may alter the signal and the circuit functionality This is frequently noticed in a mixed- signal chip. Additional analog circuit noise is increased due to the capacitive coupling between high-frequency digital signals and analog signals. A difference is created in an analog output between the good and bad machines for an analog tester. Manufacturing Process Variation * Using statistical distributions, a lage volume of integrated circuits are manufactured with various device parameters. A significant impact of process variations is observed in component perameter values. Analog design and circuit layout techniques are present to minimize the effects of temperature and diffusion gradients in circuit layouts A parametric fault refers to component value variations. — TECHNICAL PUBLICATIONS® - an up-hrust for knowedgeTest and Testabiti | 1-7 : Problems in Mixed Analog / Digital Design Testing 2.15 Illustrate the problems in mixed analog / digital design testing. ae ‘Ans. # In recent days, it is observe In order to reduce the assembl ‘on the same chip itself, The such as wireless communic real - 'd that ICs with analog, digital, and mixed - signal circuits are on the same substrate ly cost and packaging time, designers have integrated analog and digstal devices tremendous growth of mixed circuits has been observed in various applications ation, networking, multi - media information processing. process control. and ‘ime control systems. Digital cores are found in mixed-signal hardware systems. which are used digital signal processing. The digital core is surounded by analog filters, Analog to Digital (A/D) conv and Digital to Analog (D/A) converters. This is shown in Fig, Q.151 tose wot —.Frsertna]} | Senos Digital input —. Microprocessor a] oynamie RAM + Datsisgra | ogra aso ee nama | feito] snes Fig. Q.15.1 Mixed signal testing problem and system on chip * The real world communication is established with the suppor of analog portions in 2 digs! rb compared to digital transistor, analog transistors and components are vastly larger in size contains around 100 devices, while millions of devices are found in digital circuit Mixed-signal circuits make the testing cost even more of a problem, The observability sizxal circuit is low when compared to a mixed-signal system. Above all, the major portion of = occupied by analog tes itself: A single substrate holds both mechanical and elesromechanical compooe=s for performing analog and digital electronic signal processing function. At present. tesing ¢ circuits exceed 30% of the manufacturing cost of these circuits. This cost may increase furher i= future. Hence it is considered as a disturbing factor. 1.8 : Design for Test Q.16 Interpret the need for design for testability. ER NTU: Marts 2) ‘Ans. « IC design techniques that add testability Features to a hardware product design is known as Desizx is also referred as Design for Testability (DFT). Such inclusion of testing fearures makes the process oF SSE=z easier to develop. This process can be applied to designed hardware during manufacturing test. The valdssce of hardware is done by manufacturing tests. These tests ensure that manufacturing defecrs ae = reduction of manufacturing defects can adversely affect the product's correct functioning. es TECHNICAL PUBLICATIONS® - an up-thrust for knowlegeTest and Testability * The hardware manufacturing flow holds several tests that are applied at several stage of manufacturing Usually the tests applied are driven by test programs. Such programs are performed by Automatic Test Equipment (ATE). Apart from identifying the defects, test can also be used to provide diagnostic information. It provides the type of defect that made the test fail. The diagnostic information can be used to locate the source of the failure * During the testing process, the response of vectors from a good circuit is compared with the response of ‘vectors from a Device under Test (DUT). The circuit is referred to as good, if the same response is obtained: else the circuit is termed to be defective. : Printed Circuit Board Testing gi! Q.17 Explain the design flow of printed circuit board. 0 [NTU : Marks 7) Ans. : Printed Circuit Boards (PCBs) is a nonconductive board built on substrate - based structure. It is a rugged board that is used to provide electrical connection and mechanical support to the electrical components of a cireuit ‘The following Fig. Q17.1 shows the design flow of PCB. In most cases, PCBs are available in the green- Introduction to Testing colored board. In a circuit design. active and passive -¢ mounted on PCBs based on the design specifi requirements. PCB mounted components will match the form factor of the final sign. A feature of any hardware design that elevant physical components art and ions circuit de: specifies the size, shape, and other r properties of the PCB depend on the form factor. 18 List the factors that are considered for PCB design. 1] [ITU : Marks 7) ‘ans. The determination of form factor for a PCB design considers mounting schemes, and board configurations Such consideration will create an effective PCB design process. «The signal routing process among the components on a PCB are established with copper interconnects. This interconnection acts as the pathway for electrical signal. Area, power, performance, reliability, and security of a computing system are the parameters to be considered for the PCB design and test process. © The PCB designer goes through the basic steps of design flow, that is, schematic capture and simulation, board layout, and verification and validation to finalize the complete process. The design is forwarded to the design house with exact design specifications, when designer is satisfied with the final version of design, In-house design | 2 o Sfstem integration inspection and testing PCB design house BCR schematic! create board file Design specifications PCB assembly Fig. Q.17.1 PCB design flow TECHNICAL PUBLICATIONS® 1 upthuet forkrowedgeest and Testability 19 Outline the verification procedure of PCB. ae INTU : Marks 7) ans. | PCBs are common in diversity of application areas. It is important to provide utmost care in design of the PCB. The designed PCB should provide flawless ‘output during the circuit operation. Since PCB contains hundreds of components and soldering, complexity of PCB increases. This complexity has created several challenges of PCB testing. + It has become mandatory to PCB manufacturing industries to overcome the challenges and hence companies have incorporated a variety of inspections and testing methodologies. Such inspection techniques have paved a way to produce high-quality end products. + The faulty boards are identified and forwarded to repair during the inspection and testing phases, The cyclic process of getting feedback onthe manufactured board helps engineers to continuously improve the design through multiple iterations. Based ‘on the design and performance specifications, each PCB is inspected and tested by the manufacturers. Such process supports to ensure the maximum yield and reliability from the final product. This has made inspection and testing as vital stages in the PCB life cycle Q20 Outline the methods of PCB inspection and testing. GF [INTU : Marks 5] ‘Ans.: PCB inspection and testing can be performed in two different ways namely, manual and automated inspection. The following Fig. Q.20.1 shows the PCB design inspection. Detecting the placement errors on the board or solder problems in a PCB consisting of few components and solder connections is sufficient through manual inspection. Since repetitive task of inspection is Performed in manual inspection, there are chances of niistakes occurrence. * Any unidentified defect in the manual inspection stage may cause serious fault during system operation. ‘Automated Manual inspection inspection Fig. 0.20.1 PCB design inspection «To reduce the errors introduced by human involvement in the inspection process, the inspection process has been automated. © Automated inspection processes are integrated with pre-reflow, post-reflow, or both, to detect and pinpoint potential faults in a board. In automated inspection system, the misalignment and faulty status can be identified using pick-and-place machines. 21 Summarize the various PCB defects introduced due to improper design of circuit boards. E@ (INTU : Marks 7] ‘Ans. : Improper design practices have introduced variety of defects into PCB boards. The commonly found defects in the PCBs include misaligned components, incomplete solder connections, and short circuit caused by excess soldering © PCBs are expected to function according to their design parameters with no errors or failures. It has become mandatory that PCBs must perform flawlessly though PCBs can be complex, with hundreds of components and thousands of solder connections. To ensure the quality of products, PCB manufacturing industry and manufacturers of products have met the challenges by incorporating variety of inspection procedure. Based on specific design and performance specifications, each PCB needs to be inspected and tested. This will maximize final yield and device reliability. The Table Q.21.1 lists out the common defects of PCBs and its classification based on the type of defects, rate of occurrence, and relevance to soldering issues. SSS TECHNICAL PUBLICATIONS® Nn up-thrus fr knowtedgeRate of Soldering occurrence Open 25 Yes Insufficient solder | 18 Yes Shon 13 | Stmucturt | Yes Missing eleciricl 12 | Stwcturat [No ‘component Defective elecirial 8 ‘component Excess solder 3 1.10: Inspection” 2.22 Discuss the commonly used PCB Inspection techniques. EP (NTU : Marks 5) ‘Ans. : Early fault detection can be performed by inspecting boards at various manufacturing stages. By correcting the defects at testing stage yields can be improved. The commonly used PCB inspection systems are automated optical inspection and Automated X-ray Inspection (AXI). In such inspection process, visual checks are done by scanning board with the support of video cameras. The board image is created from various angles of images taken by machine. + Automated inspection system identifies the problems like nodules, seratches and stains, as well as dimensional defects such as open circuits, shorts and thinning of the solder. Such inspections are carried out by comparing board image with required PCB image Apart from the above mentioned problems, missing and skewed components are also identified by automated inspection. Such process consumes less time, At the same time greater accuracy can be attained when compared to human inspectors Q.23 Show the merits and demerits of automated PCB Inspection. SaP [JNTU : Marks 6) ‘Ans. : Merits of automated inspection * Detection of common PCB faults. Introduction to Texting + Deployment of inline inspection at several points in the PCB manufacturing process Demorits of automated Inspection © Unable to inspect hidden connections in underneath packages; «Less effective inspecting for densely loaded boards. | 1.11: Testing lure of performing In-circult GF [NTU : Marks 6) 1g once manufactured 0.24 Explain the proced! testing. ‘Ans.: © A PCB gets ready for testing PCB passes all of its inspection stages. There are two widely used methodologies for testing, namely In-Circuit Testing (ICT) and Functional Testing (FCT). In-circuit ‘measures each component's parameter with test This measure ensures correctness of each testing equipment. component placement. An electrical probe tests the entire PCB identifying shorts, opens, resistance, capacitance and other factors to show if it was correctly made. A simple fixture holds the board, and the probes move around the board, making contact as required. Probe movements are controlled by software so any board updates can be accommodated with programming changes. Functionality of a board cannot be checked by in-circuit testing, Merits of In-circult testing * Identifies the defects such as solder shorts, missing components, wrong components and _—_ open connections. * Performs tests without power being applied to the DUT. Domorits of In-circult testing © Requires costly test fixtures © Requires detailed programming for controlling probe movement * Continuity through connectors cannot be checked Connector faults cannot be identified Q.25 Why Ie it mandatory to perform functionality testing ? (Sa [JNTU : Marks 7) ‘Ans. : © It has become mandatory to ensure the functionality of PCB. Thus, to test a PCB's functionality, —— TECHNICAL PUBLICATIONS®. 31 uptrust for knowiegeestan stably «functional fester interfaces 00 the PCR via it edge conmecleroF | FeSEPFObe point can be performed. Such provision WHE reveal the PCBS fing electrical eqn eXtcty, Futon testers are ten og igue aS a product being tested See This emphasizes sandantization 0 fest equipment by manufacturers, venoe the Cost of equipment can be reduced Os —rtrtrtsS—— cabinet, an interface to the DUT, cabli Ing to connect all of the instruments, a cen al processing unit and monitors. The hardware used gets varied based on the DUT and the environment in which it will be used Functional testing is specific tothe DUT soit requires investment of both money and time to yield assured suceess, + Functional testing is not a perfect solution. It involves «fot of variability, including how much of the PCB is going fo be tested, what inputs or stimuli are needed, definition of desired results and delineation of testing parameters, Narts of functionalty testing + Testing process is complex + Identifies functional defects within a PCB * Determines DUT power consumption during operation * Uncovers problems with analog and digital circuitry Demerts of functionality testing © High cost * Programming requires a thorough understanding of the DUT and its working environment * Utilizes expensive high-speed instrumentation to characterize signals from the DUT * Testing done through connectors can have reliability issues 1.12: Controllability 0 25 Explain the controllability of an internal circult. ESF [ANTU : Marks 6) Ans. : © The controllability of an intemal circuit node “thin a chip is a measure of the ease of setting the node Introduction to Testing to a 1 or 0 state, This metric 1s of importance when assessing the degree of difficulty of testing a particular signal within a circuit. An easily controllable node would be directly settable via an input pad. © A node with little controllability, such as the most significant bit of a counter, might require many hundreds or thousands of cycles to get into correct state. It is often impossible to generate a test sequence to set a number of poorly controllable nodes into the correct state. Hence, a chip designer must aim to make all ncdes easily controllable. Making all flip-flops resettzble via a global reset signal is one step toward g00d controllability 1.13: Observability 2 Q.27 How to compute the ability of signal at a node by controlling circuit input ? BH [INTU : Marks 8] ‘Ans. : Observability is defined as ability to determine the signal value at any node in a circuit by controlling the Circuit's inputs and observing its outputs. It is the degree to which output of a circuit can be observed at a particular node. This value can be used to measure the output of a gate in an entire circuit. Repeatability * When a circuit functions correctly, then such circuits can be referred as a circuit with repeatable nature. It is commonly observed in combinational logic and Synchronous sequential logic, where the output of a Circuit is always repeatable when it is functioning correctly. There are few cases in which repeatable nature cannot be observed. In particular, asynchronous Circuits are nondeterministic, so repeatable output cannot be obtained, For example, an arbiter may select either input when both arrive at nearly the same time. Thus to define the Tepeatable nature of a circuit, the term repeatability can be used. * The repeatability of system is the ability to produce the same outputs given the same inputs. Testing is much easier when the system is repeatable. Some systems _—_—_————— TECHNICAL PUBLICATIONS® on upsnast or knowledge‘Test and Testability with asynchronous interfaces have a lock-step mode to facilitate repeatable testing. Survivability © The ability of a system to continue function after a fault is defined as survivability. For example, in presence of soft errors, an error - correcting code provides predetermined function. © Redundant rows and columns in memories and spare cores provide survivability in the event of manufacture fault. Few of the survivability features are invoked automatically by the hardware, while others are activated by blowing fuses after manufacturing test. 1.14 : Fault Coverage Q.28 Explain the procedure for calculating fault coverage. (B® [INTU : Marks 6) ‘Ans, : © Fault coverage is the degree of measure of goodness of a set of test vectors. For the vectors applied, the percentage of the chip’s internal nodes that were checked is given by fault coverage. © Procedure for fault coverage calculation 1. Fora given sequence, each circuit node is held to 0 i.e Stuck-at-zero (S-A-0), 2. Circuit is simulated with the test vectors comparing the chip outputs with a known good machine. 3. Node is tuck at 0 and 1 sequentially 4. Discrepancy detection between the faulty machine and the good machine 5. Mark the fault 6. Stop the simulation Q.29 Explain the procedure for calculating fault coverage I | Marks 6) Ans. : Similar procedure to be followed for the node stuck to 1 i.e Stuck-at-zero (S-A-1) 1. Fora given sequence, each circuit node is held to 1 (S-A-1). 2. Circuit is simulated with the test vectors comparing the chip outputs with a known good machine 3. Node is stuck at 1 and 0 sequentially Lu Introducton to Testing 4, Discrepancy detection between the faulty machine and the good machine 5. Mark the fault, 6. Stop the simulation ‘+ Thus, when the veetors are applied to a circuit, then the fault coverage of a set of test vectors states the percentage of total nodes that can be detected as faulty. To achieve world-class quality levels, circuits are required to have in excess of 98.5% fault coverage, | 1,15: Fault Models 2.30 List the various defects observed during testing procest 1 [INTU : Marks 7] ‘Ans. : In electronic systems, the terms defect, error and fault are commonly used terminologies to define the incorectness of a system. To avoid the confusion between terminologies used in testing, the following definitions are given below. * The unintended difference between the implemented hardware and its intended design in an electronic system is defined as defect. Process defects, material defects, age defects and package defects are few of the typical defects in VLSI chips. The following are the types of defects observed in a chip. *# Process Defects © Missing contact windows, parasitic transistors, oxide breakdown, etc. © Material Defects © Bulk defects (cracks, surface impurities, etc, crystal imperfections), © Age Defects © Dielectric breakdown, electro migration, ete. * Package Defects © Contact degradation, seal leaks, etc, h defects occur in a chip. EE [NTU : Marks 6) Ans. : ¢ There are two different ways in which a defect can occur. Either during manufacture or during the use of devices a defect can occur in a chip. In a manufacturing Q.31 List the various by wi LETT ———— TECHNICAL PUBLICATIONS® an up-hrust for knowsedgespat on Test pots, te term defect can be used as an indicator for ingens ManUfACUFing proces oF design a4 evioe. «The repeated occurrence of the same d lefect can also be used for diagnosis of the faulty condition. The Iowledge on defect can be applied for deriving the procedures for diagnosing defects and finding the cause of defects. This analysis is known as Failure Mode Analyses (FMA) ror + The outcome of defect is termed as ertor. When a deviation of output is observed in a system for an applied input, then the output signal generated is teamed at sor. I is 8 wrong outat sigoal produced by a defective system. It is also referred as effect caused by a defective system, Fault * At the abstracted function level, the deviation in system performance is stated as a fault. The difference between a defect and a fault is rather subtle. It can also be quoted as an imperfection in the hardware and function, 1.16 : Levels of Fault Models Q32 Infer the relation between fault modeling and design hierarchy. BS [NTU : Marks 7) ‘Ans. « It has become mandatory to model faults during circuit modeling itself. This is because these two models are closely related. In the VLSI design hierarchy, the level refers to degree of abstraction. The behavioral level is also referred as high level, where it has fewer implementation details. The fault models at this level do Tot have noticeable correlation to manufacturing defects. High level fault models play a vital role in the simulation- based design verification only. The impact of high level fault model is not observed in testing. * The Register Transfer Level (RTL) or logic level Consists of a net list of gates and the stuck-at faults at {his level are the most popular fault models in digital ‘esting. Other fault models at this level are bridging Introduction to Testing. faults and delay faults. Bridging faults mainly focuses fon delay faults. Transistor and other lower levels which are referred to as component levels include stuck open types of faults. It is also known as technology-dependent faults. Component level faults are mainly modeled in analog circuit testing only. ‘Apart from the above listed fault model, there are fault models that may not fit any of the design hierarchies, Example for such type is the quiescent current defect. The advantage of this model is that physical defects are represented, while other model does not have that ability. Hence, such models are known as realistic model ‘* It is mandatory to propose a fault model because to tackle with the existence of good and bad parts of a circuit. A model will show the extent of fault occurrence and their impact on circuits. The most Popular model is called the Stuck-At model. While the other model is Short Circuit / Open Circuit model that can be a closer fit to reality. But it is harder to incorporate into logic simulation tools. or 1.17 : Stuck at Faults Q.33 Define stuck at fault and list its types with a neat sketch. ES | Marks 8) ‘Ans. : © The Stuck-At-Fault (SAF) is a fault model that considers a fault to create nodes within the design to be stuck at a logic level. The logic level can be either zero or one. The SAF is considered to detect unmodelled fabrication defects. For detection of stuck-at-fault, each node is considered in tum to be Stuck-At-Zero ($A0) and then Stuck-At-One (SA1). The effect of the fault needs to be propagated to the primary output in order to set an Output that logically differs between the fault-free and faulty circuits. In order to set the opposite logic level at the node to value of the stuck-at-fault, primary inputs are set. The Fig. Q33.1 shows the stuck at fault model, A node is considered to be either stuck-at-logic 0 (SAO) or stuck-at-logic 1 (SA1), TECHNICAL PUBLICATIONS® - an up.thrust for knowiedgeTest and Testabti -# Node SAD Al nodes are considered 4 tobe SAO or SAT Primary ‘inputs. Check that the primary <= Inputs can be sel-up 20 thal they set the considered ‘node to ar Pomary ‘output (=D Check that the fautt effect is propagated to he primary output Fig. 0.33.1 Stuck-at-fautt 0.34 Discuss the reasons for logical fault in a circuit. ES (NTU: Marke 7] ‘Ans. : An assumption is made that a defect within the circuit will certainly cause logical fault. There are Possibilities of a circuit to act in any of the three cases mentioned below. Fault-free operation * It is a case in a circuit where no fault is considered to be absent. Hence the working of such circuits is referred as fault free operation. Single-Stuck-at-Fault (SSAF) operation * When a only one fault assumption is made, then the circuit is considered to contain a single stuck-at-fault. Multiple-Stuck-at-Fault (MSAF) operation © This case of circuit operation is similar to single stuck at fault, But the difference is the circuit holds many fault assumptions. Thus, the circuit operation is known as multiple stuck-at-faults. * In the Stuck-At model, a faulty gate input is modeled as a stuck at zero (Stuck-At-0, S-A- 0) or stuck at one (Stuck-At-l, S-A-1). This model dates from board-level designs, where it was determined to be adequate for modeling faults. Fig. Q.34.1 shows how an S-A-0 or S-A-I fault might occur. These faults most frequently ‘occur due to gate oxide shorts (the nMOS gate to GND or the pMOS gate to VDD) or metal-to-metal shorts. =) = 2 a b>. = = p> td ta) el ‘SAO Fig. 2.34.1 Stuck-at-fault (SA1 /SA0) 3 upshrst for knowiedse TECHNICAL PUBLICATIONS®1.18 : Bridging Faults a35 Explain the modeling of detect ortented fault sing PLAS. 53 (ONTU: Man ans.: Usually modeled at the gate or transistor I ks a tridging fault repy stor level, a Tl ayedeledas 1 - dominant (OR bridge), twidge) oF indeterminate, dependin, in which the circuit is implemented. Non-feedbeck tridging faults are combinational and c srck-at fault tests is normally very high, While in feedvock bridging faults, the fault coverage is not to high Bridging foults are often used as examples of “dfect-oriented faults”. Such faults can also be modeled in Programmable Logic Arrays (PLAs). The bridging {ault considers two or more nodes that are unintenti connected, An example for such type of fault is iaemen of metal interconnect layer close to adjacent metal imerconnect layer in a physical circuit layout. Low resistance value bridges are commonly considered. To identify the interconnect that may be bridged, the following can be used. 0 dominant (AND '8 Upon the technology their coverage by Circuit schematic + The nodes within the circuit net list are used. All nodes may be considered, but this can lead to a large number of bridging faults. The fault list does not reflect the Physical positioning of the faults on the layout. Cteuit layout * The nodes within the circuit that are physically close on the layout can be considered. The number of bridges can be reduced. The potential bridging fault is Probability of occurrence of bridged faults that are Physically close on the layout and run close to each other for a substantial distance. 36 Determine defect oriented fault. UB (NTU: Marks 6] + The bridging faults can be determined from the yout using Inductive Fault Analysis (IFA) techniques. TFA methodology can be executed using critical area or Monte Carlo technique. The critical area technique is a Sometry based method. Monte Carlo is based on Randomly scattered defects on a layout. IFA has been used Ans, L ae ie u Introduction to Testing in the creation of fault lists based on a defect oriented approach for testing, It has been used for the extraction of ‘a range of component and interconnect faults. Digital fault simulation can be used in case if creations of bridging faults are logical in nature. Q.37 Show the schematic representation of bridging fault models. | [JNTU : Marks 6] Ans. : Bridging faults can be analyzed using analog or digital simulation model, When a fault to be modeled is resistive in nature then analog simulation can be employed. If the fault to be considered is at the transistor level, then digital simulation can be deployed to detect the fault. However, analog fault simulation is time consuming when compared to digital fault simulation. Apart from this, analog fault simulation needs extensive computing facilities for fault determination. There are possibilities of ascertaining the value of resistive connection between the nodes in analog simulation. The figure shows the representation of a bridging fault model. schematic =D) Nose 1 : | Faultres design Node 1 \ Wired-AND fautt Node 2 Wired-OR fault Resistive faut TecHNicat PUBLICATIONS® Fig. Bridging fault models 3 upstust er nowledgerls Test and Testability ‘The bridging foult model can be either a Wired - AND or Wired - OR type. When the fault modeled in Wired - AND has logic 0 to be dominant in two nodes that are considered for analysis. In case of Wired - OR, sidered and the fault is modeled to two nodes are con: be logic 1 dominant. | 1.19 : CMOS Technology Considerations 2.38 Explain the technology consideration for design defect free circult. EH [INTU : Marks 7) Ans. ; © The International Technology Roadmap for Semiconductors (ITRS) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing demands for performance. An exponential increase in leakage current and large variability in threshold voltage both within and across dies is the resultant of scaling. Hence, designers are required to implement innovative aggressive power management strategies to meet the power constraints. Thus, testing will be varied based on the exponential increase in leakage, the device parameter variations and aggressive power management techniques. * Defect - free Integrated Circuits (IC) cannot be guaranteed by VLSI circuit manufacturers. Circuit complexity, IC defect anomalies, and economic considerations prevent complete validation of VLSI circuits. These VLSI test problems are especially acute in high-reliability designs and will only worsen as IC circuit size increases. Designers of IC, board, and system projects must be aware of the difficult engineering challenges that are involved in verifying high - quality ICs. Q.39 Explain the term intermittent fe 1@ [NTU : Marks 4) ‘Ans. : + Certain faults exhibit time dependency during testing process. One such fault is intermittent fault. It is a fault that appears and disappears as a function of time ‘Assume there is a fracture in circuit interconnects. Such fractures may produce an intermittent open. This circuit opening occurs ahead in a circuit, before it becomes a permanent fault. Intermittent faults can be of any type > Atroducton to esing e.g, stuck-at fault or a bridging fault. The presence ofan of these faults is time dependent. : 40 Infer the relation between cost reduction ang fault coverage during testing process. 1 (OKT: Maks Ans. : The role of testing can be increased based onthe requirement ofthe customer. Often a tradeoff requiremen, between cost reduction and fault coverage is high, needed for a product and product application area. Then are few issues to be addressed irrespective of application area, The following are the issues to be addressed for testing product + Increased device functionality © Increased circuitry per mm’ of silicon area and higher operating frequencies + Reduced physical size ‘© Support miniaturization of the product and aig portability + Lower cost + Tradeoff between higher performance and cost factor The cost to test an IC is of primary concer given thee main points : © Cost of design is reducing. ‘© Cost of fabrication is reducing. # Cost to test relative to the cost of design and fabrication is increasing. 1.20: Computer Aided Test | Q41 Explain the role of computer aided system in testing process. GP [NTU : Marks 7) ‘Ans. : To improve the design activities, there is a need for more sophisticated software design and analysis tools Computer Aided Design (CAD) has evolved to product software design tools that allow for the efficiency and effectiveness needs of the designer. Thus, a circu! designer can meet the trends towards increasiney complex IC products. TECHNICAL PUBLICATIONS® - an up-thrust for knowledgeestan Tstabilty 4 ncarler days, the test was sup tools that have supported desi of technologies, a close link hy test development and design are now used to support generation of the test progran (CAT) tools provide the software tools that lnk invo the design database and allow for Test Program Generation (TPG) to be effectively undertaken, 42 Explain the virtual testing process in ATE Ported with the types of en. But, with the advent 'as been ereated between Activities. Sofware tools he test engineer in the ms. Computer Aided Test ES [NTU : Marks 6) ans: # As the technology gets advanced, the device complexity also gets increased. This has subsequently aggavated the problems associated with the creation of tet programs. The reduction test program development time is highly demanded in recent days. Thus, to address this isoue virtual test can be deployed. It uses a software model of the design, a model of the ATE and the test program in order to simulate the operation of the test program prior to application on the ATE itself. + Hence, through simulation, the development and debugging of the test program can be done, It also has a direct link to the target ATE. It allows for much of the test program development and debugging to be undertaken prior to device fabrication and without the need to undertake the tasks directly on the ta‘get ATE | Fillinthe Blanks for Mid Term Exam = 1. The application of known input stimulus to a unit ina known state for predicting a known response is defined as , Q2 The stimulus value depends on the type of for which testing is to be done. 3 The way of creating a known state is to apply a hardware Q4 The ability to evaluate the output response of the unit-under-test is generally referred to as Introduetton to Testing Q5 Digital testing has voltages of minimum and maximum that represent a logic 0 and logic | respectively Q.6 When a group of inputs are applied to input pins of chip, then the stimulus is known as ar and are commonly used techniques for description of output response. as as Testing is categorized based on the test uses a set of tests that verifies the intended function performed by a chip. Q.40 Another name of functionality testis Q.11 A set of tests that are performed on the first batch of chips from fabrication is known as Q.42 Design verification test is used for of intended performance of a circuit. Q.13 The digital design testing is done to define the logical relationship between and Q.14 A test pattern is a test vector with the addition of the expected output values from the circuit under test when the circuit is : Q.45 When a device fails a test, then the cause for device failure is determined using Q.46 During testing process, the response of vectors from a good circuit is compared with the response of vectors from a aay are integrated with pre-reflow, post-reflow, or both, to detect and pinpoint potential faults in a board. Q.18 In testing, probe movements are controlled by so any board updates can be accommodated with programming changes. Q.49 The ability of a system to continue to function after a fault is defined as 20 is the degree of measure of goodness of a set of test vectors Q.21 To achieve world-class quality levels, circuits are required to have in excess of % fault coverage, a ‘TECHNICAL PUBLICATIONS - an upstrust for knowedge