TEST & TESTABILITY

UNIT-1(PART-A)

NEED FOR TESTABILITY

Why Testing is Needed in Electronics?

Whenever a company designs and manufactures a product, it goes through a design phase,
followed by testing (usually of a prototype) before starting mass production.

But testing each and every final product completely is too expensive and time-consuming,
especially when the product is very complex — like microelectronics or integrated circuits (ICs).

 For mechanical parts, you can inspect them visually.

 But for ICs, visual inspection doesn’t work — everything happens inside the chip.

 So we must use parametric or functional testing (i.e., apply inputs and check outputs).

(Five Main Stages)

1. IC Manufacturer’s Fabrication Tests:

o Done on the wafer to check manufacturing steps.

o Uses "drop-in" test circuits inside the wafer.

o OEM has no role here.

2. IC Design Testing:

o Ensures that the prototype IC design works properly.

o Usually done by the vendor, but if it's a custom chip (ASIC/USIC), OEM is involved.

3. Production Testing by Vendor:

o Ensures that mass-produced chips are working (no defects).

4. Acceptance Tests by OEM:

o OEM may test the ICs they receive to check if they work correctly.

5. Product-Level Testing by OEM:

o Testing the final product that contains ICs.

 For regular off-the-shelf ICs, the vendor handles steps 1–3, and the OEM
handles 4–5.

 For custom ICs (ASICs), the OEM and vendor work together for step 2.

Challenges in Testing

 In small/simple circuits, the OEM can test everything.

 In large/complex systems (e.g., microprocessors with millions of gates), it’s
impossible to test every condition.
  VLSI (Very-Large-Scale Integration) increased the need for testing but made it
harder due to:
o Complex designs
o Limited pins
o Tiny defects not visible externally

If there are errors in production or incomplete testing, faulty ICs can pass the tests and
cause failure later.

A Simple Example:

 Suppose production process gives 50% working ICs (F = 0.5)

 If no testing is done (FC = 0) ➜ 50% faulty ICs!
 If testing detects 80% of faults (FC = 0.8) ➜ Still 15% ICs will be faulty after
testing!
(That’s 1 out of 7 — still too high!)

So:

High production quality (F) + High fault coverage (FC) = Low defect levels (DL)
PROBLEMS IN DIGITAL DESIGN TESTING

First, it may be appropriate to define three basic terms which arise in digital circuit testing.
These are:

(i) Input test vector (or input vector or test vector): this is a combination of logic 0 and 1
signals applied in parallel to the accessible (primary) inputs of the circuit under test. For
example, if eight primary inputs are present then one test vector may be 01110011 .

(ii) Test pattern: a test pattern is an input test vector plus the addition of the fault-free output
response of the circuit under test to the given test vector. For example, if there are four
accessible (primary) outputs, then with the above test vector the expected outputs might be 0,
0, 0, 1.

(iii) Test set: a test set is a sequence of test patterns, which ideally should determine whether
the circuit under test is fault free or not. As will be seen later, a test set may be a fully-
exhaustive, a reduced or minimum, or a pseudorandom test set.
Main Problems in Digital Testing

2. Testing Combinational Circuits

These circuits don’t have memory — output only depends on current input.

🧮 But if there are n inputs, then there are 2ⁿ combinations (like a full truth table).

📌 Example:

 For n = 32, there are 2³² = 4.29 billion combinations!

 Even at 10 million tests per second (10 MHz), it takes about 7 minutes to run all
tests.

📌 And you also have to check all output values for each input combo. This is a huge task!

3. Testing Sequential Circuits

Sequential circuits have memory (flip-flops/latches), so output depends on:

 Current input
 Internal stored state

🧮 So if the circuit has n inputs and s storage elements:

 You need 2ⁿ × 2ˢ = 2ⁿ⁺ˢ test vectors to test all conditions.

📌 Example:

 A 16-bit accumulator has:

o n = 19 inputs (16 data + 3 control)
o s = 16 storage units (like flip-flops)
o Total combinations = 2³⁵ = 34+ billion
 At 10 MHz, it takes about 1 hour to run these tests.

The Real Challenge

Testing itself is not hard, but:

 Number of test combinations is huge as circuits grow.

 You can only apply inputs and read outputs using the limited number of pins.

 This is called the "pin-limited" problem.

 For big circuits, testing every possible case is not practical.

📌 Therefore, we use:

 Reduced test sets

 Random/pseudorandom patterns

 Design for Test (DFT) techniques to make testing easier

PROBLEMS IN ANALOG DESIGN TESTING

While digital circuits have many simple gates (0s and 1s), analogue circuits usually have:

 Fewer components, like op-amps, filters, amplifiers, etc.

 But each component is more complex than a digital gate.

In digital, you just check if the output is 0 or 1 (correct or wrong).

But in analogue, you must test many performance characteristics, like:

Parameter Meaning

Gain How much the circuit amplifies a signal

Bandwidth Range of frequencies it can handle

Signal-to-Noise Ratio (SNR) How clean the signal is (vs noise)

CMR (Common Mode Rejection) How well it ignores noise common to both inputs

Offset Voltage Output voltage when input should ideally be zero

So even if an analogue IC "works", it may still perform poorly, and that also counts as a fault.

How Analogue ICs Are Tested

✅ During Prototype Phase (By Vendor)

 Very thorough testing is done to check:

o Fabrication quality (wafer checks)

 o Circuit behavior (gain, noise, etc.)

 Vendor ensures parameters are correct before starting mass production.

✅ During Production

 Vendor still needs to test production ICs to make sure:

o No defects from the fabrication process (like surface dust, mask issues)

o Performance is still within the expected range

 Usually, a subset of prototype tests is applied (since full testing of every chip takes too much
time/cost).

The actual testing of analogue ICs involves standard test instrumentation such as waveform
generators, signal analysers, programmable supply units, voltmeters, etc., which may be used in the
test of any type of analogue system.

Testing is done using standard lab equipment:

Instrument Purpose

Waveform Generator Sends test signals into the IC

Signal Analyzer Checks output waveform quality

Voltmeter Measures voltages

Programmable Power Supply Provides accurate power to the IC

These are usually set up in a rack, connected by a bus system (called GPIB, like USB but for lab tools),
and controlled by a microcontroller or computer. This is called:

 Testing is more challenging because:

o Each custom IC is different

o Needs expert-level knowledge

  So the OEM and vendor must work very closely to:

o Define test requirements

o Agree on acceptable performance levels

PROBLEMS IN MIXED ANALOG/DIGITAL DESIGN TESTING:

These are combined circuits that have:
 A part that handles analogue signals (like real-world voltages)
 A part that handles digital signals (like 0s and 1s)
📌 Examples:
 A system that takes in sound (analogue), converts it to digital (A-to-D), processes it,
and converts it back to sound (D-to-A)
 Microcontrollers with built-in sensors
Problems
1. Analogue and Digital Parts Need Different Testing Methods
 You learned earlier:
o Analogue: tests things like gain, noise, voltage
o Digital: tests logic 0/1 outputs for given inputs
Because they’re so different, you often have to:
👉 Test them separately
It can be done by -> You need to bring the interface point (where analogue connects to digital) to
the outside of the chip so you can apply tests to each part independently.

2. Sometimes You Can Test Without Interface Access

If the circuit is simple, like:
 A-to-D → Digital Processing → D-to-A
...then you might be able to test the whole thing as a black box (input signal → output
signal), without breaking it into parts.
But:
❗ Not all circuits are this simple — most need custom test procedures.
Modern Solutions
✅ Option 1: Use Special Signals to Combine Tests
Some researchers are working on ways to:
  Use multi-level signals or bit streams to test analogue parts
 Use controlled analogue voltages to test digital parts
But:
🚧 These techniques are still experimental and not widely used in the industry yet.

✅ Option 2: Use Combined Analogue + Digital Test Systems

The more common and practical solution is to build a test setup that includes:
 Analogue test instruments (signal generator, voltmeter, etc.)
 Digital test equipment (pattern generators, logic analyzers)
 A computer controller (host processor) to run the test program
📊 This is shown in Figure 1.6 of your text — everything connected using a bus system (like
GPIB).

DESIGN FOR TEST

When a circuit or system becomes very complex (like VLSI ICs), testing it can become:
 Time-consuming
 Expensive
 Or even impossible using regular testing methods
That’s why we need to plan for testing from the beginning — during the design stage itself.
This is called Design for Test (DFT)
DFT means adding extra features to the circuit — not for normal operation — but only to
make testing easier.
DFT Features Can Be:

Feature Purpose

✅ Extra I/O pins To observe or control signals inside the chip

🔁 Breakable connections Temporarily disconnect feedback loops for testing

🧩 Circuit partitioning Break a big circuit into smaller blocks to test individually
Feature Purpose

Parts of the circuit behave differently in “test mode” vs normal

🔄 Test modes
mode

One powerful DFT method, especially for digital VLSI circuits, is the:
Scan Test — using serial bit streams
How It Works:
 You shift in test data (like pushing bits into the circuit)
 Circuit processes the data
 You shift out the output as another bit stream
 Then compare output with expected result
This is used especially when:
 The chip has few external pins (pin-limited)
 You can’t apply wide test vectors in parallel
Downside:
 Increases circuit complexity
 Uses more chip area
 Can increase cost
But the benefit is reliable and efficient testing, even for very large circuits.

The GPIB (General Purpose Interface Bus) connects everything together so they can
communicate and synchronize.
✅ This setup allows a test engineer to:
 Send signals
 Collect outputs
 Automate testing for both analogue and digital parts of a mixed-signal IC

PRINTED CIRCUIT BOARD TESTING:

Every electronic system uses Printed Circuit Boards (PCBs) to connect and hold components
like ICs, resistors, capacitors, etc.
To make sure everything works properly, PCB testing is done in three major phases:
 Bare-board testing
 In-circuit testing
 Functional testing
1️. Bare-board Testing
 Done before any components are mounted on the board.
 Checks whether all the copper tracks and connections are properly made.
 Used mainly for continuity testing (ensuring there are no broken or shorted lines).
 For complex boards, bed-of-nails fixtures (lots of test probes) and automated testers
are used.
2️. In-circuit Testing (ICT)
Goal: Check individual components (like resistors, capacitors, ICs) after mounting, but not
the full circuit operation yet.
How it's done:
 Uses a bed-of-nails fixture to connect to many test points at once.
 The board is not powered on during passive testing (resistors, capacitors).
 Uses a special circuit (shown in Figure 1.7) to test components like
resistors/capacitors while they’re still connected in the circuit.
In this figure, we want to measure the impedance Zx (like a resistor, capacitor, or
inductor) while it is still connected on a board.
🌟 Key Idea:
Even though Zx is connected to other components (Z1, Z2), the circuit isolates it during
measurement using a virtual ground at the op-amp's input.
🧠 How it works:
1. A source voltage Vs is applied.
2. Z₁ and Z₂ are grounded — making most of the current flow through Zx.
3. The op-amp measures the output voltage Vout.
4. Using the formula:

This gives the value of the component without removing it from the circuit.
What about active components like ICs?
 You need to power up the board with its normal power supply.
 For analogue ICs (like op-amps), give test inputs and check the output.
  For digital ICs, apply forced logic pulses (0 or 1) to gate inputs and monitor outputs.
o These pulses are short (e.g., 10 μs) to avoid damaging other parts of the
circuit.
🛑 ⚠️BUT: As ICs became more complex (LSI/VLSI), in-circuit testing became difficult or
unreliable.
3. Functional Testing
This is the final test — check the full circuit operation just like it would work in real life.
🎛 How it works:
 Connect to the normal I/O ports (not internal test points).
 Give real inputs, see if expected outputs come out.
 This is like a system-level test.
⚠️Cannot be done with bed-of-nails — needs to go through actual ports (like USB,
Ethernet, etc.).

SOFTWARE TESTING
In today’s systems:
 Software is everywhere — from your phone and washing machine to aircraft control
and emergency services.
 In many cases, software development takes more time and cost than the hardware
itself.
 If software doesn’t work correctly, the whole system may fail — even if all the
hardware is perfect.
Real-World Examples of Software Issues
 Airport baggage handling systems failing due to timing or control software bugs.
 Emergency services (police, fire, ambulance) getting delayed due to poor software
coordination.
 These failures show that software bugs can have serious real-world consequences.
Software must be tested to ensure that it behaves correctly and reliably, not just during
normal use, but also in extreme or unexpected situations.
Software should be tested for:
1. Extreme inputs (e.g., very high/low values, memory overload).
2. Different input sequences (like unexpected orders or combinations).
 3. Faulty input data (e.g., missing, wrong, or corrupted data).
4. Abnormal conditions (e.g., slow response, unexpected user behavior, system
crashes).
Some of the hidden or unexpected software faults that:
 Don’t occur all the time.
 Are hard to detect.
 Often only happen in rare, complex situations.
🔍 Types of Sneak Conditions:

Type What it means

Sneak Output Software gives wrong output even though inputs are correct.

Sneak Inhibit A valid input or output is mistakenly blocked from working.

Sneak Timing Output is generated at the wrong time, due to timing bugs.

Sneak Message Program shows the wrong status or error message.

These are very dangerous because they don’t show up in basic testing, but can cause major
failures in real use.
Why Is Software Testing So Hard?
 Complex software (especially in VLSI or distributed systems) has millions of lines of
code and possible conditions.
 It's impossible to test every possible input and situation.
 So, like in hardware testing, we aim for high coverage, not 100%.

🧪 What’s Being Done About It?

 Computer scientists and software engineers are developing:
o Reliability models – to predict and measure how likely software is to fail.
o Simulation tools – to test how software reacts in different conditions.
 But it’s still a specialized field, especially important in:
o Medical devices
o Aircraft systems
o Autonomous vehicles
o Emergency response systems
UNIT-1 (PART-B)
CONTROLLABILITY and OBSERVABILITY:
The basic concept of controllability is simple: it is a measure of how easily a node in a digital
circuit can be set to logic 0 or to logic 1 by signals applied to the accessible (primary) inputs.

In the circuit from Figure 2.1,

To control node 7, you need to carefully adjust E, F, and G.
You try two different input combinations:

 E=0, F=1, G=1 ➝ Output is 1

 E=1, F=1, G=1 ➝ Output becomes 0
This shows how controllability gets harder as you move away from inputs

OBSERVABILITY:
the concept of observability is simple: it is a measure of how easily the state of a given node
(logic 0 or logic 1) can be determined from the logic signals available at the accessible
(primary) outputs.

Example:
In Figure 2.3, to observe node 2 through the output Z, you must:
 Set node 1 = 1, node 4 = 1, node 6 = 0
This way, node 2 directly affects output Z.
If you can't propagate the internal value to the output, the node is not observable — and
faults in it might go undetected.

CHARECTERISTICS:

Controllability and Observability Together

They go hand-in-hand:
 You must control a node to check it.
 You must also observe the result at output.
That's why the product of both is often used:
FAULT MODELS:
When testing digital circuits (like ICs), we can’t test every possible problem directly — there
are too many.
Instead, we assume a small set of common fault types, and generate test vectors (input
patterns) to check for these faults.
If all the tests pass, we assume the circuit is working correctly.
This process is called:
✅ Structural Testing
✅ Automatic Test Pattern Generation (ATPG) when done by software tools
The faults in digital circuits which are usually considered are:
(i) stuck-at faults
(ii) bridging faults
(iii) stuck-open faults
(iv) pattern sensitive faults.

STUCK-AT FAULTS
A stuck-at fault assumes a digital signal line (wire, gate input/output) is permanently fixed
to logic 0 (s-a-0) or logic 1 (s-a-1) due to a physical defect.
 Example: A wire intended to switch between 0 and 1 may always read 0 (s-a-0).
 It could happen because of open circuits, short circuits, or gate damage.

 It simplifies fault modeling while being realistic.

 It works well especially for two-level combinational logic.
 Kohavi’s Theorem: If you detect all single stuck-at faults in a 2-level circuit, you also catch
all multiple stuck-at faults (i.e., faults don't mask each other).
 For multi-level circuits, this isn't always true, but detection rates are still high.
To test a node:
 s-a-0: Force node to 1 and check if output is incorrect.
 s-a-1: Force node to 0 and check if output is incorrect.
  Key Idea: Propagate the internal fault effect to the primary output, where it can be
observed.

For a three-input NAND gate there are eight possible single stuck-at faults,

A 3-input NAND gate has:

 3 inputs → A, B, C
 1 output → Z = ¬(A·B·C)
It has 8 possible single stuck-at faults:
 A s-a-0, A s-a-1
 B s-a-0, B s-a-1
 C s-a-0, C s-a-1
 Z s-a-0, Z s-a-1
Key insights:
 Table 2.1 shows fault-free vs faulty outputs.
 Table 2.2 gives the minimum test set (4 vectors) to detect all 8 faults.
  Test vectors are designed such that fault effects change the output, hence
detectable.

 Here, G1 has a stuck-at-0 on its output.

 Test vector sets G1 output to 1, and the effect is propagated through G4 and other
gates to the primary output.
 If G1 is faulty (s-a-0), output will be 0.
 If no fault, output will be 1.
This propagation path is essential: without it, faults are invisible.

BRIDGING FAULTS: