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IJARSE, Vol. No.4, Special Issue (01), March 2015 ISSN-2319-8354(E)

DESIGN AND SIMULATION OF INTEGRATOR USING

THIN FILM TRANSISTOR BASED OPERATIONAL
AMPLIFIER
Prabhakaran.G1, Kannan.V2,
1
Research Scholar, Faculty of Electronics Engineering, Sathyabama University Chennai, (India)
2
Principal, Jeppiaar Institute of Technology, Chennai, (India)

ABSTRACT
An Operational Amplifier is a basic building block of many analog and mixed signal systems. It is a high gain
differential amplifier which can be used as summer, integrator, differentiator etc., and designed to operate at
low voltage 3V DC. To design an Op-Amp, various electrical characteristics such as gain, bandwidth, slew rate,
CMRR, output swing offset, etc., have to be taken in to account. Frequency compensation is necessary for closed
loop stability since the op-amps are designed to be operated on negative feedback. An Integrator is an essential
circuit component in many analog circuits that performs mathematical operation of Integration particularly in
solving differential equation and can be used as a storage element in analog computing circuits. It is used
where initial condition is of great importance and which affects the future calculations. The present research
work proposes the basic use of integrator circuits in engineering design and simulation using Thin Film
Transistor based Operational Amplifiers. This work also investigates the design of integrator circuit and the
applications of the integrator. The designed circuits are very suitable for integrated circuit and implementation.
The circuit performance is obtained through HSpice simulations and the results are compared with the existing
theoretical work showing good agreement.

Keywords: Hspice, Integrator, Low Voltage, Operational Amplifier, Thin Film Transistor,.

I INTRODUCTION
Thin Film Transistor is popularly known as TFT, which are presently demanding more attention amongst the
most common electronic devices. Since they introduced in the modern electronic industry and applications,
TFTs have undergone extensive evolution, development and refinement. TFTs are three terminal devices, which
belongs to IGFET family. TFT differs from a typical MOSFET in that it is composed of very thin layer
deposited on an insulating substrate, whereas most MOSFETs are formed from a semiconductor wafer. TFTs are
gaining more interest in large area electronics such as flexible displays, RFIDs, sensors, switching systems, solar
cells, RAMs, low cost computer logic, flat panel for image crystallization etc,. They draw more attention
towards the application of different types of TFTs, Mainly a-Si, and Poly-Si, increases need for an accurate and
efficient material to simulate the circuits used on these devices.
Recently amorphous silicon TFT (a-Si TFT) and Poly Si TFT have become essential devices in many

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applications especially in low cost ICs and large area integration. In this, a-Si TFT represent as mainstream
technology for active matrix liquid crystal displays. Their advantages compared to crystalline MOSFETs are
having low price and high capability of large area integration. These advantages compensates for low speed of
a-Si TFT which is its main disadvantage. Although, Poly Si TFT have many more of the same applications as a-
Si TFT its main advantages are both displays/switching and driver circuitry can be fabricated on the same chip
and preferred in applications necessary for high speed. As their intended uses began from switching systems to
low cost computer logic to flat panel display, addressing new materials, structures and fabrication techniques
were introduced. A-Si TFT is the most widely used active layer material while Poly Si is increasingly pursued as
a next generation TFT technology.
This paper is organized into the following sections. The detailed introductions about TFT is explained in Section
I. The Section II, introduces the structures and modelling aspects of thin film transistor. Section III, dealt with
the TFT Operational Amplifier circuit. Detailed design on TFT based Integrators and their analysis are
discussed in section IV. Finally in section V, the result has been discussed and concluded in section VI.

1.1 Thin Film Transistors

Both in microelectronics and in low cost integrated circuits, Poly Silicon Thin Film Transistors (Poly-Si TFT)
have become essential device due to its low temperature process. A leakage current (Ion, off current) present
inconsistently in the device, is the problem of Poly Si TFT and this current is depend strongly on the bias and
temperature which has been generated from grain boundary defects near the drain. It is very important to
research on leakage current of Poly Si TFT and its reduction, because abnormal leakage current is the main
deficiency of Poly Si TFT which is due to the field-assisted generation mechanism.

Fig. 1. Poly-Si Structure with Different Layers.

Fig.1 shows the structure of Poly Si TFT which is a kind of three terminal device; its substrate is floating just
like SOI MOSFET. The modelling of Poly Si TFT is the effective medium of approach which treats the non-
uniform poly silicon sample with grain boundaries as some uniform effective medium with effective material
properties. The increase of drain current in saturation caused by the floating body effect. This short channel
devices show a significant decrease of the sub-threshold idealistic factor with increasing drain voltage. By using
the model, the relations of leakage current between terminal voltages, temperature of the TFT can be obtained.

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Fig. 2. Bottom Gate Structure of an a-Si:H TFT.

Fig.2 shows the bottom gate structure of a-Si:H TFT, also a three terminal device. The operation of a-Si TFT is
quite different from that of crystalline MOSFETs. In the sub-threshold region the drain current is a poor
function of the gate voltage dictated by large trap density in the material as in crystalline MOSFETs. Above the
threshold, most of the induced charge in a-Si:H TFT are trapped and only a small fraction enters the
conduction band. This fraction increases as the gate voltage increases. The field effect mobility increases with
the gate voltage.

II OPERATIONAL AMPLIFIERS
2.1. Related Work
The CMOS OPAMP is widely used as analog building block for mixed signal circuits. Many OPAMP design is
[1]
simple and robust, providing good values for its functional parameters. Palmisano, et al , explained about
CMOS Op-Amp design procedure. This procedure has conditionally allowed using the compensation capacitor
for limited range. In this design, Cc is the compensation capacitor greater than a parasitic capacitor Cgs5 of TFT
in the Op-Amp. The design procedure that allows the Cc a wider range and it would provide a higher degree of
freedom in the trade-off between noise and power consumption which have been improved by Mahattanakul and
Chutichatuporn[2]. A design procedure of multistage Op-Amp for settling time minimisation with low power is
proposed by Pugliese, et al.[3]. When an Op-Amp is necessary to be operated at a high frequency, several
limitations have come into the forefront in the existing approaches. The Op-Amp designed to work at a low
voltage and low power has been improved by R. Kr. Baruah[4]. Although the simulation (Ehsan Kargaran, et
al.)[5] done in HSPICE shows an operation at a low voltage and it consumes very low power, but an increase is
observed in the UGF which is not noteworthy to be considered. The multi-stage designed proposed by Anshu
Gupta, et al. 2010[6], leads to the decrease of the phase margin and UGF, but it improves the gain and settling
time. It is very difficult that the transistors are in saturation condition when the supply voltage decreases (R.
Gonzalez, et al.)[7]. In this research work an Op-Amp has been designed which exhibits high UGF for optimized
balancing of gain, speed, power, phase margin, noise and load. Here, the proposed method is to set a higher
UGF of the Op-Amp working at a low voltage supply. This permits the value of each circuit element of the
amplifier i.e., transistor aspect ratios, bias current and compensation capacitor etc,. Frequency compensation is
essential for two-stage and multi-stage Op-Amps and it has been analysed as done by Zushu Yan, et.al [8].

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2.2. Ideal Operational Amplifier

An Op-Amp is the core component of surprisingly larger application in modern electronic era and undoubtedly
one of the most useful mixed signal circuitry. The Op-Amp is usually, a single-ended output with a differential
input of an electronic voltage amplifier of high gain. Its differential input is either NMOS input or PMOS input.
Many operational amplifier systems are incorporating MOSFET transistors in design. This is true in low power
and low voltage CMOS Op-Amp analog applications and act as functional core elements of mixed analog and
digital Nano VLSI circuits and systems.
The main challenges of Op-Amp are a high dc gain and a high bandwidth with a high output swing depending
on the applications. To achieve a higher gain, multi-stage Op-Amp can be used by cascading the stages [9]. If the
gain is increased the bandwidth will be considerably reduced, which is the drawback of the two stage Op-Amp.
However, it is difficult to compensate and hard to stabilize for the two- stage Op-Amp, which is widely used in
many applications [10].
Frequency compensation technique is necessary to avoid closed loop instability. The easiest method for
compensation is to connect a capacitor between input and output of the second stage [11]. This method gives high
closed loop stability with lower bandwidth and results in splitting the poles. The Cascade compensation
[12]
technique has been introduced to improve the stability in performance . This technique improves the settling
[13]
performance and the output swing is limited to certain range . Single Miller Feed Forward Compensation
[14]
technique is proposed and this technique improves stability and limits the bandwidth reduction . However,
[15]
this method suffers from compressed gain bandwidth problem because of very high gain of the first stage .
The circuit approach for the implementation of CMOS Op-Amp in the two stage configuration shown in Fig.3.

Fig. 3. Two Stage CMOS Op-amp.

It is designed to provide moderate gain and a relatively low UGF. The differential gain stage includes the input
of the Op-Amp and provides the overall gain to improve off-set and noise performance. The additive gain stage
improves its gain additionally and to allow maximum output swing. The final stage provides proper biasing and
act as a buffer to convert impedance to low output impedance of additive gain stage and improves the current
gain.

2.3. TFT Based Op-Amp

TFT have higher pinch-off voltage as compared with almost all the types of FETs. The TFT acts as a switching
device in most of the applications. The switching is closed in microseconds and opened it in milliseconds. Like
CMOS device characteristics, TFTs are having high immunity to noise, operates on low power voltage and low
static power consumption.

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Fig. 4. Two Stage Hybrid Op-Amp with n-channel Input Stage

As MOSFET, significant power is drawn only when TFT device is switching between on and off states and it is
not producing much heat as other forms of logic. These devices also allow a high density of logic functions on a
chip. TFTs operate on low power voltage and low static power consumption like MOSFET and CMOS, but they
are highly immunity to noise. When TFT device is switching between on and off states, it draws less power.
Also, they are not producing much heat as MOSFETs. These TFT devices also allow a high density of logic
functions on a chip.
[16-21]
In our previous work , we designed an Op-Amp using a-Si TFT and Poly-Si TFT. Also, we discussed
about the design constraints which leads to a well-designed Op-Amp and explained the reason for using two
types of TFT devices such as amorphous Si TFT and Poly-Si TFT. Our proposed design of a two stage TFT
based Op-Amp circuit is shown in Fig.4. Simulations are carried out on the design of both the TFTs as well as
CMOS based Op-Amps. In TFT based Op-Amp, TFTs are used as n-type MOSFET while p-type MOSFET are
used as complementary devices.

2.4. Detailed Designed Procedure

Fig.5.Design Procedure of an Op-Amp

The design procedure of proposed Op-amp is described in Fig.5, with required basic fundamental data shown in
Table.1 for procedural technique to design an Op-amp. The design procedure carried out for the Op-amp using
both TFTs and CMOS. The design specification used for calculation is shown in Table.1. The designed

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Op-Amps have been simulated using HSpice Circuit Simulator and the final design specifications have been
shown in Table.2. The performances of Op-Amps are shown in Table.3 obtained from the recorded values.

III INTEGRATOR USING TFT OP-AMP

Fig.6.Ideal Inverting Integrator Circuits using an Op-Amp

The Integrator is a circuit using OP-AMP which performs the mathematical operation of Integration. The
integrator acts like a storage element with respect to time, that produces an output voltage which is directly
proportional to the integral of voltage applied in the input. In other words, the magnitude of the signal output is
calculated by the duration of time an input voltage is present as the current flows through the capacitor which is
required for negative feedback. The circuit shown in Fig.6 is an ideal inverting integrator, since the input is
applied to the inverting input of the Op-Amp. Mixed Mode signal is used for the simulation of the integrator.
Since the circuit uses the inverting configuration, we conclude that the circuit transfer function is:
V out ( s ) Z 2(s) 1 / sC 1
G (s)           (1 )
V in ( s ) Z1(s) R sRC

In other words, the output signal is related to the input as:

 1 V in ( s )
V out ( s )                  (2)
RC s

It means that the output signal is proportional to the integral of the input signal. We can prove that the
circuit integrates the input by taking the inverse Laplace Transform:
t
1 V in ( t ' )
V out ( s ) 
RC
 s
dt '               ( 3 )
0

If the input is: V in ( t )  sin  t                    ( 4 )

t
1 1 1 1
Then the output becomes V out ( t )   sin  t dt '  cos  t  cos  t   ( 5 )
RC 0
RC   RC

The same result may be obtained using Fourier analysis also:

V out (  ) Z 2 ( ) 1 / j C j
G ( )           (6)
V in (  ) Z 1 ( ) R  RC

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Thus, the magnitude of the transfer function is:

j 1
G ( )                   (7 )
 RC  RC

And since: j  e j (  / 2 )  cos(  / 2 )  j sin(  / 2 )          ( 8 )

The phase of the transfer function is:
 G (  )   / 2 radians  90               ( 9 )

Also also the same result may be determined using time domain analysis. From the Fig.6, the voltage across the
t
1
capacitor is: V c ( t ) 
C
i 2
( t ' )dt '               (10 )
0

And from the circuit: V c ( t )  V ( t )  V out ( t )   V out ( t )               (11 )

t
1
Therefore, the output voltage is: V out ( t ) 
C
i 2
( t ' )dt '               (12 )
0

There by it is proved that by using any one of the method we can determine the same result. The practical
Integrator is shown in Fig.7. When Vin = 0, the integrator gives open loop gain because capacitor acts as a
open circuit for DC voltage, which means that the input offset voltage of the Op-Amp which produces
voltage at the output is an error. Therefore to acquire output voltage without error, a resistor is connected
in parallel with the feedback capacitor. The various applications of Op-Amp Integrator are available in the
industry. In this paper, we described the Ramp Generator and analyzed its performance.

Fig.7.Practical Inverting Integrator Circuits using an Op-Amp

3.1. Ramp Generator
The integrator integrates the current I across capacitor C1 when the same current I is flowing through
resistor R1. The voltage across C1 is called as output voltage Vout. One of the great application of the
integrator is that the ramp voltage is generated by it. This can be generated by placing a fixed voltage at VS
that develops a constant current through R1. The capacitor then integrates this current and generates a ramp
voltage. The circuit essentially integrates the input current I s  V s / R 1 across capacitor C1. The output

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T
1 VS
voltage is realized as capacitor voltage after a time interval T, described by: V out 
C1
 R1
dt . When a
0

constant input voltage is applied at VS, the output ramp voltage increases steadily. The output voltage
1 VS
(ramp) at any time T can be predicted by the simplified equation: V out  x xT
C1 R1

The response of generating ramps can be increased or decreased than the original circuit by changing the
value of VS, R1 or C1. From the principles of integration, it describes that voltage across the capacitor is
equal to ratio of the charge on the capacitor to its capacitance, ie., Q/C. Then the voltage across the
capacitor is output Vout therefore: -Vout = Q/C. The rate of change of voltage across the capacitor due to
charging and discharging of the capacitor, is given as:
Q dV out dQ 1 dQ
VC  , V C  V X  V out  0  V out ,    x             (13 )
C dt Cdt C dt

Where dQ/dt is an electric current. Since inverting input terminal of integrating Op-Amp is zero, X = 0, the
input current Iin is flowing through the input resistor Rin is given by the equation:
V in  0 V in
I in                  ( 14 )
R in R in

The current flowing through the capacitor C is given by the equation:

dV out dQ dQ dV out
I in  C  Cx   C     (15 )
dt Cdt dt dt

Assuming that input impedance of the Op-Amp is infinite as an ideal Op-Amp, no current flows into the
Op-Amp terminal. Therefore, the nodal equation at the inverting input terminal is given by the equation:
V in dV out V in dt
I in  I f
  C ,  1
R in dt dV out R in C

From which we derive an ideal voltage output for the Op-Amp used in the Integrator as:
t
1
V out 
R in C
V in
( t )dt               (16 )
0

This equation can also be re-written as:

1
V out  xV in                 (17 ) Where j = 2 ƒ
j  RC

and the output voltage Vout is a constant 1/RC times the integral of the input voltage Vin with respect to
time. The minus sign (-) indicates a 180°phase shift, because the input signal is connected directly to the
inverting input terminal of the op-amp. In this paper, we investigate the performances of ramp generator by
using TFT based Op-Amp and the circuit is simulated in HSpice Circuit Simulator and the output is shown
in Fig.7a, Fig.7b and Fig.7c.

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IV RESULTS AND DISCUSSIONS

Table-1: Design Parameters
DESIGN AND SPICE PARAMETERS
Poly Si
Parameter a-Si TFT CMOS
TFT
VDD +3V +3V +3V
VSS -3V -3V -3V
Ao ≥1000 ≥1000 ≥15000
GB= 2π(X) 1.5MHz 20KHz 5MHz
SR (V/µS) 5 2.2 10V/µS
PM >80° >85° >60°
Ro ≤3.5K ≤1.5K ≤1.46K
λ 0.04 0.04 0.02
Veff 2.25V 1.8V 2.25V
Kn(µA/V2) 2.62 1.35 40
Kp (µA/V2) 48.74 48.74 15
-2.5 ≤ , -2.65 ≤ , -2.5 ≤,
CMR
≤ 1.2 ≤ 0.65 ≤ 1.75
CC 1pF 1pF 1pF

The design and Spice parameters used for calculation of various parameters of the proposed design of Op-Amp
using Poly Si TFT, a-Si TFT and CMOS is shown in Table 1. After the calculation, values are obtained to be
used in simulation which is shown in Table-2, for all the three Op-Amps. From the Table-2, we observed that the
size of the Poly Si TFT Op-Amp is 0.57% smaller than CMOS Op-Amp. Also the current consumed in the
CMOS Op-Amp is 3.37µA more than Poly Si TFT Op-Amp. Using HSpice circuit simulator, the result has been
summarized in the Table -3 for comparison of both the Operational Amplifiers. From the Table-3, the Gain AVO
of CMOS Op-Amp is more than 10 times of Poly Si TFT Op-Amp and Slew rate and Unity gain bandwidth are
almost 3 times better than Poly Si TFT Op-Amp. But the Phase Margin is almost near to 90° in Poly Si TFT Op-
Amp and considerably less in CMOS Op-Amp. Output Resistance is double in Poly Si TFT Op-Amp than
CMOS Op-Amp. CMRR of Poly Si TFT Op-Amp is considerably less than CMOS Op-Amp. These Op-Amps
are used in the proposed Integrator design and specifications are shown in Table-4. The performances of all the
three integrators in the form of graph after simulation are shown in Fig.7a, Fig.7b, and Fig.7c. The output of a-Si
TFT is slightly degraded from the output of Poly Si TFT and CMOS based Integrators.

Table -2: TFT Based Op-Amp Design Specification

(L=6.6µm and Leff=5.6µm are used)

Poly Si TFT Op-Amp a-Si TFT Op-Amp CMOS Op-Amp

PAR I W I W I W
W/L W/L W/L
(µA) (µm) (µA) (µm) (µA) (µm)
M1 3.315 6.33 35.5 0.962 18.85 105.9 5 6.53 36.6
M2 3.315 6.33 35.5 0.962 18.85 105.9 5 6.53 36.6
M3 3.315 0.625 3.5 0.962 1.11 6.2 5 0.96 5.4
M4 3.315 0.625 3.5 0.962 1.11 6.2 5 0.96 5.4

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M5 6.63 5.36 30.0 1.924 37.5 210.0 10 5.36 30

M6 30 6.32 35.4 12.03 14.5 81.2 30 5.79 32.4
M7 30 14.8 83.0 12.03 21.2 118.8 30 16.07 90
M8 100 156 873.6 75.33 2742.7 15359.1 100 156 873.6
M9 100 53.57 300 75.33 166.6 933.0 100 53.33 300
M10 100 53.57 300 100 166.6 933.0 100 53.33 300

TABLE- 3: Op-Amp Performance

Simulation Results
Parameters
Poly Si TFT a-Si TFT CMOS
Gain 1.2496K 15.1003K 16.7618K

UGB 1.35 MHz 120.17 KHz 5.45 MHz

CMRR 253.638 1.3317K 34.182K
Slew Rate (V/µS) 6.92 3.94 7.93
Dc Offset Voltage (µV) 740.7155 -688.75 197.62

Power Dissipation (m.Watts) 1.4354 1.1357 1.4690

Output Resistance (KΩ) 3.7118 10.1345 1.3919
Phase Margin 80° 83.16° 54°
Open loop Gain Margin (dB) 84.5 83.6 84.5
TABLE- 4: Integrator Specification
Integrator Using
Parameters
Poly Si TFT a-Si TFT CMOS
VDD (V) 3 3 3
VSS (V) -3 -3 -3
Resistance R1 (Ω) 50K 450K 50K
Resistance R2 (Ω) 1MEG 1MEG 1MEG
Capacitor Cf (µF) 0.017 0.001 0.010
Resistance RL (Ω) 50K 50K 50K
DC Voltage Gain (dB) 20 2.22 20

Fig.8a. Input and Output of Poly Si TFT Op-Amp.

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Fig.8b. Input and Output of a-Si TFT Op-Amp.

Fig.8c. Input and Output of CMOS Op-Amp.

V CONCLUSION
Poly Si TFT based Op-Amp is performing well as compared to CMOS Op-Amp. Though Gain, Slew rate, and
frequency of operation of CMOS Op-Amp is better performing than Poly Si TFT Op-Amp, but Poly Si TFT Op-
Amp have better stability and robustness to failure, because of high phase margin and double the output
resistance. The TFT and CMOS Op-Amp, used for the Integrators design are generating the Ramp signal
output which agrees with the existing theoretical and practical work. But the a-Si TFT based Integrators slightly
degraded than Poly Si TFT and CMOS based Integrators which are suitably agreed with the theoretical and
existing research works [22]. When vin = 0, the integrator gives open loop gain because capacitor acts as an open
circuit for DC voltage. Input offset voltage of the Op-Amp which produces an error voltage at the output. To
obtain error free output voltage resistor R2is connected in parallel with the feedback capacitor. The error is
almost reduced in all the three Integrators output. But the CMOS Integrators are produced excellent output with
least error output voltage compared to TFT based Integrators. DC output gain of Poly Si TFT and CMOS based
Integrators are 10 times more than a-Si TFT based Integrators. This paper concludes that the characteristics of
Op-Amp limits the performance of the Integrators as the characteristics of the transistors used in the Op-Amp
decides its performance. All the three Op-Amps are suitable for any applications as seen from the results.

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REFERENCES
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[2] Mahattanakul, J. and Chutichatuporn, J., (2005). Design Procedure for Two- Stage CMOS OPAMP with
Flexible Noise-Power Balancing Scheme. IEEE Transaction on Circuits and Systems-I: Regular Paper vol.
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[3] Pugliese, A , Cappuccino, G. and Cocorullo, G., (2008). Design Procedure for Settling Time Minimization
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[13] Vaibhav,K. and C.Degang (2009). Design Procedure and Performance Potential for Operational Amplifier
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Technology (IJEAT), Volume-1, Issue-3, pp 12-19, February 2012, ISSN: 2249 – 8958.

First A. Prof. G Prabhakaran Research Scholar from Sathyabama University. He received his
Bachelor s degree from Institution of Engineers (India), Kolkatta, Master degree in VLSI Design

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under Electronics and communication engineering from Sathyabama University of Chennai, Tamil Nadu. His
research interests, on Design and Analysis of Op-amp using Thin Film Transistor. He is an Member of
Institution of Engineers (India), Kolkatta and Graduate Member in Aeronautical Society of India. He served in
Indian Air Force as AIR WARRIOR for 18 years with the specialization on Avionics. Presently working in
Jeppiaar Engineering College, Chennai, India.

Second A. Prof. Dr. V.Kannan was born at Ariyalur on 11th of April 1970. He received his
Bachelors of Electronics and Communication Engineering from Madurai Kamaraj University,
Madurai, Master Degree from Birla Institute of Technology and Science, Pilani and Ph.D degree
from Sathyabama University, Chennai. He is currently functioning as Principal of Jeppiaar
institute of Technology, Sriperumpudur, Chennai. He has more than 190 publications - in
international/national journals, proceedings, reports etc., to his credit. He produced 5 Ph.D’s in the field of
Electronics and also guided more than 100 students for the M.Tech. and M.E degrees in the field of Electronics.
He became a life member of ISTE in 1994. His research interest pertains to High Speed Devices, Opto
electronic Devices,VLSI Design, Digital Signal Processing, Digital Image Processing and Nano Electronic
Devices.

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