®

HIP4086 3-Phase Bridge Driver Configurations

and Applications
Application Note February 2003 AN9642.3

Introduction Starting with the HIP4086, the use of negative logic for the
high-side input control allows both high and low side MOSFETs
This application note describes the HIP4086 Three Phase
of a phase leg to be controlled without added external logic.
MOSFET bridge driver, popular configurations in which the
HIP4086 can be used, and the HIP4086 evaluation board. Undervoltage Shutdown
Intersil Application Notes and Data Sheets are available on Undervoltage shutdown prevents the power MOSFETs from
the Intersil worldwide web, home page: www.intersil.com. being turned on if the bias supply voltage is below the level
set by the UVLO pin. There are several ways to program the
Description UVLO pin. Leaving the UVLO pin open results in an
The HIP4086 is a Three Phase Bridge N-Channel MOSFET undervoltage trip setting of approximately 6.6V. Tying the
driver IC. The HIP4086 is especially targeted at PWM motor UVLO pin to VDD sets the trip level to approximately 6.2V.
control applications. The HIP4086 simplifies these designs Hysteresis in this configuration is disabled.
without losing flexibility. The HIP4086 has a flexible input For higher trip settings, tie a resistor between VSS and
protocol for driving every possible switch combination. The UVLO. A 50kΩ resistor, for example, will provide a trip
user can even override the shoot-through protection, a voltage of approximately 8.5. See Figure 16 of the HIP4086
feature needed when driving switched-reluctance motors. [1] data sheet, for details.
Compared to earlier parts in the HIP408X family such as the
HIP4081A, the HIP4086’s reduced output drive current of Input Logic Flexibility
0.5A and its wide range of programmable dead-time (0.25ms You can drive the input control logic of the HIP4086 by TTL
to 4.5ms) makes it ideal for motor control applications in the or CMOS logic. The threshold voltages for input control of
DC to 100kHz range. It even sports programmable the HIP4086 is a guaranteed “one” at or above 2.7V and a
undervoltage set point. guaranteed “zero” at or below 0.8V.

The HIP4086 inputs source approximately 100µA through an

HIP4086 Features internal pull-up when the inputs are held low. With 5V or more
Feature Summary at the logic inputs, the input current drops to less than 1µA.
The HIP4086 includes an enhanced superset of features Disable (DIS) Function
common to earlier members of the HIP408X family adding
A logical “one” applied to the DIS pin turns off all MOSFETs
flexibility to meet the needs of both motor control and power
and overrides all inputs. To enable the HIP4086 the 100µA
supply applications.
internal pull-up must be pulled down externally. After a short
The HIP4086 refresh startup pulse duration and the delay the gate control inputs are again re-enabled. During
undervoltage shutdown threshold levels are now adjustable. the delay, the lower MOSFETs are turned on to refresh the
Both upper and lower MOSFET switches can now be turned upper bootstrap capacitors. See text to follow, Description of
on simultaneously (useful in double forward converter Operation, Input Timing.
applications). As with other 408X family parts, a suitable
‘dead-time’ can be programmed using an external resistor.

TRUTH TABLE

INPUT OUTPUT
ALI, BLI, CLI AHI, BHI, CHI UV DIS RDEL ALO, BLO, CLO AHO, BHO, CHO

X X X 1 X 0 0

X X 1 X X 0 0

1 X 0 0 >100mV 1 0

0 0 0 0 X 0 1

0 1 0 0 X 0 0

1 0 0 0 <100mV 1 1

NOTE: X signifies that input can be either a “1” or “0”.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 Application Note 9642

Functional Block Diagram (1/3 of HIP4086)

CHARGE
PUMP
16 AHB
DRIVER
AHI 5 TURN-ON LEVEL
17 AHO
DELAY SHIFTER
DIS 10
10ns UV 18 AHS
VDD 20 DELAY
UNDERVOLTAGE
8 DETECTOR UV DEAD TIME
UVLO
DISABLE

9
RFSH 20 VDD
RFSH
PULSE DRIVER
TURN-ON 21 ALO
DELAY
ALI 4 6 VSS
DEAD TIME
RDEL 7 CURRENT
MIRRORS DEAD TIME
DISABLE
2µs
-
+ DELAY

100mV +
-
VSS

Typical Application (PWM Mode Switching)

+12V 80V

+12V

1 BHB BHO 24
2 BHI BHS 23
RDEL 3 BLI BLO 22

PWM 4 ALI ALO 21

INPUTS 5 AHI VDD 20
6 VSS CLO 19
7 RDEL AHS 18
GND
8 UVLO AHO 17
9 RFSH AHB 16
RUV 10 DIS CHS 15
(OPTIONAL)
11 CLI CHO 14
CRFSH 12 CHI CHB 13
(OPTIONAL)
FROM
OPTIONAL
OVERCURRENT 3-PHASE
LATCH RDIS
LOAD

2
 Application Note 9642

Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
17 AHB High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect cathode
1 BHB of bootstrap diode and positive side of bootstrap capacitor to each xHB pin.
13 CHB
(xHB)
5 AHI High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin 17), BHO
2 BHI (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the dead time is
12 CHI disabled by connecting RDEL (Pin 7) to ground, the low side input of each phase will override the corresponding high
(xHI) side input on that phase - see Truth Table on previous page. If RDEL is tied to ground, dead time is disabled and the
outputs follow the inputs. Care must be taken to avoid shoot-through in this application. DIS (Pin 10) also overrides the
high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than VDD).
4 ALI Low-Side Logic Level Inputs. Logic at these three pins controls the three low side output drivers ALO (Pin 21), BLO
3 BLI (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and xHO drivers,
11 CLI with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs
(xLI) low. xLI can be driven by signal levels of 0V to 15V (no greater than VDD).
6 VSS Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
7 RDEL Dead Time Setting. Connect a resistor from this pin to VDD to set timing current that defines the dead time between
drivers - see Figure 17 of HIP4086 [1]. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees
no shoot-through by delaying the turn-on of all drivers. When RDEL is tied to VSS, both upper and lowers can be
commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1µF or smaller
may be connected between RDEL and VSS.
8 UVLO Undervoltage Setting. A resistor can be connected between this pin and VSS to program the undervoltage set point,
see Figure 18 of HIP4086 [1]. With this pin not connected, the undervoltage disable is typically 6.6V. When this pin is
tied to VDD , the undervoltage disable is typically 6.2V.
9 RFSH Refresh Pulse Setting. An external capacitor can be connected from this pin to VSS to increase the length of the start
up refresh pulse - see Figure 14 of HIP4086 [1]. If this pin is not connected, the refresh pulse is typically 1.5µs.
10 DIS Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs. With
DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V (no greater than
VDD).
17 AHO High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.
24 BHO
14 CHO
(xHO)
15 AHS High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins. The negative
23 BHS side of the bootstrap capacitors should also be connected to these pins.
15 CHS
(xHS)
20 VDD Positive Supply. Decouple this pin to VSS (Pin 6).
21 ALO Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.
22 BLO
19 CLO
(xLO)
NOTE: x = A, B and C.

Charge-Pumps When both upper and lower switches are turned off the
The charge pumps are designed to maintain floating supply charge pumps continue to operate, but the off level-shift
bias voltage when the upper MOSFETs are turned on and current (typically 800µA) overcomes that of the charge pump
the lower MOSFETs are turned off. The upper charge pump (typically 125µA) and the bootstrap capacitor will discharge.
is turned off whenever the lower MOSFET in that phase is In order to refresh the bootstrap capacitor for subsequent
turned on. When a lower MOSFET is turned on, the upper turn-on, that phase’s lower must first be turned on. As
bootstrap capacitor for that phase is refreshed through its long as the lower MOSFETs are continually being
VDD supply and bootstrap diode eliminating the need for pulse-width-modulated at a reasonably high frequency, the
charge-pumping during these periods. The total chip bias bootstrap capacitors in each phase will remain charged up.
current, ICC, is reduced by 1.0mA for each phase’s charge When both upper and lower MOSFETs are commanded on
pump which is turned off. simultaneously (switched-reluctance motor drive or other
double-forward converter applications) the charge pump

3
 Application Note 9642

deactivates because the lower MOSFET is turned on. Since 6

the upper MOSFET is also on, the bootstrap capacitor will
eventually discharge. To maintain bootstrap supply in this RDEL = 100kΩ
situation, the upper/lower pairs must be constantly PWM-ed.
Refreshing of the bootstrap supply will occur automatically

DEAD TIME (µs)

4
during the period when both upper and lower MOSFETs are
off. This happens because the load current will continue to
flow during the ‘off’ part of the PWM cycle forcing the
converter’s flyback diodes to conduct. The conducting flyback 2
diodes will cause the XHS terminals to be pulled a diode drop
below VSS, which will refresh the bootstrap capacitors.
RDEL = 10kΩ
Good practice always dictates the use of a bootstrap diode
and capacitor for maintaining upper bias voltage. Do not 0
-60 -40 -20 0 20 40 60 80 100 120 140 160
assume that the charge pump can always maintain the JUNCTION TEMPERATURE (oC)
required bias. When connecting one of the upper drivers as
a low-side driver, do not use the bootstrap diode and FIGURE 1. DEAD TIME vs RDEL RESISTANCE
capacitor. Rather connect that phase’s XHB terminal to VCC
and the XHS terminal to VSS. 80
TJ = 25oC
An excellent treatise on bootstrap circuit design and charge
pump operation can be found in Application Notes 60

REFRESH TIME (µs)

AN9404 [2] or AN9405 [3], see Applications Considerations.

Shoot-Through Avoidance
40
Shoot-through or cross conduction is eliminated by
Connecting a resistor from the RDEL pin to VDD ranging
from 2kΩ to 100kΩ provides for a dead-time range of
20
approximately 0.1µs to 4.5µs. Dead-time varies directly with
RDEL resistance above 0.1µs as shown in Figure 1.

In double-forward and/or switched-reluctance driver 0

0 50 100 150 200 250 300 350 400 450 500
applications where simultaneous conduction in both upper CRFSH (pF)
and lower MOSFETs the phase legs are desired or where
dead-time will be externally controlled, tie the RDEL pin to FIGURE 2. REFRESH CAPACITANCE vs REFRESH TIME
VSS. This disables the dead-time delay circuitry and allows
direct control of both upper and lower MOSFETs without
regard to prior conduction states.

Very small propagation delays associated with both upper

and lower MOSFETs, typically 50ns, remain even with RDEL
tied to VSS.

Programmable Refresh
The startup refresh pulse duration is controlled by the size of
the refresh capacitor tied to the RFSH pin as shown in
Figure 2. The startup refresh pulse initializes the charge on
the bootstrap capacitors of the 3 high side drivers when
power is first applied to the HIP4086. The charge pump can
supply only enough charge to maintain the gate voltage
applied to an upper MOSFET in the on-state position.

The duration of the startup refresh pulse will be at least 1µs

with no external capacitor connected between the RFSH and
the VSS pins. The startup refresh pulse duration can be
extended beyond 1µs by connecting a small capacitor
between pin 9 (RFSH) and pin 6 (VSS). For example, a
100pF capacitor extends the refresh time to about 16µs.
which is more than long enough for most applications.

4
 Application Note 9642

LOWER LOWER
TURN-OFF TURN-ON

XLI

XHI

XLO

XHO

DEAD TIME DEAD TIME

XLO (RDEL = VSS)

XHO (RDEL = VSS)

UPPER UPPER
TURN-ON TURN-OFF
FIGURE 3. TIMING DIAGRAMS

DISABLE TO LOWER DISABLE TURN-OFF

TURN-ON PROP DELAY PROP DELAY (UPPERS)

REFRESH
PULSE WIDTH
DIS OR UV

XHI, XLI

XLO

XHO

DISABLE TO UPPER
NOTES: ENABLE

1. X means any “A”, “B”, or “C” phase.

2. With RDEL resistor tied to VDD, lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless RDEL
< 100mV.
FIGURE 4. DISABLE FUNCTION

Description of Operation conduction mode) either the upper or lower inputs must be
inverted with respect to each other.
Input Timing
The Dead-Time as shown in Figure 3 actually represents the
The Timing Diagrams of Figures 3 and 4 show the switching
turn-on delay time associated with turning on that device in
relationships between the inputs and their respective outputs
response to that device’s input command. Simultaneously a
in standard bridge mode (RDEL tied to VDD through a
turn-off command is issued to the opposite device in the
programming resistor) and in simultaneous-conduction
same phase leg, but the actual turn-off is only delayed by the
mode (RDEL tied to VSS). Note that RDEL should never be
natural IC propagation delay. In other words there is no
left open.
added delay involved in turning off the switches, other than
Since the HIP4086 upper input logic is inverted, the upper their natural transport delays (approximately 45ns to 75ns)
devices will be OFF if the upper inputs are pulled high. For plus the time it takes the driver to pull enough charge out of
full bridge operation the upper input control pins should be the power MOSFET gate to turn it off.
connected to the lower control input pins thus minimizing
The Dead-Time, or more appropriately, the turn-on delay
additional external logic. For double-forward and
time is tailored to specific application by adjusting the value
switched-reluctance operating modes (simultaneous

5
 Application Note 9642

of the RDEL resistor as discussed previously in the section, “Phase C”. The three-phase bridge configuration is used for
Shoot-through Avoidance and characterized by Figure 1. controlling PM brushless DC (BDC) motors.

Figure 4 indicates how the Undervoltage sensor, U/V, and A high-side driver paired with a low-side driver is referred to
the DIS, disable, pin affect the states of the gate driver as a half-bridge, three of which are used in the three-phase
outputs. Two conditions must be satisfied to allow a lower bridge configuration. The half-bridge is the basic building
refresh pulse to be initiated. First, the VDD voltage must be block for driving most brush and brushless motor drives.
above the U/V trip level and second, the DIS pin must be Normally the MOSFETs body diodes are used to recirculate
pulled low (chip enable). The refresh function was discussed inductive load current in configurations comprised of one or
previously in the section, Programmable Refresh and is more half-bridges.
characterized in Figure 2. Long refresh times may be
Note that the 3 “floating” drivers incorporated in the
necessary when MOSFETs with very large gate turn-on
HIP4086, can control up to 6 independent low side MOSFET
charge requirements are used or when several large
switches for driving various loads, (i.e., relays and single
MOSFETs are paralleled to drive heavy loads that a single
quadrant brush motors).
MOSFET can not drive.
VBUS
Level-Shift Operation
The level-shift function for the HIP4086 operates exactly like
the HIP4082 level-shifter described more fully in Application
AHO BHO CHO
Note AN9611 [4]. TO 3-PHASE
LOAD
GATES AND PHASE A
The continuous on/off level-shift technique uses no latches UPPER SOURCE
RETURNS CONNECT PHASE B
in the floating logic section of the IC and avoids the TO HIP4086 PHASE C
possibility that an on/off latch could inadvertently change
states. The only down-side of the continuous on/off ALO BLO CLO

level-shift technique is that higher level-shift power

dissipation can occur under certain modes of operation, for
example, when the upper MOSFETs are off throughout most of
the duty cycle. See application note AN9611 [4] for more detail. FIGURE 5. THREE PHASE BRIDGE CONFIGURATION

Power Dissipation The HIP4086 can provide up to 3 separate high side switch
See Power Dissipation [2, 3] and Thermal Design under drivers for driving grounded loads or it can drive all high-side
Power Dissipation the Easy Way [2, 3] for a very good connected loads as shown in Figure 6. Appropriate
discussion on determining IC power dissipation based upon freewheeling diodes must be added as shown. The 3
the switching frequency, IC supply voltage and switching remaining non-floating, ground-referenced gate drivers must
frequency. be used as low side drivers. The low-side driver outputs are
distinguished by their ALO, BLO and CLO pin designations.
HIP4086 Applications Configurations Another basic building block, repeated 3 times in Figure 7 is
Application Configurations referred to as a double-forward converter. In the
The HIP4086 can drive up to 6 independent power double-forward converter the load is connected between the
MOSFETs. Three of the HIP4086’s gate drivers must be upper and lower MOSFETs. This configuration is a basic
used to drive low-side, N-Channel MOSFETs. That is, building block for many two-switch forward converter (power
MOSFETs which have their sources tied to the most supplies), switched reluctance motors, and automotive fuel
negative power bus rail or very close to it through a low injectors. In this configuration, one MOSFET can be used to
valued resistive shunt. commutate the current in the windings while the other can be
pulse-with-modulated to regulate current. Note in Figure 7
The three remaining drivers’ negative references float, since that diodes must be added for recirculating current. When
they are intended for driving high side, N-Channel MOSFETs are used as high side switches, a current of 1mA
MOSFETs. However, they can also be configured to drive flows into the load from each of the pins, AHS, BHS and
low side MOSFETs by externally tying the drivers’ negative CHS when the upper MOSFET(s) is off.
references, AHS, BHS and CHS to the HIP4086’s VSS
potential.

The 3-phase bridge configuration, one of the most common

motor drive configurations, employs 3 low side and 3 high
side drivers as shown in Figure 5. The load is connected
between the points marked “Phase A”, “Phase B” and

6
 Application Note 9642

VBUS GATES AND VBUS

UPPER SOURCE
RETURNS CONNECT
TO HIP4086
LOAD 1

LOAD 2

LOAD 3

LOAD 4

LOAD 5

LOAD 6
AHO BHO CHO

LOAD 1

LOAD 2

LOAD 3
ONLY PRIMARIES
AHO BHO CHO ALO BLO CLO OF THE 3-PHASE
TRANSFORMERS
ARE SHOWN

ALO BLO CLO

UPPER DRIVERS LOW-SIDE DRIVERS
(CONNECTED AS CAN ONLY BE
LOW-SIDE DRIVERS) CONNECTED LOW-SIDE PHASE A PHASE B PHASE C

FIGURE 6. 6-LOWER CONFIGURATION FIGURE 7. DOUBLE-FORWARD CONVERTER BRIDGE

CONFIGURATION

It is possible to share the current regulation MOSFET that is VBUS

pulse-width-modulated for multiple loads as shown in
Figure 8. This minimizes the number of MOSFETs required
CHO
to drive the loads. To allow both upper and lower MOSFETs
to be turned on simultaneously, the RDEL pin of the
HIP4086 is tied to VSS . This disables the ‘on-delay’ feature

LOAD 1

LOAD 2

LOAD 3

LOAD 4

LOAD 5
also known as “dead-time”.

Of course, there are many other possibilities. For example,

the three-phase bridge configuration can drive three
independent DC brush motors in two-quadrant mode, which AHO BHO ALO BLO BLO

means that each motor can have one polarity of voltage

impressed across it, but with current flowing either into or out
of the motor. In two quadrant mode, motors may be
controlled in one direction with both accelerating or braking 2 UPPER DRIVERS THREE DEDICATED
CONVERTED TO LOWER DRIVERS
torque control. LOWER DRIVERS

Another possibility is to drive one DC brush motor in FIGURE 8. MULTIPLE LOADS WITH UPPER MODULATED
SWITCH FOR CONTROL
4-quadrant mode (this requires a full H-bridge) and a second
in 2-quadrant mode as discussed above. In 4-quadrant V > VBUS1
mode the motor’s torque and rotational direction can be
controlled in both directions. The 4-quadrant motor would be
connected between any two of the phase terminals as AHO BHO CHO
shown in Figure 9 and a 2-quadrant motor would be
VBUS1
connected between the remaining phase terminal and either + A -
the bus or the power ground. B
A C DC MOTOR
Since the phases are truly independent, a synchronous boost
ALO BLO CLO
regulator could be made using one of the three MOSFET
bridge legs with the resulting DC output used to supply the bus
for the other two MOSFET bridge legs, either making these two
independently controlled half-bridges or an H-bridge as shown
in Figure 9. In the figure a boost regulator was chosen with the FIGURE 9. SYNCHRONOUS BOOST WITH HIGHER VOLTAGE
upper MOSFET of phase A being used as the diode. Phases B FOR DRIVING LOAD
and C function as an H-Bridge to control the load voltage.
In summary, the HIP4086 drives six independent N-Channel
MOSFETs. Three of these drivers must drive low side
MOSFETs, but the other three floating drivers can be used to
drive high or low side MOSFETs. The outputs can be
configured in many ways to drive a variety of motors, relays,
injectors, speakers and two-switch forward converter (power

7
 Application Note 9642

supplies). The HIP4086 allows the designer great flexibility. Setting Up the HIP4086 Evaluation Printed Circuit
The details of this flexibility pertains not only to configuration Board
versatility, but also to the HIP4086’s many features which will Since the HIP4086 can drive floating as well as
be discussed next. ground-referenced N-Channel MOSFETs, the power circuit
configurations shown in Figures 5 through 9 can be driven by
HIP4086 Evaluation PC Board the HIP4086. Please refer to the full schematic located in the
The HIP4086 Evaluation PC Board provides a fast and appendix to this application note. The HIP4086 EVAL-
efficient way for users to evaluate performance of the BOARD can be configured to implement the configurations
HIP4086 without having to design and build their own board. shown in Figures 5 through 9, with the exception that, in
In fact, the evaluation printed circuit board was used to Figure 8, only four low-side MOSFETs can be implemented.
characterize the propagation and dead-time parameters
Connect power to the HIP4086 EVAL-BOARD, +12VDC to BJ1
included in the HIP4086 Data Sheet.
with ground of this supply to BJ11 (the common ground for logic
The evaluation PC board has been designed to enable users and power). The Power Bus (up to +80 VDC Max) is tied to BJ2
to quickly try different power circuit configurations, such as with its ground tied to BJ11. The Power and Control power can
3-phase full wave bridge. The switched reluctance and be driven from the same 12V supply if desired.
double-forward converter configurations can also be
If desired, the internal current sensor can be used to latch
configured with the HIP4086 Evaluation PC Board. For the
upon sensing an overcurrent in the shunt resistor, SH3. This
latter, fast recovery power rectifiers have been included for
is a 3W, 0.1Ω, 1% resistor mounted on the heat sink which
allowing freewheeling currents to flow in the inductive load.
also cools the power MOSFETs. To use the internal
Evaluation Printed Circuit Board Features overcurrent latch, pins 1 and 2 of JP1 must be jumpered.
The evaluation printed circuit board provides the following Two other shunts, identical to SH3, are located in the source
features and conveniences: paths of two upper MOSFETs, Q1 and Q2. The Kelvin sense
leads of these have been brought to JP2 pins 1 and 2 and
• 6 RFP22N10 Power MOSFETs, 2 RURG3010 power pins 3 and 4, respectively. These shunts may be sensed by a
rectifiers and 5 RURP1510 power rectifiers to provide
users external sense amplifiers or comparators as desired. If
circuitry for changing quickly between different circuit
they will be used in lieu of SH3 or if overcurrent latchout is
configurations. 11 banana jacks for fast connection of
external circuits and power supplies and for changing not desired, the jumper connecting JP1 pins 1 and 2 should
configurations. be removed, allowing the DIS pin on the HIP4086 to be held
low by resistor, R11.
• 3 Kelvin shunts, 0.1Ω, 3W for current sensing. Two are
located in the upper MOSFET source to phase Potentiometer, P1, may be used to adjust the duty cycle of
connections (1 in each of two phases) and the third is the pulse width modulator, PWM. This is a simple PWM
located between the common source connections of the modulator made by comparing a triangle wave (from the
lower MOSFETs and power ground. ICM7555 timer) with a DC level from the wiper of P1. Three
• A four terminal header to access the upper shunt signals individual DC levels may be compared to the triangle wave if
and a 28 pin header to provide access to the HIP4086 the jumpers between pins 3 to 4, 5 to 6 and 7 to 8 of JP1 are
gate control inputs and to customize signals coming from removed and appropriate user-supplied signals are applied
the on-board PWM distribution network. to pins 3, 5 and 7 to control the modulation index of phases
B, C and A respectively.
• On-board PWM distribution network with potentiometer to
change duty cycle. An access test-point is available to Tables 1, 2, and 3 have been prepared to simplify the task of
dynamically control duty-cycle if desired from an external connecting all of the jumpers for the different configurations
source. possible with the HIP4086 EVAL-BOARD. The Table 1 deals
• 24 test points to monitor waveforms at representative with the setting of the JP1 jumpers to implement several of
points on the HIP4086 and bridge inverter. the configurations possible with the EVAL-BOARD. Probably
the most popular configuration is the three phase bridge
• All necessary bootstrap components, bypass capacitors,
gate resistors and source return resistors are included. configuration. For this reason the HIP4086 was designed to
Provision for tailoring refresh start-up pulse width, allow bringing in only one control signal for each of the A, B
undervoltage set-point and dead-time are included. and C half-bridges. This is accomplished by jumpering the
XLI input to the same XHI input. In this configuration, when
• Color-coded banana jacks for connecting Bias supply and
an upper is to be on, a lower is to be off and face-savers. The
Bus supply voltages.
upper input control signals are designed to cause each
upper switch to be on when its corresponding input signal is
low (a logical inversion). The JP1 jumpers provide for either
bringing the same control signal to the XLI and XHI inputs or
for inverting one of them. The former provides the proper

8
 Application Note 9642

input polarities for conventional three phase bridges, runs within the power circuit, good ground plane techniques,
whereas the latter provides the proper input polarities for and proper bias supply and high voltage bus bypassing
implementing double-forward converter configurations. techniques are important. The section, Layout Problems and
Effects, in AN9405 [3] is a good resource as the comments
The Table 2 deals with PWM stimulus and overcurrent
therein apply generally to all IC MOSFET gate drivers.
shutdown provisions. When a user wants to supply external
control signals for the driver, the HIP4086 provides a means
References
for bringing in separate external PWM stimuli. This is
accomplished through JP1 jumpers across terminals 3-4, For Intersil documents available on the internet, see web site
5-6 and 7-8. The single low-side connected shunt, SH3, www.intersil.com/
triggers the U5B comparator with latching hysteresis added. [1] HIP4086 Data Sheet, Intersil Corporation, Doc. No.
The output of the comparator will drive the HIP4086 DIS pin 4220
if JP1 pin 1 is jumpered to JP1 pin 2. This jumper can be
[2] Danz, George E., “HIP4080A, 80V High Frequency
pulled when the user wishes to employ external current
H-Bridge Driver”, AN9404, Intersil Corp., Melbourne,
sense through use of the current-sensing shunts. FL, March, 1995. Doc. No. 9404
Table 3 shows how to connect the loads for the different [3] Danz, George E., “HIP4081A, 80V High Frequency
configurations shown in Table 3. Please refer to the H-Bridge Driver”, AN9405, Intersil Corp., Melbourne,
schematic, Figure 10. FL, March, 1995. Doc. No. 9405
[4] Danz, George E., “A DC-AC Isolated Battery Inverter
Printed Circuit Board Layout
Using the HIP4082”, AN9611, Intersil Corp., Melbourne,
Eventually you will want to produce your own printed circuit FL, May, 1996. Doc. No. 9611
board layout. As with any high frequency circuit, short wire

TABLE 1.

LOW SIDE HIGH SIDE

ON BOARD PWM
CONFIGURATION STIMULUS A B C A B C

3-Phase Bridge (Figure 5) Yes 25-26 19-20 13-14 23-24 17-18 11-12

3-Upper, 3-Lower (Figure 5) Yes 25-26 19-20 13-14 23-24 17-18 11-12

3-Double Forward Converter (Figure 7) Yes 25-26 19-20 13-14 21-22 15-16 9-10

Multiple Load Drive (Figure 8) Yes 25-26 19-20 13-14 21-22 15-16 9-10

All Configurations No EXT-26 EXT-20 EXT-14 EXT-24 EXT-18 EXT-12

NOTES:
3. JP1 is shown in Figure 12 schematic.
4. “EXT” refers to external logic level stimulus supplied by user.
5. The “3-Upper/3-Lower” configuration can also be jumpered like the 3-double-forward converter configuration.
6. When both upper and lower MOSFETs are to be simultaneously on, tie the RDEL pin to VSS.

TABLE 2.

JP1 CONNECTIONS

LOW-SIDE HIGH-SIDE
LOW AND HIGH LOW AND HIGH LOW AND HIGH CURRENT SENSE CURRENT SENSE
FUNCTION A B C (SH3) (SH1, SH2)

On Board PWM Stimulus 7-8 3-4 5-6

On Board Overcurrent Shutdown 1-2

Off Board Overcurrent Shutdown Note 8 Note 9

NOTES:
7. Use Potentiometer, P1, to control PWM pulse width.
8. Off board current sense amplifier input connected to pin 3 and 2 of SH1. Remove jumper, JP1, pins 1-2.
9. Off board current sense amplifier input connected to pins 1 and 2 of JP2 (SH1) or JP2 pins 3 and 4 (SH2). Off board control circuit controls upper
FET PWM for current control in multiple drive or double forward configurations.

9
 Application Note 9642

TABLE 3.

LOAD CONNECTION

CONFIGURATION LOAD 1 LOAD 2 LOAD 3 LOAD 4 LOAD 5 LOAD 6

3-Upper, 3-Lower BJ4 - BJ11 BJ4 - BJ11 BJ6 - BJ11 BJ7 - BJ2 BJ8 - BJ2 BJ9 - BJ2

3-Phase Bridge (Note 10) BJ4 to BJ5 BJ5 to BJ6 BJ6 to BJ4 NA NA NA

3-Double Forward Converter BJ4 - BJ7 BJ8 - BJ5 BJ9 - BJ6 NA NA NA

Multiple Load Drive (Note 11) BJ7 - BJ4 BJ8 - BJ4 BJ9 - BJ4 BJ3 - BJ4 NA NA

NOTES:
10. Before connecting loads, jumper BJ4 to BJ7, BJ5 to BJ8 and BJ6 to BJ9 and BJ2 to BJ3.
11. Maximum of 4 low-side FETs can be driven with this EVAL BD. In addition to connecting loads as shown above, jumper BJ6 to BJ10. Q2 is not
used and Q3 becomes a low-side switch.

Appendix
BJ2
VBUS
TP10 TP11
Q2 TP12 C9
Q1 VBUS + C10
AHG BHG 0.22µF 470mfd
D7 10% 100VDC
100VDC -10%, +50%
BJ3
SH1 CHD
0.1Ω
3W. SH2 TP13 TP14
1% 0.1Ω BJ4
3W. 1% AHS
AHS
TP15
BJ5
JP2 BHS
BHS
1 TP16
2
3 Q3 TP17
4 CHG BJ6
CHS
HEADER 4 CHS

D8 D9 D10 D11 D12 D13

TP18
RURG3010
100VDC BJ7
RURG3010 ALD

TP19
TP20 BJ8
Q4 BLD
ALG TP22
TP21 BJ9
Q5
CLD
BLG TP23
Q6
CLG TP24
BJ10
SH+

SH3 SHP
BJ11 0.1Ω NOTES:
3W. 1% SHN 12. Q1 through Q6 are RFP22N10.
GND
13. D7, D9, D11, D12, D13 are RURP1510.
14. D13 is optional for “fly by wire” controls and is used
in lieu of D11.

FIGURE 10.

10
 Application Note 9642

Appendix (Continued)

+12V VDD

R24
R19 562K R20
SHP
100K 10K
U5B
5 7 R21
R22 +
- OC
SHN CA3260 10K
6
100K C11 R23
C12
0.1µF 10K
0.47µF

FIGURE 11.

11
 Appendix (Continued)

VDD

TP5
R14

8 U2
3.61K
VDD
2 VCC 3
TR OUT 8 1
7 U3A U4A
5 3
CTL DIS 1 3 2
-
12

6 2 +
4 THR
R GND CA3260 4049
8 1
U4B JP1
ICM7555 4
1 5 4
27 28
25 26 ALI
4049 23 24 AHI
8 21 22
C8 19 20 BLI
TP6 17 18 BHI
0.01µF
1 1 U4D 15 16
TP7 U3B

Application Note 9642

5 U4C 13 14 CLI
7 7 6 9 10 11 12 CHI
- 9 10
6 +
7 8 VDD
CA3260 4049 4049 5 6
8 8 3 4
1 2
VDD VDD R15
HEADER 14X2 21.5K
8 1 U4E 1
TP8 U5A U4F
3
- 1 11 12 14 15 OC DIS
2 + 1
CA3260 4049 4049 CCW P1
8 8 2
4 20K

CW
TP9
3

R17
21.5K

NOTES:
15. Insert 20K resistor in JP1 pin 13 to 14 for UVLO setting.
16. Insert 100pF capacitor in JP1 pin 17 to 18 for refresh adjustment.
17. Jumper JP1, pin 19 to 20 to activate O/C shutdown.
FIGURE 12.
 Application Note 9642

Appendix (Continued)

VDD

C1
D1 0.22µF
C2 UF4002 10%
1.5µF 100VDC U1 50VDC
1 24 R1 10Ω
BHB BHO BHG

2 23 R2 1Ω
BHI BHINOT BHS BHS
D2
UF4002
3 22 100VDC R3 10Ω
BLI BLI BLO BLG

4 21 R4 10Ω
ALI ALI ALO BJ1 VDD ALG
TP1

AHI
5
AHINOT VDD
20 +C3
R5 C4 4.7µF
20K 1.0µF 16VDC R6 10Ω
1/8W 6 19 10% CLG
VSS CLO 50V
1%

7 18 R7 1Ω
RDEL AHS AHS
R8 C5 D3
UF4002
8 17 0.22µF 100VDC R9 10Ω
R10 49.9K UVLO AHO AHG
TP2 VDD
1/8W C6 D4
1% 9 16
RFSH AHB TP3 TP4
470pF UF4002
R11 100VDC R12 1Ω
10 15 CHS
DIS CHS
5.62K C7
DIS 0.22µF R13 10Ω
11 14 CHG
CLI CLI CHO

12 13 D5
CHI CHINOT CHB UF4002
D6 100VDC
HIP4086
UF4002
100VDC
VDD

FIGURE 13.

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