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1: /**
2: ******************************************************************************
3: * @file stm8s.h
4: * @author MCD Application Team
5: * @version V2.3.0
6: * @date 16-June-2017
7: * @brief This file contains all HW registers definitions and memory mapping.
8: ******************************************************************************
9: * @attention
10: *
11: * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
12: *
13: * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14: * You may not use this file except in compliance with the License.
15: * You may obtain a copy of the License at:
16: *
17: * http://www.st.com/software_license_agreement_liberty_v2
18: *
19: * Unless required by applicable law or agreed to in writing, software
20: * distributed under the License is distributed on an "AS IS" BASIS,
21: * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22: * See the License for the specific language governing permissions and
23: * limitations under the License.
24: *
25: ******************************************************************************
26: */
27:
28: /* Define to prevent recursive inclusion -------------------------------------*/
29: #ifndef __STM8S_H
30: #define __STM8S_H
31:
32: /** @addtogroup STM8S_StdPeriph_Driver
33: * @{
34: */
35:
36: /* Uncomment the line below according to the target STM8S or STM8A device used in
your
37: application. */
38:
39: /* #define STM8S208 */ /*!< STM8S High density devices with CAN */
40: /* #define STM8S207 */ /*!< STM8S High density devices without CAN */
41: /* #define STM8S007 */ /*!< STM8S Value Line High density devices */
42: /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */
43: /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */
44: /* #define STM8S105 */ /*!< STM8S Medium density devices */
45: /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */
46: /* #define STM8AF626x */ /*!< STM8A Medium density devices */
47: /* #define STM8AF622x */ /*!< STM8A Low density devices */
48: /* #define STM8S103 */ /*!< STM8S Low density devices */
49: #define STM8S003 // */ /*!< STM8S Value Line Low density devices */
50: /* #define STM8S903 */ /*!< STM8S Low density devices */
51: /* #define STM8S001 */ /*!< STM8S Value Line Low denisty devices */
52:
53: /* Tip: To avoid modifying this file each time you need to switch between these
54: devices, you can define the device in your toolchain compiler preprocessor.
55:
56: - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
57: STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory
58: density ranges between 32 to 128 Kbytes
59: - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,

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60: STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory

61: density ranges between 8 to 32 Kbytes
62: - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx
microcontrollers
63: where the Flash memory density ranges between 32 to 128 Kbytes.
64: - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers
65: where the Flash memory density ranges between 16 to 32-Kbytes.
66: - Low-Density STM8A devices are the STM8AF622x microcontrollers where the Flash
67: density is 8 Kbytes.
68: - Low-Density STM8S devices are the STM8S103xx, STM8S003, STM8S903xx and STM8S001
microcontrollers
69: where the Flash density is 8 Kbytes. */
70:
71: #if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \
72: !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \
73: !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \
74: !defined (STM8S003)&& !defined (STM8S005) && !defined(STM8S001) && !defined
(STM8AF622x)
75: #error "Please select first the target STM8S/A device used in your application (in
stm8s.h file)"
76: #endif
77:
78: /******************************************************************************/
79: /* Library configuration section */
80: /******************************************************************************/
81: /* Check the used compiler */
82: #if defined(__CSMC__)
83: #define _COSMIC_
84: #elif defined(__RCST7__)
85: #define _RAISONANCE_
86: #elif defined(__ICCSTM8__)
87: #define _IAR_
88: #else
89: #error "Unsupported Compiler!" /* Compiler defines not found */
90: #endif
91:
92: #if !defined USE_STDPERIPH_DRIVER
93: /* Comment the line below if you will not use the peripherals drivers.
94: In this case, these drivers will not be included and the application code will b
95: based on direct access to peripherals registers */
96: #define USE_STDPERIPH_DRIVER
97: #endif
98:
99: /**
100: * @brief In the following line adjust the value of External High Speed
oscillator (HSE)
101: used in your application
102:
103: Tip: To avoid modifying this file each time you need to use different HSE, you
104: can define the HSE value in your toolchain compiler preprocessor.
105: */
106: #if !defined HSE_Value
107: #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined
(STM8AF52Ax) || \
108: defined (STM8AF62Ax) || defined (STM8AF622x)
109: #define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz*
110: #else
111: #define HSE_VALUE ((uint32_t)16000000) /* Value of the External oscillator in Hz*
112: #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax ||
STM8AF622x */

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113: #endif /* HSE_Value */

114:
115: /**
116: * @brief Definition of Device on-chip RC oscillator frequencies
117: */
118: #define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */
119: #define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */
120:
121: #ifdef _COSMIC_
122: #define FAR @far
123: #define NEAR @near
124: #define TINY @tiny
125: #define EEPROM @eeprom
126: #define CONST const
127: #elif defined (_RAISONANCE_) /* __RCST7__ */
128: #define FAR far
129: #define NEAR data
130: #define TINY page0
131: #define EEPROM eeprom
132: #define CONST code
133: #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined
(STM8AF52Ax) || \
134: defined (STM8AF62Ax)
135: /*!< Used with memory Models for code higher than 64K */
136: #define MEMCPY fmemcpy
137: #else /* STM8S903, STM8S103, STM8S001, STM8S003, STM8S105, STM8AF626x, STM8AF622x
*/
138: /*!< Used with memory Models for code less than 64K */
139: #define MEMCPY memcpy
140: #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */
141: #else /*_IAR_*/
142: #define FAR __far
143: #define NEAR __near
144: #define TINY __tiny
145: #define EEPROM __eeprom
146: #define CONST const
147: #endif /* __CSMC__ */
148:
149: /* For FLASH routines, select whether pointer will be declared as near (2 bytes,
150: to handle code smaller than 64KB) or far (3 bytes, to handle code larger
151: than 64K) */
152:
153: #if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined
(STM8S003) || \
154: defined (STM8S001) || defined (STM8S903) || defined (STM8AF626x) || defined
(STM8AF622x)
155: /*!< Used with memory Models for code smaller than 64K */
156: #define PointerAttr NEAR
157: #define MemoryAddressCast uint16_t
158: #else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */
159: /*!< Used with memory Models for code higher than 64K */
160: #define PointerAttr FAR
161: #define MemoryAddressCast uint32_t
162: #endif /* STM8S105 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF626x or
STM8AF622x */
163:
164: /* Uncomment the line below to enable the FLASH functions execution from RAM */
165: #if !defined (RAM_EXECUTION)
166: /* #define RAM_EXECUTION (1) */
167: #endif /* RAM_EXECUTION */

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168:
169: #ifdef RAM_EXECUTION
170: #ifdef _COSMIC_
171: #define IN_RAM(a) a
172: #elif defined (_RAISONANCE_) /* __RCST7__ */
173: #define IN_RAM(a) a inram
174: #else /*_IAR_*/
175: #define IN_RAM(a) __ramfunc a
176: #endif /* _COSMIC_ */
177: #else
178: #define IN_RAM(a) a
179: #endif /* RAM_EXECUTION */
180:
181: /*!< [31:16] STM8S Standard Peripheral Library main version V2.3.0*/
182: #define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version
*/
183: #define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x03) /*!< [23:16] sub1 version
*/
184: #define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version
*/
185: #define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release
candidate */
186: #define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\
187: |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\
188: |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\
189: |(__STM8S_STDPERIPH_VERSION_RC))
190:
191: /******************************************************************************/
192:
193: /* Includes ------------------------------------------------------------------*/
194:
195: /* Exported types and constants ----------------------------------------------*/
196:
197: /** @addtogroup Exported_types
198: * @{
199: */
200:
201: /**
202: * IO definitions
203: *
204: * define access restrictions to peripheral registers
205: */
206: #define __I volatile const /*!< defines 'read only' permissions */
207: #define __O volatile /*!< defines 'write only' permissions */
208: #define __IO volatile /*!< defines 'read / write' permissions */
209:
210: /*!< Signed integer types */
211: typedef signed char int8_t;
212: typedef signed short int16_t;
213: typedef signed long int32_t;
214:
215: /*!< Unsigned integer types */
216: typedef unsigned char uint8_t;
217: typedef unsigned short uint16_t;
218: typedef unsigned long uint32_t;
219:
220: /*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */
221:
222: typedef int32_t s32;
223: typedef int16_t s16;

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224: typedef int8_t s8;

225:
226: typedef uint32_t u32;
227: typedef uint16_t u16;
228: typedef uint8_t u8;
229:
230:
231: typedef enum {FALSE = 0, TRUE = !FALSE} bool;
232:
233: typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
234:
235: typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
236: #define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
237:
238: typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
239:
240: #define U8_MAX (255)
241: #define S8_MAX (127)
242: #define S8_MIN (-128)
243: #define U16_MAX (65535u)
244: #define S16_MAX (32767)
245: #define S16_MIN (-32768)
246: #define U32_MAX (4294967295uL)
247: #define S32_MAX (2147483647)
248: #define S32_MIN (-2147483648uL)
249:
250: /**
251: * @}
252: */
253:
254: /** @addtogroup MAP_FILE_Exported_Types_and_Constants
255: * @{
256: */
257:
258: /******************************************************************************/
259: /* IP registers structures */
260: /******************************************************************************/
261:
262: /**
263: * @brief General Purpose I/Os (GPIO)
264: */
265: typedef struct GPIO_struct
266: {
267: __IO uint8_t ODR; /*!< Output Data Register */
268: __IO uint8_t IDR; /*!< Input Data Register */
269: __IO uint8_t DDR; /*!< Data Direction Register */
270: __IO uint8_t CR1; /*!< Configuration Register 1 */
271: __IO uint8_t CR2; /*!< Configuration Register 2 */
272: }
273: GPIO_TypeDef;
274:
275: /**
276: * @}
277: */
278:
279: /** @addtogroup GPIO_Registers_Reset_Value
280: * @{
281: */
282:
283: #define GPIO_ODR_RESET_VALUE ((uint8_t)0x00)

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284: #define GPIO_DDR_RESET_VALUE ((uint8_t)0x00)

285: #define GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
286: #define GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
287:
288: /**
289: * @}
290: */
291:
292: /*----------------------------------------------------------------------------*/
293: #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) ||
defined(STM8S003) || \
294: defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) ||
defined(STM8AF622x)
295: /**
296: * @brief Analog to Digital Converter (ADC1)
297: */
298: typedef struct ADC1_struct
299: {
300: __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */
301: __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */
302: __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */
303: __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */
304: __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */
305: __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */
306: __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */
307: __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */
308: __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */
309: __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */
310: __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */
311: __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */
312: __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */
313: __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */
314: __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */
315: __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */
316: __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */
317: __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */
318: __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */
319: __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */
320: uint8_t RESERVED[12]; /*!< Reserved byte */
321: __IO uint8_t CSR; /*!< ADC1 control status register */
322: __IO uint8_t CR1; /*!< ADC1 configuration register 1 */
323: __IO uint8_t CR2; /*!< ADC1 configuration register 2 */
324: __IO uint8_t CR3; /*!< ADC1 configuration register 3 */
325: __IO uint8_t DRH; /*!< ADC1 Data high */
326: __IO uint8_t DRL; /*!< ADC1 Data low */
327: __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */
328: __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */
329: __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/
330: __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/
331: __IO uint8_t LTRH; /*!< ADC1 low threshold register high */
332: __IO uint8_t LTRL; /*!< ADC1 low threshold register low */
333: __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */
334: __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */
335: __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */
336: __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */
337: }
338: ADC1_TypeDef;
339:
340: /** @addtogroup ADC1_Registers_Reset_Value
341: * @{

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342: */
343: #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00)
344: #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00)
345: #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00)
346: #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00)
347: #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00)
348: #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00)
349: #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03)
350: #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF)
351: #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00)
352: #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00)
353: #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00)
354: #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00)
355: /**
356: * @}
357: */
358:
359: /** @addtogroup ADC1_Registers_Bits_Definition
360: * @{
361: */
362: #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */
363: #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */
364: #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
365: #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable
mask */
366: #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */
367:
368: #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */
369: #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */
370: #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */
371:
372: #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
373: #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */
374: #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */
375: #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */
376:
377: #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */
378: #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */
379:
380: #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S001) ||
(STM8S903) || (STM8AF626x) || (STM8AF622x) */
381: /**
382: * @}
383: */
384:
385: /*----------------------------------------------------------------------------*/
386: /**
387: * @brief Analog to Digital Converter (ADC2)
388: */
389: #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined
(STM8AF52Ax) || defined (STM8AF62Ax)
390: typedef struct ADC2_struct
391: {
392: __IO uint8_t CSR; /*!< ADC2 control status register */
393: __IO uint8_t CR1; /*!< ADC2 configuration register 1 */
394: __IO uint8_t CR2; /*!< ADC2 configuration register 2 */
395: uint8_t RESERVED; /*!< Reserved byte */
396: __IO uint8_t DRH; /*!< ADC2 Data high */
397: __IO uint8_t DRL; /*!< ADC2 Data low */
398: __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */

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399: __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */
400: }
401: ADC2_TypeDef;
402:
403: /** @addtogroup ADC2_Registers_Reset_Value
404: * @{
405: */
406: #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00)
407: #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00)
408: #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00)
409: #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00)
410: #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00)
411: /**
412: * @}
413: */
414:
415: /** @addtogroup ADC2_Registers_Bits_Definition
416: * @{
417: */
418: #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */
419: #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */
420: #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */
421:
422: #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */
423: #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */
424: #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */
425:
426: #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */
427: #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */
428: #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */
429:
430: #endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) ||
(STM8AF52Ax) */
431: /**
432: * @}
433: */
434:
435: /*----------------------------------------------------------------------------*/
436:
437: /**
438: * @brief Auto Wake Up (AWU) peripheral registers.
439: */
440: typedef struct AWU_struct
441: {
442: __IO uint8_t CSR; /*!< AWU Control status register */
443: __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */
444: __IO uint8_t TBR; /*!< AWU Time base selection register */
445: }
446: AWU_TypeDef;
447:
448: /** @addtogroup AWU_Registers_Reset_Value
449: * @{
450: */
451: #define AWU_CSR_RESET_VALUE ((uint8_t)0x00)
452: #define AWU_APR_RESET_VALUE ((uint8_t)0x3F)
453: #define AWU_TBR_RESET_VALUE ((uint8_t)0x00)
454:
455: /**
456: * @}
457: */

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458:
459: /** @addtogroup AWU_Registers_Bits_Definition
460: * @{
461: */
462:
463: #define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */
464: #define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */
465: #define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */
466:
467: #define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */
468:
469: #define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */
470:
471: /**
472: * @}
473: */
474:
475: /*----------------------------------------------------------------------------*/
476: /**
477: * @brief Beeper (BEEP) peripheral registers.
478: */
479:
480: typedef struct BEEP_struct
481: {
482: __IO uint8_t CSR; /*!< BEEP Control status register */
483: }
484: BEEP_TypeDef;
485:
486: /** @addtogroup BEEP_Registers_Reset_Value
487: * @{
488: */
489: #define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F)
490: /**
491: * @}
492: */
493:
494: /** @addtogroup BEEP_Registers_Bits_Definition
495: * @{
496: */
497: #define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */
498: #define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */
499: #define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
500: /**
501: * @}
502: */
503:
504: /*----------------------------------------------------------------------------*/
505: /**
506: * @brief Clock Controller (CLK)
507: */
508: typedef struct CLK_struct
509: {
510: __IO uint8_t ICKR; /*!< Internal Clocks Control Register */
511: __IO uint8_t ECKR; /*!< External Clocks Control Register */
512: uint8_t RESERVED; /*!< Reserved byte */
513: __IO uint8_t CMSR; /*!< Clock Master Status Register */
514: __IO uint8_t SWR; /*!< Clock Master Switch Register */
515: __IO uint8_t SWCR; /*!< Switch Control Register */
516: __IO uint8_t CKDIVR; /*!< Clock Divider Register */
517: __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */

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518: __IO uint8_t CSSR; /*!< Clock Security System Register */

519: __IO uint8_t CCOR; /*!< Configurable Clock Output Register */
520: __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */
521: uint8_t RESERVED1; /*!< Reserved byte */
522: __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */
523: __IO uint8_t SWIMCCR; /*!< SWIM clock control register */
524: }
525: CLK_TypeDef;
526:
527: /** @addtogroup CLK_Registers_Reset_Value
528: * @{
529: */
530:
531: #define CLK_ICKR_RESET_VALUE ((uint8_t)0x01)
532: #define CLK_ECKR_RESET_VALUE ((uint8_t)0x00)
533: #define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1)
534: #define CLK_SWR_RESET_VALUE ((uint8_t)0xE1)
535: #define CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
536: #define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18)
537: #define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF)
538: #define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF)
539: #define CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
540: #define CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
541: #define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
542: #define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00)
543:
544: /**
545: * @}
546: */
547:
548: /** @addtogroup CLK_Registers_Bits_Definition
549: * @{
550: */
551: #define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active
Halt/Halt modes */
552: #define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator
ready */
553: #define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator
enable */
554: #define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active
Halt/Halt mode */
555: #define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator
ready */
556: #define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator
enable */
557:
558: #define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal
oscillator ready */
559: #define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal
oscillator enable */
560:
561: #define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */
562:
563: #define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */
564:
565: #define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */
566: #define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */
567: #define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */
568: #define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/
569:

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570: #define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock

prescaler */
571: #define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */
572:
573: #define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */
574: #define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */
575: #define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */
576: #define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */
577: #define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */
578: #define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */
579: #define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */
580: #define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */
581: #define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */
582: #define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */
583: #define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */
584:
585: #define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */
586: #define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */
587: #define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */
588:
589: #define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection *
590: #define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection
interrupt enable */
591: #define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to
master clock */
592: #define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */
593:
594: #define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */
595: #define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready *
596: #define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output
selection */
597: #define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable
*/
598:
599: #define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator
trimmer */
600:
601: #define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */
602:
603: /**
604: * @}
605: */
606:
607: /*----------------------------------------------------------------------------*/
608: /**
609: * @brief 16-bit timer with complementary PWM outputs (TIM1)
610: */
611:
612: typedef struct TIM1_struct
613: {
614: __IO uint8_t CR1; /*!< control register 1 */
615: __IO uint8_t CR2; /*!< control register 2 */
616: __IO uint8_t SMCR; /*!< Synchro mode control register */
617: __IO uint8_t ETR; /*!< external trigger register */
618: __IO uint8_t IER; /*!< interrupt enable register*/
619: __IO uint8_t SR1; /*!< status register 1 */
620: __IO uint8_t SR2; /*!< status register 2 */
621: __IO uint8_t EGR; /*!< event generation register */
622: __IO uint8_t CCMR1; /*!< CC mode register 1 */
623: __IO uint8_t CCMR2; /*!< CC mode register 2 */

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624: __IO uint8_t CCMR3; /*!< CC mode register 3 */

625: __IO uint8_t CCMR4; /*!< CC mode register 4 */
626: __IO uint8_t CCER1; /*!< CC enable register 1 */
627: __IO uint8_t CCER2; /*!< CC enable register 2 */
628: __IO uint8_t CNTRH; /*!< counter high */
629: __IO uint8_t CNTRL; /*!< counter low */
630: __IO uint8_t PSCRH; /*!< prescaler high */
631: __IO uint8_t PSCRL; /*!< prescaler low */
632: __IO uint8_t ARRH; /*!< auto-reload register high */
633: __IO uint8_t ARRL; /*!< auto-reload register low */
634: __IO uint8_t RCR; /*!< Repetition Counter register */
635: __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
636: __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
637: __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
638: __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
639: __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
640: __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
641: __IO uint8_t CCR4H; /*!< capture/compare register 3 high */
642: __IO uint8_t CCR4L; /*!< capture/compare register 3 low */
643: __IO uint8_t BKR; /*!< Break Register */
644: __IO uint8_t DTR; /*!< dead-time register */
645: __IO uint8_t OISR; /*!< Output idle register */
646: }
647: TIM1_TypeDef;
648:
649: /** @addtogroup TIM1_Registers_Reset_Value
650: * @{
651: */
652:
653: #define TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
654: #define TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
655: #define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
656: #define TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
657: #define TIM1_IER_RESET_VALUE ((uint8_t)0x00)
658: #define TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
659: #define TIM1_SR2_RESET_VALUE ((uint8_t)0x00)
660: #define TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
661: #define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
662: #define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
663: #define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
664: #define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
665: #define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
666: #define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
667: #define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
668: #define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
669: #define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
670: #define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
671: #define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
672: #define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
673: #define TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
674: #define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
675: #define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
676: #define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
677: #define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
678: #define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
679: #define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
680: #define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
681: #define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
682: #define TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
683: #define TIM1_DTR_RESET_VALUE ((uint8_t)0x00)

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684: #define TIM1_OISR_RESET_VALUE ((uint8_t)0x00)

685:
686: /**
687: * @}
688: */
689:
690: /** @addtogroup TIM1_Registers_Bits_Definition
691: * @{
692: */
693: /* CR1*/
694: #define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
695: #define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. *
696: #define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */
697: #define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
698: #define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
699: #define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
700: #define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
701: /* CR2*/
702: #define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */
703: #define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */
704: #define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update
Selection mask. */
705: #define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control
mask. */
706: /* SMCR*/
707: #define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */
708: #define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */
709: #define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */
710: /*ETR*/
711: #define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */
712: #define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */
713: #define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */
714: #define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */
715: /*IER*/
716: #define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */
717: #define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */
718: #define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/
719: #define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable
mask. */
720: #define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable
mask. */
721: #define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable
mask. */
722: #define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable
mask. */
723: #define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
724: /*SR1*/
725: #define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */
726: #define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */
727: #define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */
728: #define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag
mask. */
729: #define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag
mask. */
730: #define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag
mask. */
731: #define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag
mask. */
732: #define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
733: /*SR2*/

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734: #define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag

mask. */
735: #define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag
mask. */
736: #define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag
mask. */
737: #define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag
mask. */
738: /*EGR*/
739: #define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */
740: #define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
741: #define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update
Generation mask. */
742: #define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */
743: #define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
744: #define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
745: #define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
746: #define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
747: /*CCMR*/
748: #define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
749: #define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
750: #define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
751: #define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask.
*/
752: #define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */
753: #define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
754:
755: #define CCMR_TIxDirect_Set ((uint8_t)0x01)
756: /*CCER1*/
757: #define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary
output Polarity mask. */
758: #define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary
output enable mask. */
759: #define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity
mask. */
760: #define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask.
*/
761: #define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary
output Polarity mask. */
762: #define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary
output enable mask. */
763: #define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity
mask. */
764: #define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask.
*/
765: /*CCER2*/
766: #define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity
mask. */
767: #define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask.
*/
768: #define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary
output Polarity mask. */
769: #define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary
output enable mask. */
770: #define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity
mask. */
771: #define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask.
*/
772: /*CNTRH*/
773: #define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */

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774: /*CNTRL*/
775: #define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
776: /*PSCH*/
777: #define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
778: /*PSCL*/
779: #define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */
780: /*ARR*/
781: #define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
782: #define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
783: /*RCR*/
784: #define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */
785: /*CCR1*/
786: #define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. *
787: #define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. *
788: /*CCR2*/
789: #define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. *
790: #define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. *
791: /*CCR3*/
792: #define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. *
793: #define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. *
794: /*CCR4*/
795: #define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. *
796: #define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. *
797: /*BKR*/
798: #define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */
799: #define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */
800: #define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */
801: #define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */
802: #define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode
mask. */
803: #define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode
mask. */
804: #define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */
805: /*DTR*/
806: #define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */
807: /*OISR*/
808: #define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output)
mask. */
809: #define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output)
mask. */
810: #define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output)
mask. */
811: #define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output)
mask. */
812: #define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output)
mask. */
813: #define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output)
mask. */
814: #define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output)
mask. */
815: /**
816: * @}
817: */
818:
819: /*----------------------------------------------------------------------------*/
820: /**
821: * @brief 16-bit timer (TIM2)
822: */
823:
824: typedef struct TIM2_struct

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825: {
826: __IO uint8_t CR1; /*!< control register 1 */
827: #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001)
828: uint8_t RESERVED1; /*!< Reserved register */
829: uint8_t RESERVED2; /*!< Reserved register */
830: #endif
831: __IO uint8_t IER; /*!< interrupt enable register */
832: __IO uint8_t SR1; /*!< status register 1 */
833: __IO uint8_t SR2; /*!< status register 2 */
834: __IO uint8_t EGR; /*!< event generation register */
835: __IO uint8_t CCMR1; /*!< CC mode register 1 */
836: __IO uint8_t CCMR2; /*!< CC mode register 2 */
837: __IO uint8_t CCMR3; /*!< CC mode register 3 */
838: __IO uint8_t CCER1; /*!< CC enable register 1 */
839: __IO uint8_t CCER2; /*!< CC enable register 2 */
840: __IO uint8_t CNTRH; /*!< counter high */
841: __IO uint8_t CNTRL; /*!< counter low */
842: __IO uint8_t PSCR; /*!< prescaler register */
843: __IO uint8_t ARRH; /*!< auto-reload register high */
844: __IO uint8_t ARRL; /*!< auto-reload register low */
845: __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
846: __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
847: __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
848: __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
849: __IO uint8_t CCR3H; /*!< capture/compare register 3 high */
850: __IO uint8_t CCR3L; /*!< capture/compare register 3 low */
851: }
852: TIM2_TypeDef;
853:
854: /** @addtogroup TIM2_Registers_Reset_Value
855: * @{
856: */
857:
858: #define TIM2_CR1_RESET_VALUE ((uint8_t)0x00)
859: #define TIM2_IER_RESET_VALUE ((uint8_t)0x00)
860: #define TIM2_SR1_RESET_VALUE ((uint8_t)0x00)
861: #define TIM2_SR2_RESET_VALUE ((uint8_t)0x00)
862: #define TIM2_EGR_RESET_VALUE ((uint8_t)0x00)
863: #define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00)
864: #define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00)
865: #define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00)
866: #define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00)
867: #define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00)
868: #define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00)
869: #define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00)
870: #define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00)
871: #define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF)
872: #define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF)
873: #define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00)
874: #define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00)
875: #define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00)
876: #define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00)
877: #define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00)
878: #define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00)
879:
880: /**
881: * @}
882: */
883:
884: /** @addtogroup TIM2_Registers_Bits_Definition

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885: * @{
886: */
887: /*CR1*/
888: #define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
889: #define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
890: #define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
891: #define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
892: #define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
893: /*IER*/
894: #define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable
mask. */
895: #define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable
mask. */
896: #define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable
mask. */
897: #define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
898: /*SR1*/
899: #define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag
mask. */
900: #define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag
mask. */
901: #define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag
mask. */
902: #define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
903: /*SR2*/
904: #define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag
mask. */
905: #define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag
mask. */
906: #define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag
mask. */
907: /*EGR*/
908: #define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */
909: #define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
910: #define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
911: #define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
912: /*CCMR*/
913: #define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
914: #define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
915: #define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
916: #define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask.
*/
917: #define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
918: /*CCER1*/
919: #define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity
mask. */
920: #define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask.
*/
921: #define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity
mask. */
922: #define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask.
*/
923: /*CCER2*/
924: #define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity
mask. */
925: #define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask.
*/
926: /*CNTR*/
927: #define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
928: #define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */

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929: /*PSCR*/
930: #define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
931: /*ARR*/
932: #define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
933: #define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
934: /*CCR1*/
935: #define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. *
936: #define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. *
937: /*CCR2*/
938: #define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. *
939: #define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. *
940: /*CCR3*/
941: #define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. *
942: #define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. *
943:
944: /**
945: * @}
946: */
947:
948: /*----------------------------------------------------------------------------*/
949: /**
950: * @brief 16-bit timer (TIM3)
951: */
952: typedef struct TIM3_struct
953: {
954: __IO uint8_t CR1; /*!< control register 1 */
955: __IO uint8_t IER; /*!< interrupt enable register */
956: __IO uint8_t SR1; /*!< status register 1 */
957: __IO uint8_t SR2; /*!< status register 2 */
958: __IO uint8_t EGR; /*!< event generation register */
959: __IO uint8_t CCMR1; /*!< CC mode register 1 */
960: __IO uint8_t CCMR2; /*!< CC mode register 2 */
961: __IO uint8_t CCER1; /*!< CC enable register 1 */
962: __IO uint8_t CNTRH; /*!< counter high */
963: __IO uint8_t CNTRL; /*!< counter low */
964: __IO uint8_t PSCR; /*!< prescaler register */
965: __IO uint8_t ARRH; /*!< auto-reload register high */
966: __IO uint8_t ARRL; /*!< auto-reload register low */
967: __IO uint8_t CCR1H; /*!< capture/compare register 1 high */
968: __IO uint8_t CCR1L; /*!< capture/compare register 1 low */
969: __IO uint8_t CCR2H; /*!< capture/compare register 2 high */
970: __IO uint8_t CCR2L; /*!< capture/compare register 2 low */
971: }
972: TIM3_TypeDef;
973:
974: /** @addtogroup TIM3_Registers_Reset_Value
975: * @{
976: */
977:
978: #define TIM3_CR1_RESET_VALUE ((uint8_t)0x00)
979: #define TIM3_IER_RESET_VALUE ((uint8_t)0x00)
980: #define TIM3_SR1_RESET_VALUE ((uint8_t)0x00)
981: #define TIM3_SR2_RESET_VALUE ((uint8_t)0x00)
982: #define TIM3_EGR_RESET_VALUE ((uint8_t)0x00)
983: #define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00)
984: #define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00)
985: #define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00)
986: #define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00)
987: #define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00)
988: #define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00)

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989: #define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF)

990: #define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF)
991: #define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00)
992: #define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00)
993: #define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00)
994: #define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00)
995:
996: /**
997: * @}
998: */
999:
1000: /** @addtogroup TIM3_Registers_Bits_Definition
1001: * @{
1002: */
1003: /*CR1*/
1004: #define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
1005: #define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
1006: #define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
1007: #define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
1008: #define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
1009: /*IER*/
1010: #define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable
mask. */
1011: #define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable
mask. */
1012: #define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
1013: /*SR1*/
1014: #define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag
mask. */
1015: #define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag
mask. */
1016: #define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
1017: /*SR2*/
1018: #define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag
mask. */
1019: #define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag
mask. */
1020: /*EGR*/
1021: #define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */
1022: #define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */
1023: #define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
1024: /*CCMR*/
1025: #define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */
1026: #define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */
1027: #define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
1028: #define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask.
*/
1029: #define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */
1030: /*CCER1*/
1031: #define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity
mask. */
1032: #define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask.
*/
1033: #define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity
mask. */
1034: #define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask.
*/
1035: /*CNTR*/
1036: #define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
1037: #define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */

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1038: /*PSCR*/
1039: #define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
1040: /*ARR*/
1041: #define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */
1042: #define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */
1043: /*CCR1*/
1044: #define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. *
1045: #define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. *
1046: /*CCR2*/
1047: #define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. *
1048: #define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. *
1049: /**
1050: * @}
1051: */
1052:
1053: /*----------------------------------------------------------------------------*/
1054: /**
1055: * @brief 8-bit system timer (TIM4)
1056: */
1057:
1058: typedef struct TIM4_struct
1059: {
1060: __IO uint8_t CR1; /*!< control register 1 */
1061: #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001)
1062: uint8_t RESERVED1; /*!< Reserved register */
1063: uint8_t RESERVED2; /*!< Reserved register */
1064: #endif
1065: __IO uint8_t IER; /*!< interrupt enable register */
1066: __IO uint8_t SR1; /*!< status register 1 */
1067: __IO uint8_t EGR; /*!< event generation register */
1068: __IO uint8_t CNTR; /*!< counter register */
1069: __IO uint8_t PSCR; /*!< prescaler register */
1070: __IO uint8_t ARR; /*!< auto-reload register */
1071: }
1072: TIM4_TypeDef;
1073:
1074: /** @addtogroup TIM4_Registers_Reset_Value
1075: * @{
1076: */
1077:
1078: #define TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
1079: #define TIM4_IER_RESET_VALUE ((uint8_t)0x00)
1080: #define TIM4_SR1_RESET_VALUE ((uint8_t)0x00)
1081: #define TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
1082: #define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
1083: #define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
1084: #define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
1085:
1086: /**
1087: * @}
1088: */
1089:
1090: /** @addtogroup TIM4_Registers_Bits_Definition
1091: * @{
1092: */
1093: /*CR1*/
1094: #define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */
1095: #define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
1096: #define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
1097: #define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */

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1098: #define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */

1099: /*IER*/
1100: #define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */
1101: /*SR1*/
1102: #define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
1103: /*EGR*/
1104: #define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
1105: /*CNTR*/
1106: #define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
1107: /*PSCR*/
1108: #define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */
1109: /*ARR*/
1110: #define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */
1111:
1112: /**
1113: * @}
1114: */
1115:
1116: /*----------------------------------------------------------------------------*/
1117: /**
1118: * @brief 16-bit timer with synchro module (TIM5)
1119: */
1120:
1121: typedef struct TIM5_struct
1122: {
1123: __IO uint8_t CR1; /*!<TIM5 Control Register 1 */
1124: __IO uint8_t CR2; /*!<TIM5 Control Register 2 */
1125: __IO uint8_t SMCR; /*!<TIM5 Slave Mode Control Register */
1126: __IO uint8_t IER; /*!<TIM5 Interrupt Enable Register */
1127: __IO uint8_t SR1; /*!<TIM5 Status Register 1 */
1128: __IO uint8_t SR2; /*!<TIM5 Status Register 2 */
1129: __IO uint8_t EGR; /*!<TIM5 Event Generation Register */
1130: __IO uint8_t CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */
1131: __IO uint8_t CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */
1132: __IO uint8_t CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */
1133: __IO uint8_t CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */
1134: __IO uint8_t CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */
1135: __IO uint8_t CNTRH; /*!<TIM5 Counter High */
1136: __IO uint8_t CNTRL; /*!<TIM5 Counter Low */
1137: __IO uint8_t PSCR; /*!<TIM5 Prescaler Register */
1138: __IO uint8_t ARRH; /*!<TIM5 Auto-Reload Register High */
1139: __IO uint8_t ARRL; /*!<TIM5 Auto-Reload Register Low */
1140: __IO uint8_t CCR1H; /*!<TIM5 Capture/Compare Register 1 High */
1141: __IO uint8_t CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */
1142: __IO uint8_t CCR2H; /*!<TIM5 Capture/Compare Register 2 High */
1143: __IO uint8_t CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */
1144: __IO uint8_t CCR3H; /*!<TIM5 Capture/Compare Register 3 High */
1145: __IO uint8_t CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */
1146: }TIM5_TypeDef;
1147:
1148: /** @addtogroup TIM5_Registers_Reset_Value
1149: * @{
1150: */
1151:
1152: #define TIM5_CR1_RESET_VALUE ((uint8_t)0x00)
1153: #define TIM5_CR2_RESET_VALUE ((uint8_t)0x00)
1154: #define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00)
1155: #define TIM5_IER_RESET_VALUE ((uint8_t)0x00)
1156: #define TIM5_SR1_RESET_VALUE ((uint8_t)0x00)
1157: #define TIM5_SR2_RESET_VALUE ((uint8_t)0x00)

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1158: #define TIM5_EGR_RESET_VALUE ((uint8_t)0x00)

1159: #define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00)
1160: #define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00)
1161: #define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00)
1162: #define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00)
1163: #define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00)
1164: #define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00)
1165: #define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00)
1166: #define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00)
1167: #define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF)
1168: #define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF)
1169: #define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00)
1170: #define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00)
1171: #define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00)
1172: #define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00)
1173: #define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00)
1174: #define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00)
1175:
1176: /**
1177: * @}
1178: */
1179:
1180: /** @addtogroup TIM5_Registers_Bits_Definition
1181: * @{
1182: */
1183: /* CR1*/
1184: #define TIM5_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable
mask. */
1185: #define TIM5_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */
1186: #define TIM5_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */
1187: #define TIM5_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */
1188: #define TIM5_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */
1189: /* CR2*/
1190: #define TIM5_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection Mask. */
1191: #define TIM5_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */
1192: /* SMCR*/
1193: #define TIM5_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
1194: #define TIM5_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */
1195: #define TIM5_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
1196: /*IER*/
1197: #define TIM5_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask.
*/
1198: #define TIM5_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt
Enable mask. */
1199: #define TIM5_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt
Enable mask. */
1200: #define TIM5_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt
Enable mask. */
1201: #define TIM5_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask.
*/
1202: /*SR1*/
1203: #define TIM5_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. *
1204: #define TIM5_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt
Flag mask. */
1205: #define TIM5_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt
Flag mask. */
1206: #define TIM5_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt
Flag mask. */
1207: #define TIM5_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */
1208: /*SR2*/

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1209: #define TIM5_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture

Flag mask. */
1210: #define TIM5_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture
Flag mask. */
1211: #define TIM5_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture
Flag mask. */
1212: /*EGR*/
1213: #define TIM5_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
1214: #define TIM5_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation
mask. */
1215: #define TIM5_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation
mask. */
1216: #define TIM5_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation
mask. */
1217: #define TIM5_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */
1218: /*CCMR*/
1219: #define TIM5_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler
mask. */
1220: #define TIM5_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. *
1221: #define TIM5_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */
1222: #define TIM5_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload
Enable mask. */
1223: #define TIM5_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection
mask. */
1224: /*CCER1*/
1225: #define TIM5_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output
Polarity mask. */
1226: #define TIM5_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output
enable mask. */
1227: #define TIM5_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output
Polarity mask. */
1228: #define TIM5_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output
enable mask. */
1229: /*CCER2*/
1230: #define TIM5_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output
Polarity mask. */
1231: #define TIM5_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output
enable mask. */
1232: /*CNTR*/
1233: #define TIM5_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */
1234: #define TIM5_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */
1235: /*PSCR*/
1236: #define TIM5_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */
1237: /*ARR*/
1238: #define TIM5_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. *
1239: #define TIM5_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. *
1240: /*CCR1*/
1241: #define TIM5_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB)
mask. */
1242: #define TIM5_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB)
mask. */
1243: /*CCR2*/
1244: #define TIM5_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB)
mask. */
1245: #define TIM5_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB)
mask. */
1246: /*CCR3*/
1247: #define TIM5_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB)
mask. */
1248: #define TIM5_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB)
mask. */
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1249: /*CCMR*/
1250: #define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01)
1251: /**
1252: * @}
1253: */
1254:
1255: /*----------------------------------------------------------------------------*/
1256: /**
1257: * @brief 8-bit system timer with synchro module(TIM6)
1258: */
1259:
1260: typedef struct TIM6_struct
1261: {
1262: __IO uint8_t CR1; /*!< control register 1 */
1263: __IO uint8_t CR2; /*!< control register 2 */
1264: __IO uint8_t SMCR; /*!< Synchro mode control register */
1265: __IO uint8_t IER; /*!< interrupt enable register */
1266: __IO uint8_t SR1; /*!< status register 1 */
1267: __IO uint8_t EGR; /*!< event generation register */
1268: __IO uint8_t CNTR; /*!< counter register */
1269: __IO uint8_t PSCR; /*!< prescaler register */
1270: __IO uint8_t ARR; /*!< auto-reload register */
1271: }
1272: TIM6_TypeDef;
1273: /** @addtogroup TIM6_Registers_Reset_Value
1274: * @{
1275: */
1276: #define TIM6_CR1_RESET_VALUE ((uint8_t)0x00)
1277: #define TIM6_CR2_RESET_VALUE ((uint8_t)0x00)
1278: #define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00)
1279: #define TIM6_IER_RESET_VALUE ((uint8_t)0x00)
1280: #define TIM6_SR1_RESET_VALUE ((uint8_t)0x00)
1281: #define TIM6_EGR_RESET_VALUE ((uint8_t)0x00)
1282: #define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00)
1283: #define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00)
1284: #define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF)
1285:
1286: /**
1287: * @}
1288: */
1289:
1290: /** @addtogroup TIM6_Registers_Bits_Definition
1291: * @{
1292: */
1293: /* CR1*/
1294: #define TIM6_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */
1295: #define TIM6_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */
1296: #define TIM6_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */
1297: #define TIM6_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */
1298: #define TIM6_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */
1299: /* CR2*/
1300: #define TIM6_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */
1301: /* SMCR*/
1302: #define TIM6_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */
1303: #define TIM6_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */
1304: #define TIM6_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */
1305: /* IER*/
1306: #define TIM6_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */
1307: #define TIM6_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */
1308: /* SR1*/

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1309: #define TIM6_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */

1310: #define TIM6_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */
1311: /* EGR*/
1312: #define TIM6_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */
1313: #define TIM6_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */
1314: /* CNTR*/
1315: #define TIM6_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */
1316: /* PSCR*/
1317: #define TIM6_PSCR_PSC ((uint8_t)0x07) /*!<Prescaler Value Mask. */
1318:
1319: #define TIM6_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */
1320: /**
1321: * @}
1322: */
1323: /*----------------------------------------------------------------------------*/
1324: /**
1325: * @brief Inter-Integrated Circuit (I2C)
1326: */
1327:
1328: typedef struct I2C_struct
1329: {
1330: __IO uint8_t CR1; /*!< I2C control register 1 */
1331: __IO uint8_t CR2; /*!< I2C control register 2 */
1332: __IO uint8_t FREQR; /*!< I2C frequency register */
1333: __IO uint8_t OARL; /*!< I2C own address register LSB */
1334: __IO uint8_t OARH; /*!< I2C own address register MSB */
1335: uint8_t RESERVED1; /*!< Reserved byte */
1336: __IO uint8_t DR; /*!< I2C data register */
1337: __IO uint8_t SR1; /*!< I2C status register 1 */
1338: __IO uint8_t SR2; /*!< I2C status register 2 */
1339: __IO uint8_t SR3; /*!< I2C status register 3 */
1340: __IO uint8_t ITR; /*!< I2C interrupt register */
1341: __IO uint8_t CCRL; /*!< I2C clock control register low */
1342: __IO uint8_t CCRH; /*!< I2C clock control register high */
1343: __IO uint8_t TRISER; /*!< I2C maximum rise time register */
1344: uint8_t RESERVED2; /*!< Reserved byte */
1345: }
1346: I2C_TypeDef;
1347:
1348: /** @addtogroup I2C_Registers_Reset_Value
1349: * @{
1350: */
1351:
1352: #define I2C_CR1_RESET_VALUE ((uint8_t)0x00)
1353: #define I2C_CR2_RESET_VALUE ((uint8_t)0x00)
1354: #define I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
1355: #define I2C_OARL_RESET_VALUE ((uint8_t)0x00)
1356: #define I2C_OARH_RESET_VALUE ((uint8_t)0x00)
1357: #define I2C_DR_RESET_VALUE ((uint8_t)0x00)
1358: #define I2C_SR1_RESET_VALUE ((uint8_t)0x00)
1359: #define I2C_SR2_RESET_VALUE ((uint8_t)0x00)
1360: #define I2C_SR3_RESET_VALUE ((uint8_t)0x00)
1361: #define I2C_ITR_RESET_VALUE ((uint8_t)0x00)
1362: #define I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
1363: #define I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
1364: #define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
1365:
1366: /**
1367: * @}
1368: */

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1369:
1370: /** @addtogroup I2C_Registers_Bits_Definition
1371: * @{
1372: */
1373:
1374: #define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave
mode) */
1375: #define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */
1376: #define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */
1377:
1378: #define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */
1379: #define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */
1380: #define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */
1381: #define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */
1382: #define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */
1383:
1384: #define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */
1385:
1386: #define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
1387: #define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */
1388:
1389: #define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */
1390: #define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address Mode Configuration */
1391: #define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */
1392:
1393: #define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */
1394:
1395: #define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) *
1396: #define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers)
*/
1397: #define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */
1398: #define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */
1399: #define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */
1400: #define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched
(slave mode) */
1401: #define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */
1402:
1403: #define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */
1404: #define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */
1405: #define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */
1406: #define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */
1407: #define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */
1408:
1409: #define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */
1410: #define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */
1411: #define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */
1412: #define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */
1413:
1414: #define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */
1415: #define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */
1416: #define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */
1417:
1418: #define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode)
*/
1419:
1420: #define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */
1421: #define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */
1422: #define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in
Fast/Standard mode (Master mode) bits [11..8] */
1423:

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1424: #define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard

mode (Master mode) */
1425:
1426: /**
1427: * @}
1428: */
1429:
1430: /*----------------------------------------------------------------------------*/
1431: /**
1432: * @brief Interrupt Controller (ITC)
1433: */
1434:
1435: typedef struct ITC_struct
1436: {
1437: __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */
1438: __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */
1439: __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */
1440: __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */
1441: __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */
1442: __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */
1443: __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */
1444: __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */
1445: }
1446: ITC_TypeDef;
1447:
1448: /** @addtogroup ITC_Registers_Reset_Value
1449: * @{
1450: */
1451:
1452: #define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority
registers */
1453:
1454: /**
1455: * @}
1456: */
1457:
1458: /** @addtogroup CPU_Registers_Bits_Definition
1459: * @{
1460: */
1461:
1462: #define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits
mask */
1463:
1464: /**
1465: * @}
1466: */
1467:
1468: /*----------------------------------------------------------------------------*/
1469: /**
1470: * @brief External Interrupt Controller (EXTI)
1471: */
1472:
1473: typedef struct EXTI_struct
1474: {
1475: __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
1476: __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */
1477: }
1478: EXTI_TypeDef;
1479:
1480: /** @addtogroup EXTI_Registers_Reset_Value

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1481: * @{
1482: */
1483:
1484: #define EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
1485: #define EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
1486:
1487: /**
1488: * @}
1489: */
1490:
1491: /** @addtogroup EXTI_Registers_Bits_Definition
1492: * @{
1493: */
1494:
1495: #define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity
bits mask */
1496: #define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity
bits mask */
1497: #define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity
bits mask */
1498: #define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity
bits mask */
1499:
1500: #define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask
*/
1501: #define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity
bits mask */
1502:
1503: /**
1504: * @}
1505: */
1506:
1507:
1508:
1509: /*----------------------------------------------------------------------------*/
1510: /**
1511: * @brief FLASH program and Data memory (FLASH)
1512: */
1513:
1514: typedef struct FLASH_struct
1515: {
1516: __IO uint8_t CR1; /*!< Flash control register 1 */
1517: __IO uint8_t CR2; /*!< Flash control register 2 */
1518: __IO uint8_t NCR2; /*!< Flash complementary control register 2 */
1519: __IO uint8_t FPR; /*!< Flash protection register */
1520: __IO uint8_t NFPR; /*!< Flash complementary protection register */
1521: __IO uint8_t IAPSR; /*!< Flash in-application programming status register */
1522: uint8_t RESERVED1; /*!< Reserved byte */
1523: uint8_t RESERVED2; /*!< Reserved byte */
1524: __IO uint8_t PUKR; /*!< Flash program memory unprotection register */
1525: uint8_t RESERVED3; /*!< Reserved byte */
1526: __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */
1527: }
1528: FLASH_TypeDef;
1529:
1530: /** @addtogroup FLASH_Registers_Reset_Value
1531: * @{
1532: */
1533:
1534: #define FLASH_CR1_RESET_VALUE ((uint8_t)0x00)

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1535: #define FLASH_CR2_RESET_VALUE ((uint8_t)0x00)

1536: #define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF)
1537: #define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
1538: #define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00)
1539: #define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00)
1540:
1541: /**
1542: * @}
1543: */
1544:
1545: /** @addtogroup FLASH_Registers_Bits_Definition
1546: * @{
1547: */
1548:
1549: #define FLASH_CR1_HALT ((uint8_t)0x08) /*!< Standby in Halt mode mask */
1550: #define FLASH_CR1_AHALT ((uint8_t)0x04) /*!< Standby in Active Halt mode mask
*/
1551: #define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable mask */
1552: #define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time mask */
1553:
1554: #define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Select option byte mask */
1555: #define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word Programming mask */
1556: #define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block mask */
1557: #define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode mask */
1558: #define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block mask */
1559:
1560: #define FLASH_NCR2_NOPT ((uint8_t)0x80) /*!< Select option byte mask */
1561: #define FLASH_NCR2_NWPRG ((uint8_t)0x40) /*!< Word Programming mask */
1562: #define FLASH_NCR2_NERASE ((uint8_t)0x20) /*!< Erase block mask */
1563: #define FLASH_NCR2_NFPRG ((uint8_t)0x10) /*!< Fast programming mode mask */
1564: #define FLASH_NCR2_NPRG ((uint8_t)0x01) /*!< Program block mask */
1565:
1566: #define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag mask */
1567: #define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask *
1568: #define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag mask */
1569: #define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Flash Program memory unlocked
flag mask */
1570: #define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected
page mask */
1571:
1572: #define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory
unprotection mask */
1573:
1574: #define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */
1575:
1576: /**
1577: * @}
1578: */
1579:
1580: /*----------------------------------------------------------------------------*/
1581: /**
1582: * @brief Option Bytes (OPT)
1583: */
1584: typedef struct OPT_struct
1585: {
1586: __IO uint8_t OPT0; /*!< Option byte 0: Read-out protection (not accessible in
IAP mode) */
1587: __IO uint8_t OPT1; /*!< Option byte 1: User boot code */
1588: __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */
1589: __IO uint8_t OPT2; /*!< Option byte 2: Alternate function remapping */

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1590: __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */

1591: __IO uint8_t OPT3; /*!< Option byte 3: Watchdog option */
1592: __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */
1593: __IO uint8_t OPT4; /*!< Option byte 4: Clock option */
1594: __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */
1595: __IO uint8_t OPT5; /*!< Option byte 5: HSE clock startup */
1596: __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */
1597: uint8_t RESERVED1; /*!< Reserved Option byte*/
1598: uint8_t RESERVED2; /*!< Reserved Option byte*/
1599: __IO uint8_t OPT7; /*!< Option byte 7: flash wait states */
1600: __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */
1601: }
1602: OPT_TypeDef;
1603:
1604: /*----------------------------------------------------------------------------*/
1605: /**
1606: * @brief Independent Watchdog (IWDG)
1607: */
1608:
1609: typedef struct IWDG_struct
1610: {
1611: __IO uint8_t KR; /*!< Key Register */
1612: __IO uint8_t PR; /*!< Prescaler Register */
1613: __IO uint8_t RLR; /*!< Reload Register */
1614: }
1615: IWDG_TypeDef;
1616:
1617: /** @addtogroup IWDG_Registers_Reset_Value
1618: * @{
1619: */
1620:
1621: #define IWDG_PR_RESET_VALUE ((uint8_t)0x00)
1622: #define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
1623:
1624: /**
1625: * @}
1626: */
1627:
1628: /*----------------------------------------------------------------------------*/
1629: /**
1630: * @brief Window Watchdog (WWDG)
1631: */
1632:
1633: typedef struct WWDG_struct
1634: {
1635: __IO uint8_t CR; /*!< Control Register */
1636: __IO uint8_t WR; /*!< Window Register */
1637: }
1638: WWDG_TypeDef;
1639:
1640: /** @addtogroup WWDG_Registers_Reset_Value
1641: * @{
1642: */
1643:
1644: #define WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
1645: #define WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
1646:
1647: /**
1648: * @}
1649: */

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1650:
1651: /** @addtogroup WWDG_Registers_Bits_Definition
1652: * @{
1653: */
1654:
1655: #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */
1656: #define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */
1657: #define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */
1658:
1659: #define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */
1660: #define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */
1661:
1662: /**
1663: * @}
1664: */
1665:
1666: /*----------------------------------------------------------------------------*/
1667: /**
1668: * @brief Reset Controller (RST)
1669: */
1670:
1671: typedef struct RST_struct
1672: {
1673: __IO uint8_t SR; /*!< Reset status register */
1674: }
1675: RST_TypeDef;
1676:
1677: /** @addtogroup RST_Registers_Bits_Definition
1678: * @{
1679: */
1680:
1681: #define RST_SR_EMCF ((uint8_t)0x10) /*!< EMC reset flag bit mask */
1682: #define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag bit mask */
1683: #define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */
1684: #define RST_SR_IWDGF ((uint8_t)0x02) /*!< IWDG reset flag bit mask */
1685: #define RST_SR_WWDGF ((uint8_t)0x01) /*!< WWDG reset flag bit mask */
1686:
1687: /**
1688: * @}
1689: */
1690:
1691: /*----------------------------------------------------------------------------*/
1692: /**
1693: * @brief Serial Peripheral Interface (SPI)
1694: */
1695:
1696: typedef struct SPI_struct
1697: {
1698: __IO uint8_t CR1; /*!< SPI control register 1 */
1699: __IO uint8_t CR2; /*!< SPI control register 2 */
1700: __IO uint8_t ICR; /*!< SPI interrupt control register */
1701: __IO uint8_t SR; /*!< SPI status register */
1702: __IO uint8_t DR; /*!< SPI data I/O register */
1703: __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */
1704: __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */
1705: __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */
1706: }
1707: SPI_TypeDef;
1708:
1709: /** @addtogroup SPI_Registers_Reset_Value

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1710: * @{
1711: */
1712:
1713: #define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value
*/
1714: #define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value
*/
1715: #define SPI_ICR_RESET_VALUE ((uint8_t)0x00) /*!< Interrupt Control Register
reset value */
1716: #define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */
1717: #define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */
1718: #define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value
*/
1719: #define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */
1720: #define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */
1721:
1722: /**
1723: * @}
1724: */
1725:
1726: /** @addtogroup SPI_Registers_Bits_Definition
1727: * @{
1728: */
1729:
1730: #define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */
1731: #define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */
1732: #define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */
1733: #define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */
1734: #define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */
1735: #define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */
1736:
1737: #define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask
*/
1738: #define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode
mask */
1739: #define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask
*/
1740: #define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */
1741: #define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */
1742: #define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */
1743: #define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */
1744:
1745: #define SPI_ICR_TXEI ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask
*/
1746: #define SPI_ICR_RXEI ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask
*/
1747: #define SPI_ICR_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */
1748: #define SPI_ICR_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */
1749:
1750: #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
1751: #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
1752: #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
1753: #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */
1754: #define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */
1755: #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */
1756: #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */
1757:
1758: /**
1759: * @}
1760: */

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1761:
1762: /*----------------------------------------------------------------------------*/
1763: /**
1764: * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)
1765: */
1766:
1767: typedef struct UART1_struct
1768: {
1769: __IO uint8_t SR; /*!< UART1 status register */
1770: __IO uint8_t DR; /*!< UART1 data register */
1771: __IO uint8_t BRR1; /*!< UART1 baud rate register */
1772: __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
1773: __IO uint8_t CR1; /*!< UART1 control register 1 */
1774: __IO uint8_t CR2; /*!< UART1 control register 2 */
1775: __IO uint8_t CR3; /*!< UART1 control register 3 */
1776: __IO uint8_t CR4; /*!< UART1 control register 4 */
1777: __IO uint8_t CR5; /*!< UART1 control register 5 */
1778: __IO uint8_t GTR; /*!< UART1 guard time register */
1779: __IO uint8_t PSCR; /*!< UART1 prescaler register */
1780: }
1781: UART1_TypeDef;
1782:
1783: /** @addtogroup UART1_Registers_Reset_Value
1784: * @{
1785: */
1786:
1787: #define UART1_SR_RESET_VALUE ((uint8_t)0xC0)
1788: #define UART1_BRR1_RESET_VALUE ((uint8_t)0x00)
1789: #define UART1_BRR2_RESET_VALUE ((uint8_t)0x00)
1790: #define UART1_CR1_RESET_VALUE ((uint8_t)0x00)
1791: #define UART1_CR2_RESET_VALUE ((uint8_t)0x00)
1792: #define UART1_CR3_RESET_VALUE ((uint8_t)0x00)
1793: #define UART1_CR4_RESET_VALUE ((uint8_t)0x00)
1794: #define UART1_CR5_RESET_VALUE ((uint8_t)0x00)
1795: #define UART1_GTR_RESET_VALUE ((uint8_t)0x00)
1796: #define UART1_PSCR_RESET_VALUE ((uint8_t)0x00)
1797:
1798: /**
1799: * @}
1800: */
1801:
1802: /** @addtogroup UART1_Registers_Bits_Definition
1803: * @{
1804: */
1805:
1806: #define UART1_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
1807: #define UART1_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
1808: #define UART1_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
1809: #define UART1_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
1810: #define UART1_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
1811: #define UART1_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
1812: #define UART1_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
1813: #define UART1_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
1814:
1815: #define UART1_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask *
1816:
1817: #define UART1_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask
*/
1818: #define UART1_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask
*/

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1819:
1820: #define UART1_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
1821: #define UART1_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
1822: #define UART1_CR1_UARTD ((uint8_t)0x20) /*!< UART1 Disable (for low power
consumption) */
1823: #define UART1_CR1_M ((uint8_t)0x10) /*!< Word length mask */
1824: #define UART1_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
1825: #define UART1_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */
1826: #define UART1_CR1_PS ((uint8_t)0x02) /*!< UART1 Parity Selection */
1827: #define UART1_CR1_PIEN ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask *
1828:
1829: #define UART1_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
1830: #define UART1_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt
Enable mask */
1831: #define UART1_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
1832: #define UART1_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
1833: #define UART1_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
1834: #define UART1_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
1835: #define UART1_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
1836: #define UART1_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
1837:
1838: #define UART1_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
1839: #define UART1_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
1840: #define UART1_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */
1841: #define UART1_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */
1842: #define UART1_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */
1843: #define UART1_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
1844:
1845: #define UART1_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable
mask */
1846: #define UART1_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
1847: #define UART1_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
1848: #define UART1_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART1 node mask */
1849:
1850: #define UART1_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */
1851: #define UART1_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
1852: #define UART1_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
1853: #define UART1_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
1854: #define UART1_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */
1855:
1856: /**
1857: * @}
1858: */
1859:
1860: /*----------------------------------------------------------------------------*/
1861: /**
1862: * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2)
1863: */
1864:
1865: typedef struct UART2_struct
1866: {
1867: __IO uint8_t SR; /*!< UART1 status register */
1868: __IO uint8_t DR; /*!< UART1 data register */
1869: __IO uint8_t BRR1; /*!< UART1 baud rate register */
1870: __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
1871: __IO uint8_t CR1; /*!< UART1 control register 1 */
1872: __IO uint8_t CR2; /*!< UART1 control register 2 */
1873: __IO uint8_t CR3; /*!< UART1 control register 3 */
1874: __IO uint8_t CR4; /*!< UART1 control register 4 */
1875: __IO uint8_t CR5; /*!< UART1 control register 5 */

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1876: __IO uint8_t CR6; /*!< UART1 control register 6 */

1877: __IO uint8_t GTR; /*!< UART1 guard time register */
1878: __IO uint8_t PSCR; /*!< UART1 prescaler register */
1879: }
1880: UART2_TypeDef;
1881:
1882: /** @addtogroup UART2_Registers_Reset_Value
1883: * @{
1884: */
1885:
1886: #define UART2_SR_RESET_VALUE ((uint8_t)0xC0)
1887: #define UART2_BRR1_RESET_VALUE ((uint8_t)0x00)
1888: #define UART2_BRR2_RESET_VALUE ((uint8_t)0x00)
1889: #define UART2_CR1_RESET_VALUE ((uint8_t)0x00)
1890: #define UART2_CR2_RESET_VALUE ((uint8_t)0x00)
1891: #define UART2_CR3_RESET_VALUE ((uint8_t)0x00)
1892: #define UART2_CR4_RESET_VALUE ((uint8_t)0x00)
1893: #define UART2_CR5_RESET_VALUE ((uint8_t)0x00)
1894: #define UART2_CR6_RESET_VALUE ((uint8_t)0x00)
1895: #define UART2_GTR_RESET_VALUE ((uint8_t)0x00)
1896: #define UART2_PSCR_RESET_VALUE ((uint8_t)0x00)
1897:
1898: /**
1899: * @}
1900: */
1901:
1902: /** @addtogroup UART2_Registers_Bits_Definition
1903: * @{
1904: */
1905:
1906: #define UART2_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
1907: #define UART2_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
1908: #define UART2_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
1909: #define UART2_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
1910: #define UART2_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
1911: #define UART2_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
1912: #define UART2_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
1913: #define UART2_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
1914:
1915: #define UART2_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask *
1916:
1917: #define UART2_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask
*/
1918: #define UART2_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask
*/
1919:
1920: #define UART2_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
1921: #define UART2_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
1922: #define UART2_CR1_UARTD ((uint8_t)0x20) /*!< UART2 Disable (for low power
consumption) */
1923: #define UART2_CR1_M ((uint8_t)0x10) /*!< Word length mask */
1924: #define UART2_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
1925: #define UART2_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */
1926: #define UART2_CR1_PS ((uint8_t)0x02) /*!< UART2 Parity Selection */
1927: #define UART2_CR1_PIEN ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask *
1928:
1929: #define UART2_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
1930: #define UART2_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt
Enable mask */
1931: #define UART2_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */

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1932: #define UART2_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
1933: #define UART2_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
1934: #define UART2_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
1935: #define UART2_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
1936: #define UART2_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
1937:
1938: #define UART2_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
1939: #define UART2_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
1940: #define UART2_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */
1941: #define UART2_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */
1942: #define UART2_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */
1943: #define UART2_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
1944:
1945: #define UART2_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable
mask */
1946: #define UART2_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
1947: #define UART2_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
1948: #define UART2_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART2 node mask */
1949:
1950: #define UART2_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */
1951: #define UART2_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
1952: #define UART2_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
1953: #define UART2_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */
1954:
1955: #define UART2_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */
1956: #define UART2_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */
1957: #define UART2_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
1958: #define UART2_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt
Enable */
1959: #define UART2_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */
1960: #define UART2_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */
1961:
1962: /**
1963: * @}
1964: */
1965:
1966:
1967: /*----------------------------------------------------------------------------*/
1968: /**
1969: * @brief LIN Universal Asynchronous Receiver Transmitter (UART3)
1970: */
1971:
1972: typedef struct UART3_struct
1973: {
1974: __IO uint8_t SR; /*!< status register */
1975: __IO uint8_t DR; /*!< data register */
1976: __IO uint8_t BRR1; /*!< baud rate register */
1977: __IO uint8_t BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */
1978: __IO uint8_t CR1; /*!< control register 1 */
1979: __IO uint8_t CR2; /*!< control register 2 */
1980: __IO uint8_t CR3; /*!< control register 3 */
1981: __IO uint8_t CR4; /*!< control register 4 */
1982: uint8_t RESERVED; /*!< Reserved byte */
1983: __IO uint8_t CR6; /*!< control register 5 */
1984: }
1985: UART3_TypeDef;
1986:
1987: /** @addtogroup UART3_Registers_Reset_Value
1988: * @{
1989: */

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1990:
1991: #define UART3_SR_RESET_VALUE ((uint8_t)0xC0)
1992: #define UART3_BRR1_RESET_VALUE ((uint8_t)0x00)
1993: #define UART3_BRR2_RESET_VALUE ((uint8_t)0x00)
1994: #define UART3_CR1_RESET_VALUE ((uint8_t)0x00)
1995: #define UART3_CR2_RESET_VALUE ((uint8_t)0x00)
1996: #define UART3_CR3_RESET_VALUE ((uint8_t)0x00)
1997: #define UART3_CR4_RESET_VALUE ((uint8_t)0x00)
1998: #define UART3_CR6_RESET_VALUE ((uint8_t)0x00)
1999:
2000: /**
2001: * @}
2002: */
2003:
2004: /** @addtogroup UART3_Registers_Bits_Definition
2005: * @{
2006: */
2007:
2008: #define UART3_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
2009: #define UART3_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
2010: #define UART3_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
2011: #define UART3_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
2012: #define UART3_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
2013: #define UART3_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
2014: #define UART3_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
2015: #define UART3_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
2016:
2017: #define UART3_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask *
2018:
2019: #define UART3_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask
*/
2020: #define UART3_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask
*/
2021:
2022: #define UART3_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
2023: #define UART3_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
2024: #define UART3_CR1_UARTD ((uint8_t)0x20) /*!< UART Disable (for low power
consumption) */
2025: #define UART3_CR1_M ((uint8_t)0x10) /*!< Word length mask */
2026: #define UART3_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
2027: #define UART3_CR1_PCEN ((uint8_t)0x04) /*!< Parity control enable mask */
2028: #define UART3_CR1_PS ((uint8_t)0x02) /*!< Parity selection bit mask */
2029: #define UART3_CR1_PIEN ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */
2030:
2031: #define UART3_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
2032: #define UART3_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt
Enable mask */
2033: #define UART3_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
2034: #define UART3_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
2035: #define UART3_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
2036: #define UART3_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
2037: #define UART3_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
2038: #define UART3_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
2039:
2040: #define UART3_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
2041: #define UART3_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
2042:
2043: #define UART3_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable
mask */
2044: #define UART3_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */

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2045: #define UART3_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
2046: #define UART3_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART3 node mask */
2047:
2048: #define UART3_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */
2049: #define UART3_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */
2050: #define UART3_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
2051: #define UART3_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt
Enable */
2052: #define UART3_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */
2053: #define UART3_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */
2054:
2055: /**
2056: * @}
2057: */
2058:
2059: /*----------------------------------------------------------------------------*/
2060: /**
2061: * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART4)
2062: */
2063: #if defined(STM8AF622x)
2064: typedef struct UART4_struct
2065: {
2066: __IO uint8_t SR; /*!< UART4 status register */
2067: __IO uint8_t DR; /*!< UART4 data register */
2068: __IO uint8_t BRR1; /*!< UART4 baud rate register */
2069: __IO uint8_t BRR2; /*!< UART4 DIV mantissa[11:8] SCIDIV fraction */
2070: __IO uint8_t CR1; /*!< UART4 control register 1 */
2071: __IO uint8_t CR2; /*!< UART4 control register 2 */
2072: __IO uint8_t CR3; /*!< UART4 control register 3 */
2073: __IO uint8_t CR4; /*!< UART4 control register 4 */
2074: __IO uint8_t CR5; /*!< UART4 control register 5 */
2075: __IO uint8_t CR6; /*!< UART4 control register 6 */
2076: __IO uint8_t GTR; /*!< UART4 guard time register */
2077: __IO uint8_t PSCR; /*!< UART4 prescaler register */
2078: }
2079: UART4_TypeDef;
2080:
2081: /** @addtogroup UART4_Registers_Reset_Value
2082: * @{
2083: */
2084:
2085: #define UART4_SR_RESET_VALUE ((uint8_t)0xC0)
2086: #define UART4_BRR1_RESET_VALUE ((uint8_t)0x00)
2087: #define UART4_BRR2_RESET_VALUE ((uint8_t)0x00)
2088: #define UART4_CR1_RESET_VALUE ((uint8_t)0x00)
2089: #define UART4_CR2_RESET_VALUE ((uint8_t)0x00)
2090: #define UART4_CR3_RESET_VALUE ((uint8_t)0x00)
2091: #define UART4_CR4_RESET_VALUE ((uint8_t)0x00)
2092: #define UART4_CR5_RESET_VALUE ((uint8_t)0x00)
2093: #define UART4_CR6_RESET_VALUE ((uint8_t)0x00)
2094: #define UART4_GTR_RESET_VALUE ((uint8_t)0x00)
2095: #define UART4_PSCR_RESET_VALUE ((uint8_t)0x00)
2096:
2097: /**
2098: * @}
2099: */
2100:
2101: /** @addtogroup UART4_Registers_Bits_Definition
2102: * @{
2103: */

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2104:
2105: #define UART4_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */
2106: #define UART4_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */
2107: #define UART4_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */
2108: #define UART4_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */
2109: #define UART4_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */
2110: #define UART4_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */
2111: #define UART4_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */
2112: #define UART4_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */
2113:
2114: #define UART4_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART4DIV [7:0] mask *
2115:
2116: #define UART4_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART4DIV [11:8] mask
*/
2117: #define UART4_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART4DIV [3:0] mask
*/
2118:
2119: #define UART4_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */
2120: #define UART4_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */
2121: #define UART4_CR1_UARTD ((uint8_t)0x20) /*!< UART4 Disable (for low power
consumption) */
2122: #define UART4_CR1_M ((uint8_t)0x10) /*!< Word length mask */
2123: #define UART4_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */
2124: #define UART4_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */
2125: #define UART4_CR1_PS ((uint8_t)0x02) /*!< UART4 Parity Selection */
2126: #define UART4_CR1_PIEN ((uint8_t)0x01) /*!< UART4 Parity Interrupt Enable mask *
2127:
2128: #define UART4_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */
2129: #define UART4_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt
Enable mask */
2130: #define UART4_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */
2131: #define UART4_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */
2132: #define UART4_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */
2133: #define UART4_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */
2134: #define UART4_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */
2135: #define UART4_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */
2136:
2137: #define UART4_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */
2138: #define UART4_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */
2139: #define UART4_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */
2140: #define UART4_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */
2141: #define UART4_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */
2142: #define UART4_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */
2143:
2144: #define UART4_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable
mask */
2145: #define UART4_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */
2146: #define UART4_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */
2147: #define UART4_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART4 node mask */
2148:
2149: #define UART4_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */
2150: #define UART4_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */
2151: #define UART4_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */
2152: #define UART4_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */
2153: #define UART4_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */
2154:
2155: #define UART4_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */
2156: #define UART4_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */
2157: #define UART4_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */
2158: #define UART4_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt
Enable */
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2159: #define UART4_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */

2160: #define UART4_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */
2161: #endif /* STM8AF622x */
2162:
2163: /**
2164: * @}
2165: */
2166:
2167: /*----------------------------------------------------------------------------*/
2168:
2169: /*----------------------------------------------------------------------------*/
2170: /**
2171: * @brief Controller Area Network (CAN)
2172: */
2173:
2174: typedef struct
2175: {
2176: __IO uint8_t MCR; /*!< CAN master control register */
2177: __IO uint8_t MSR; /*!< CAN master status register */
2178: __IO uint8_t TSR; /*!< CAN transmit status register */
2179: __IO uint8_t TPR; /*!< CAN transmit priority register */
2180: __IO uint8_t RFR; /*!< CAN receive FIFO register */
2181: __IO uint8_t IER; /*!< CAN interrupt enable register */
2182: __IO uint8_t DGR; /*!< CAN diagnosis register */
2183: __IO uint8_t PSR; /*!< CAN page selection register */
2184:
2185: union
2186: {
2187: struct
2188: {
2189: __IO uint8_t MCSR;
2190: __IO uint8_t MDLCR;
2191: __IO uint8_t MIDR1;
2192: __IO uint8_t MIDR2;
2193: __IO uint8_t MIDR3;
2194: __IO uint8_t MIDR4;
2195: __IO uint8_t MDAR1;
2196: __IO uint8_t MDAR2;
2197: __IO uint8_t MDAR3;
2198: __IO uint8_t MDAR4;
2199: __IO uint8_t MDAR5;
2200: __IO uint8_t MDAR6;
2201: __IO uint8_t MDAR7;
2202: __IO uint8_t MDAR8;
2203: __IO uint8_t MTSRL;
2204: __IO uint8_t MTSRH;
2205: }TxMailbox;
2206:
2207: struct
2208: {
2209: __IO uint8_t FR01;
2210: __IO uint8_t FR02;
2211: __IO uint8_t FR03;
2212: __IO uint8_t FR04;
2213: __IO uint8_t FR05;
2214: __IO uint8_t FR06;
2215: __IO uint8_t FR07;
2216: __IO uint8_t FR08;
2217:
2218: __IO uint8_t FR09;

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2219: __IO uint8_t FR10;

2220: __IO uint8_t FR11;
2221: __IO uint8_t FR12;
2222: __IO uint8_t FR13;
2223: __IO uint8_t FR14;
2224: __IO uint8_t FR15;
2225: __IO uint8_t FR16;
2226: }Filter;
2227:
2228: struct
2229: {
2230: __IO uint8_t F0R1;
2231: __IO uint8_t F0R2;
2232: __IO uint8_t F0R3;
2233: __IO uint8_t F0R4;
2234: __IO uint8_t F0R5;
2235: __IO uint8_t F0R6;
2236: __IO uint8_t F0R7;
2237: __IO uint8_t F0R8;
2238:
2239: __IO uint8_t F1R1;
2240: __IO uint8_t F1R2;
2241: __IO uint8_t F1R3;
2242: __IO uint8_t F1R4;
2243: __IO uint8_t F1R5;
2244: __IO uint8_t F1R6;
2245: __IO uint8_t F1R7;
2246: __IO uint8_t F1R8;
2247: }Filter01;
2248:
2249: struct
2250: {
2251: __IO uint8_t F2R1;
2252: __IO uint8_t F2R2;
2253: __IO uint8_t F2R3;
2254: __IO uint8_t F2R4;
2255: __IO uint8_t F2R5;
2256: __IO uint8_t F2R6;
2257: __IO uint8_t F2R7;
2258: __IO uint8_t F2R8;
2259:
2260: __IO uint8_t F3R1;
2261: __IO uint8_t F3R2;
2262: __IO uint8_t F3R3;
2263: __IO uint8_t F3R4;
2264: __IO uint8_t F3R5;
2265: __IO uint8_t F3R6;
2266: __IO uint8_t F3R7;
2267: __IO uint8_t F3R8;
2268: }Filter23;
2269:
2270: struct
2271: {
2272: __IO uint8_t F4R1;
2273: __IO uint8_t F4R2;
2274: __IO uint8_t F4R3;
2275: __IO uint8_t F4R4;
2276: __IO uint8_t F4R5;
2277: __IO uint8_t F4R6;
2278: __IO uint8_t F4R7;

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2279: __IO uint8_t F4R8;

2280:
2281: __IO uint8_t F5R1;
2282: __IO uint8_t F5R2;
2283: __IO uint8_t F5R3;
2284: __IO uint8_t F5R4;
2285: __IO uint8_t F5R5;
2286: __IO uint8_t F5R6;
2287: __IO uint8_t F5R7;
2288: __IO uint8_t F5R8;
2289: } Filter45;
2290:
2291: struct
2292: {
2293: __IO uint8_t ESR;
2294: __IO uint8_t EIER;
2295: __IO uint8_t TECR;
2296: __IO uint8_t RECR;
2297: __IO uint8_t BTR1;
2298: __IO uint8_t BTR2;
2299: uint8_t Reserved1[2];
2300: __IO uint8_t FMR1;
2301: __IO uint8_t FMR2;
2302: __IO uint8_t FCR1;
2303: __IO uint8_t FCR2;
2304: __IO uint8_t FCR3;
2305: uint8_t Reserved2[3];
2306: }Config;
2307:
2308: struct
2309: {
2310: __IO uint8_t MFMI;
2311: __IO uint8_t MDLCR;
2312: __IO uint8_t MIDR1;
2313: __IO uint8_t MIDR2;
2314: __IO uint8_t MIDR3;
2315: __IO uint8_t MIDR4;
2316: __IO uint8_t MDAR1;
2317: __IO uint8_t MDAR2;
2318: __IO uint8_t MDAR3;
2319: __IO uint8_t MDAR4;
2320: __IO uint8_t MDAR5;
2321: __IO uint8_t MDAR6;
2322: __IO uint8_t MDAR7;
2323: __IO uint8_t MDAR8;
2324: __IO uint8_t MTSRL;
2325: __IO uint8_t MTSRH;
2326: }RxFIFO;
2327: }Page;
2328: } CAN_TypeDef;
2329:
2330: /** @addtogroup CAN_Registers_Bits_Definition
2331: * @{
2332: */
2333: /******************************* Common ***************************************/
2334: /* CAN Master Control Register bits */
2335: #define CAN_MCR_INRQ ((uint8_t)0x01)
2336: #define CAN_MCR_SLEEP ((uint8_t)0x02)
2337: #define CAN_MCR_TXFP ((uint8_t)0x04)
2338: #define CAN_MCR_RFLM ((uint8_t)0x08)

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2339: #define CAN_MCR_NART ((uint8_t)0x10)

2340: #define CAN_MCR_AWUM ((uint8_t)0x20)
2341: #define CAN_MCR_ABOM ((uint8_t)0x40)
2342: #define CAN_MCR_TTCM ((uint8_t)0x80)
2343:
2344: /* CAN Master Status Register bits */
2345: #define CAN_MSR_INAK ((uint8_t)0x01)
2346: #define CAN_MSR_SLAK ((uint8_t)0x02)
2347: #define CAN_MSR_ERRI ((uint8_t)0x04)
2348: #define CAN_MSR_WKUI ((uint8_t)0x08)
2349: #define CAN_MSR_TX ((uint8_t)0x10)
2350: #define CAN_MSR_RX ((uint8_t)0x20)
2351:
2352: /* CAN Transmit Status Register bits */
2353: #define CAN_TSR_RQCP0 ((uint8_t)0x01)
2354: #define CAN_TSR_RQCP1 ((uint8_t)0x02)
2355: #define CAN_TSR_RQCP2 ((uint8_t)0x04)
2356: #define CAN_TSR_RQCP012 ((uint8_t)0x07)
2357: #define CAN_TSR_TXOK0 ((uint8_t)0x10)
2358: #define CAN_TSR_TXOK1 ((uint8_t)0x20)
2359: #define CAN_TSR_TXOK2 ((uint8_t)0x40)
2360:
2361: #define CAN_TPR_CODE0 ((uint8_t)0x01)
2362: #define CAN_TPR_TME0 ((uint8_t)0x04)
2363: #define CAN_TPR_TME1 ((uint8_t)0x08)
2364: #define CAN_TPR_TME2 ((uint8_t)0x10)
2365: #define CAN_TPR_LOW0 ((uint8_t)0x20)
2366: #define CAN_TPR_LOW1 ((uint8_t)0x40)
2367: #define CAN_TPR_LOW2 ((uint8_t)0x80)
2368: /* CAN Receive FIFO Register bits */
2369: #define CAN_RFR_FMP01 ((uint8_t)0x03)
2370: #define CAN_RFR_FULL ((uint8_t)0x08)
2371: #define CAN_RFR_FOVR ((uint8_t)0x10)
2372: #define CAN_RFR_RFOM ((uint8_t)0x20)
2373:
2374: /* CAN Interrupt Register bits */
2375: #define CAN_IER_TMEIE ((uint8_t)0x01)
2376: #define CAN_IER_FMPIE ((uint8_t)0x02)
2377: #define CAN_IER_FFIE ((uint8_t)0x04)
2378: #define CAN_IER_FOVIE ((uint8_t)0x08)
2379: #define CAN_IER_WKUIE ((uint8_t)0x80)
2380:
2381:
2382: /* CAN diagnostic Register bits */
2383: #define CAN_DGR_LBKM ((uint8_t)0x01)
2384: #define CAN_DGR_SLIM ((uint8_t)0x02)
2385: #define CAN_DGR_SAMP ((uint8_t)0x04)
2386: #define CAN_DGR_RX ((uint8_t)0x08)
2387: #define CAN_DGR_TXM2E ((uint8_t)0x10)
2388:
2389:
2390: /* CAN page select Register bits */
2391: #define CAN_PSR_PS0 ((uint8_t)0x01)
2392: #define CAN_PSR_PS1 ((uint8_t)0x02)
2393: #define CAN_PSR_PS2 ((uint8_t)0x04)
2394:
2395: /******************** Tx MailBox & Fifo Page common bits **********************/
2396: #define CAN_MCSR_TXRQ ((uint8_t)0x01)
2397: #define CAN_MCSR_ABRQ ((uint8_t)0x02)
2398: #define CAN_MCSR_RQCP ((uint8_t)0x04)

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2399: #define CAN_MCSR_TXOK ((uint8_t)0x08)

2400: #define CAN_MCSR_ALST ((uint8_t)0x10)
2401: #define CAN_MCSR_TERR ((uint8_t)0x20)
2402:
2403: #define CAN_MDLCR_DLC ((uint8_t)0x0F)
2404: #define CAN_MDLCR_TGT ((uint8_t)0x80)
2405:
2406: #define CAN_MIDR1_RTR ((uint8_t)0x20)
2407: #define CAN_MIDR1_IDE ((uint8_t)0x40)
2408:
2409:
2410: /************************* Filter Page ****************************************/
2411:
2412: /* CAN Error Status Register bits */
2413: #define CAN_ESR_EWGF ((uint8_t)0x01)
2414: #define CAN_ESR_EPVF ((uint8_t)0x02)
2415: #define CAN_ESR_BOFF ((uint8_t)0x04)
2416: #define CAN_ESR_LEC0 ((uint8_t)0x10)
2417: #define CAN_ESR_LEC1 ((uint8_t)0x20)
2418: #define CAN_ESR_LEC2 ((uint8_t)0x40)
2419: #define CAN_ESR_LEC ((uint8_t)0x70)
2420:
2421: /* CAN Error Status Register bits */
2422: #define CAN_EIER_EWGIE ((uint8_t)0x01)
2423: #define CAN_EIER_EPVIE ((uint8_t)0x02)
2424: #define CAN_EIER_BOFIE ((uint8_t)0x04)
2425: #define CAN_EIER_LECIE ((uint8_t)0x10)
2426: #define CAN_EIER_ERRIE ((uint8_t)0x80)
2427:
2428: /* CAN transmit error counter Register bits(CAN_TECR) */
2429: #define CAN_TECR_TEC0 ((uint8_t)0x01)
2430: #define CAN_TECR_TEC1 ((uint8_t)0x02)
2431: #define CAN_TECR_TEC2 ((uint8_t)0x04)
2432: #define CAN_TECR_TEC3 ((uint8_t)0x08)
2433: #define CAN_TECR_TEC4 ((uint8_t)0x10)
2434: #define CAN_TECR_TEC5 ((uint8_t)0x20)
2435: #define CAN_TECR_TEC6 ((uint8_t)0x40)
2436: #define CAN_TECR_TEC7 ((uint8_t)0x80)
2437:
2438: /* CAN RECEIVE error counter Register bits(CAN_TECR) */
2439: #define CAN_RECR_REC0 ((uint8_t)0x01)
2440: #define CAN_RECR_REC1 ((uint8_t)0x02)
2441: #define CAN_RECR_REC2 ((uint8_t)0x04)
2442: #define CAN_RECR_REC3 ((uint8_t)0x08)
2443: #define CAN_RECR_REC4 ((uint8_t)0x10)
2444: #define CAN_RECR_REC5 ((uint8_t)0x20)
2445: #define CAN_RECR_REC6 ((uint8_t)0x40)
2446: #define CAN_RECR_REC7 ((uint8_t)0x80)
2447:
2448: /* CAN filter mode register bits (CAN_FMR) */
2449: #define CAN_FMR1_FML0 ((uint8_t)0x01)
2450: #define CAN_FMR1_FMH0 ((uint8_t)0x02)
2451: #define CAN_FMR1_FML1 ((uint8_t)0x04)
2452: #define CAN_FMR1_FMH1 ((uint8_t)0x08)
2453: #define CAN_FMR1_FML2 ((uint8_t)0x10)
2454: #define CAN_FMR1_FMH2 ((uint8_t)0x20)
2455: #define CAN_FMR1_FML3 ((uint8_t)0x40)
2456: #define CAN_FMR1_FMH3 ((uint8_t)0x80)
2457:
2458: #define CAN_FMR2_FML4 ((uint8_t)0x01)

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2459: #define CAN_FMR2_FMH4 ((uint8_t)0x02)

2460: #define CAN_FMR2_FML5 ((uint8_t)0x04)
2461: #define CAN_FMR2_FMH5 ((uint8_t)0x08)
2462:
2463: /* CAN filter Config register bits (CAN_FCR) */
2464: #define CAN_FCR1_FACT0 ((uint8_t)0x01)
2465: #define CAN_FCR1_FACT1 ((uint8_t)0x10)
2466: #define CAN_FCR2_FACT2 ((uint8_t)0x01)
2467: #define CAN_FCR2_FACT3 ((uint8_t)0x10)
2468: #define CAN_FCR3_FACT4 ((uint8_t)0x01)
2469: #define CAN_FCR3_FACT5 ((uint8_t)0x10)
2470:
2471: #define CAN_FCR1_FSC00 ((uint8_t)0x02)
2472: #define CAN_FCR1_FSC01 ((uint8_t)0x04)
2473: #define CAN_FCR1_FSC10 ((uint8_t)0x20)
2474: #define CAN_FCR1_FSC11 ((uint8_t)0x40)
2475: #define CAN_FCR2_FSC20 ((uint8_t)0x02)
2476: #define CAN_FCR2_FSC21 ((uint8_t)0x04)
2477: #define CAN_FCR2_FSC30 ((uint8_t)0x20)
2478: #define CAN_FCR2_FSC31 ((uint8_t)0x40)
2479: #define CAN_FCR3_FSC40 ((uint8_t)0x02)
2480: #define CAN_FCR3_FSC41 ((uint8_t)0x04)
2481: #define CAN_FCR3_FSC50 ((uint8_t)0x20)
2482: #define CAN_FCR3_FSC51 ((uint8_t)0x40)
2483:
2484: /**
2485: * @}
2486: */
2487:
2488: /** @addtogroup CAN_Registers_Reset_Value
2489: * @{
2490: */
2491: #define CAN_MCR_RESET_VALUE ((uint8_t)0x02)
2492: #define CAN_MSR_RESET_VALUE ((uint8_t)0x02)
2493: #define CAN_TSR_RESET_VALUE ((uint8_t)0x00)
2494: #define CAN_TPR_RESET_VALUE ((uint8_t)0x0C)
2495: #define CAN_RFR_RESET_VALUE ((uint8_t)0x00)
2496: #define CAN_IER_RESET_VALUE ((uint8_t)0x00)
2497: #define CAN_DGR_RESET_VALUE ((uint8_t)0x0C)
2498: #define CAN_PSR_RESET_VALUE ((uint8_t)0x00)
2499:
2500: #define CAN_ESR_RESET_VALUE ((uint8_t)0x00)
2501: #define CAN_EIER_RESET_VALUE ((uint8_t)0x00)
2502: #define CAN_TECR_RESET_VALUE ((uint8_t)0x00)
2503: #define CAN_RECR_RESET_VALUE ((uint8_t)0x00)
2504: #define CAN_BTR1_RESET_VALUE ((uint8_t)0x40)
2505: #define CAN_BTR2_RESET_VALUE ((uint8_t)0x23)
2506: #define CAN_FMR1_RESET_VALUE ((uint8_t)0x00)
2507: #define CAN_FMR2_RESET_VALUE ((uint8_t)0x00)
2508: #define CAN_FCR_RESET_VALUE ((uint8_t)0x00)
2509:
2510: #define CAN_MFMI_RESET_VALUE ((uint8_t)0x00)
2511: #define CAN_MDLC_RESET_VALUE ((uint8_t)0x00)
2512: #define CAN_MCSR_RESET_VALUE ((uint8_t)0x00)
2513:
2514: /**
2515: * @}
2516: */
2517:
2518: /**

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2519: * @brief Configuration Registers (CFG)

2520: */
2521:
2522: typedef struct CFG_struct
2523: {
2524: __IO uint8_t GCR; /*!< Global Configuration register */
2525: }
2526: CFG_TypeDef;
2527:
2528: /** @addtogroup CFG_Registers_Reset_Value
2529: * @{
2530: */
2531:
2532: #define CFG_GCR_RESET_VALUE ((uint8_t)0x00)
2533:
2534: /**
2535: * @}
2536: */
2537:
2538: /** @addtogroup CFG_Registers_Bits_Definition
2539: * @{
2540: */
2541:
2542: #define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */
2543: #define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */
2544:
2545: /**
2546: * @}
2547: */
2548:
2549: /******************************************************************************/
2550: /* Peripherals Base Address */
2551: /******************************************************************************/
2552:
2553: /** @addtogroup MAP_FILE_Base_Addresses
2554: * @{
2555: */
2556: #define OPT_BaseAddress 0x4800
2557: #define GPIOA_BaseAddress 0x5000
2558: #define GPIOB_BaseAddress 0x5005
2559: #define GPIOC_BaseAddress 0x500A
2560: #define GPIOD_BaseAddress 0x500F
2561: #define GPIOE_BaseAddress 0x5014
2562: #define GPIOF_BaseAddress 0x5019
2563: #define GPIOG_BaseAddress 0x501E
2564: #define GPIOH_BaseAddress 0x5023
2565: #define GPIOI_BaseAddress 0x5028
2566: #define FLASH_BaseAddress 0x505A
2567: #define EXTI_BaseAddress 0x50A0
2568: #define RST_BaseAddress 0x50B3
2569: #define CLK_BaseAddress 0x50C0
2570: #define WWDG_BaseAddress 0x50D1
2571: #define IWDG_BaseAddress 0x50E0
2572: #define AWU_BaseAddress 0x50F0
2573: #define BEEP_BaseAddress 0x50F3
2574: #define SPI_BaseAddress 0x5200
2575: #define I2C_BaseAddress 0x5210
2576: #define UART1_BaseAddress 0x5230
2577: #define UART2_BaseAddress 0x5240
2578: #define UART3_BaseAddress 0x5240

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2579: #define UART4_BaseAddress 0x5230

2580: #define TIM1_BaseAddress 0x5250
2581: #define TIM2_BaseAddress 0x5300
2582: #define TIM3_BaseAddress 0x5320
2583: #define TIM4_BaseAddress 0x5340
2584: #define TIM5_BaseAddress 0x5300
2585: #define TIM6_BaseAddress 0x5340
2586: #define ADC1_BaseAddress 0x53E0
2587: #define ADC2_BaseAddress 0x5400
2588: #define CAN_BaseAddress 0x5420
2589: #define CFG_BaseAddress 0x7F60
2590: #define ITC_BaseAddress 0x7F70
2591: #define DM_BaseAddress 0x7F90
2592:
2593: /**
2594: * @}
2595: */
2596:
2597: /******************************************************************************/
2598: /* Peripherals declarations */
2599: /******************************************************************************/
2600:
2601: #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) ||
defined(STM8S003) || \
2602: defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) ||
defined(STM8AF622x)
2603: #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
2604: #endif /*
(STM8S105)||(STM8S103)||(STM8S005)||(STM8S003)||(STM8S001)||(STM8S903)||(STM8AF626x
2605:
2606: #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined
(STM8AF52Ax) || \
2607: defined (STM8AF62Ax)
2608: #define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)
2609: #endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */
2610:
2611: #define AWU ((AWU_TypeDef *) AWU_BaseAddress)
2612:
2613: #define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
2614:
2615: #if defined (STM8S208) || defined (STM8AF52Ax)
2616: #define CAN ((CAN_TypeDef *) CAN_BaseAddress)
2617: #endif /* (STM8S208) || (STM8AF52Ax) */
2618:
2619: #define CLK ((CLK_TypeDef *) CLK_BaseAddress)
2620:
2621: #define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
2622:
2623: #define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
2624:
2625: #define OPT ((OPT_TypeDef *) OPT_BaseAddress)
2626:
2627: #define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
2628:
2629: #define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
2630:
2631: #define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
2632:
2633: #define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
2634:

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2635: #define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)

2636:
2637: #define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
2638:
2639: #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) ||
defined(STM8S105) || \
2640: defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined
(STM8AF626x)
2641: #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
2642: #endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) ||
(STM8AF626x) */
2643:
2644: #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined
(STM8AF52Ax) || \
2645: defined (STM8AF62Ax)
2646: #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
2647: #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
2648: #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
2649:
2650: #define RST ((RST_TypeDef *) RST_BaseAddress)
2651:
2652: #define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
2653: #define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
2654:
2655: #define SPI ((SPI_TypeDef *) SPI_BaseAddress)
2656: #define I2C ((I2C_TypeDef *) I2C_BaseAddress)
2657:
2658: #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) ||
defined(STM8S103) || \
2659: defined(STM8S003) || defined(STM8S001) || defined(STM8S903) || defined
(STM8AF52Ax) || defined (STM8AF62Ax)
2660: #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
2661: #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S001) || (STM8S903) ||
(STM8AF52Ax) || (STM8AF62Ax) */
2662:
2663: #if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x)
2664: #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)
2665: #endif /* STM8S105 || STM8S005 || STM8AF626x */
2666:
2667: #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined
(STM8AF52Ax) || \
2668: defined (STM8AF62Ax)
2669: #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)
2670: #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */
2671:
2672: #if defined(STM8AF622x)
2673: #define UART4 ((UART4_TypeDef *) UART4_BaseAddress)
2674: #endif /* (STM8AF622x) */
2675:
2676: #define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
2677:
2678: #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) ||
defined(STM8S103) || \
2679: defined(STM8S003) || defined(STM8S001) || defined(STM8S105) ||
defined(STM8S005) || defined (STM8AF52Ax) || \
2680: defined (STM8AF62Ax) || defined (STM8AF626x)
2681: #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
2682: #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S001) || (STM8S105) ||
(STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
2683:

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2684: #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) ||

defined(STM8S105) || \
2685: defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined
(STM8AF626x)
2686: #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)
2687: #endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) ||
(STM8AF626x)*/
2688:
2689: #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) ||
defined(STM8S103) || \
2690: defined(STM8S003) || defined(STM8S001) || defined(STM8S105) ||
defined(STM8S005) || defined (STM8AF52Ax) || \
2691: defined (STM8AF62Ax) || defined (STM8AF626x)
2692: #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
2693: #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S001) || (STM8S105) ||
(STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/
2694:
2695: #if defined (STM8S903) || defined (STM8AF622x)
2696: #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)
2697: #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)
2698: #endif /* (STM8S903) || (STM8AF622x) */
2699:
2700: #define ITC ((ITC_TypeDef *) ITC_BaseAddress)
2701:
2702: #define CFG ((CFG_TypeDef *) CFG_BaseAddress)
2703:
2704: #define DM ((DM_TypeDef *) DM_BaseAddress)
2705:
2706:
2707: #ifdef USE_STDPERIPH_DRIVER
2708: #include "stm8s_conf.h"
2709: #endif
2710:
2711: /* Exported macro --------------------------------------------------------------*/
2712:
2713: /*============================== Interrupts ====================================*/
2714: #ifdef _RAISONANCE_
2715: #include <intrins.h>
2716: #define enableInterrupts() _rim_() /* enable interrupts */
2717: #define disableInterrupts() _sim_() /* disable interrupts */
2718: #define rim() _rim_() /* enable interrupts */
2719: #define sim() _sim_() /* disable interrupts */
2720: #define nop() _nop_() /* No Operation */
2721: #define trap() _trap_() /* Trap (soft IT) */
2722: #define wfi() _wfi_() /* Wait For Interrupt */
2723: #define halt() _halt_() /* Halt */
2724: #elif defined(_COSMIC_)
2725: #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
2726: #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */
2727: #define rim() {_asm("rim\n");} /* enable interrupts */
2728: #define sim() {_asm("sim\n");} /* disable interrupts */
2729: #define nop() {_asm("nop\n");} /* No Operation */
2730: #define trap() {_asm("trap\n");} /* Trap (soft IT) */
2731: #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */
2732: #define halt() {_asm("halt\n");} /* Halt */
2733: #else /*_IAR_*/
2734: #include <intrinsics.h>
2735: #define enableInterrupts() __enable_interrupt() /* enable interrupts */
2736: #define disableInterrupts() __disable_interrupt() /* disable interrupts */
2737: #define rim() __enable_interrupt() /* enable interrupts */

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2738: #define sim() __disable_interrupt() /* disable interrupts */

2739: #define nop() __no_operation() /* No Operation */
2740: #define trap() __trap() /* Trap (soft IT) */
2741: #define wfi() __wait_for_interrupt() /* Wait For Interrupt */
2742: #define halt() __halt() /* Halt */
2743: #endif /*_RAISONANCE_*/
2744:
2745: /*============================== Interrupt vector Handling
========================*/
2746:
2747: #ifdef _COSMIC_
2748: #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
2749: #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
2750: #endif /* _COSMIC_ */
2751:
2752: #ifdef _RAISONANCE_
2753: #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b
2754: #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap
2755: #endif /* _RAISONANCE_ */
2756:
2757: #ifdef _IAR_
2758: #define STRINGVECTOR(x) #x
2759: #define VECTOR_ID(x) STRINGVECTOR( vector = (x) )
2760: #define INTERRUPT_HANDLER( a, b ) \
2761: _Pragma( VECTOR_ID( (b)+2 ) ) \
2762: __interrupt void (a)( void )
2763: #define INTERRUPT_HANDLER_TRAP(a) \
2764: _Pragma( VECTOR_ID( 1 ) ) \
2765: __interrupt void (a) (void)
2766: #endif /* _IAR_ */
2767:
2768: /*============================== Interrupt Handler declaration
========================*/
2769: #ifdef _COSMIC_
2770: #define INTERRUPT @far @interrupt
2771: #elif defined(_IAR_)
2772: #define INTERRUPT __interrupt
2773: #endif /* _COSMIC_ */
2774:
2775: /*============================== Handling bits
====================================*/
2776: /*-----------------------------------------------------------------------------
2777: Method : I
2778: Description : Handle the bit from the character variables.
2779: Comments : The different parameters of commands are
2780: - VAR : Name of the character variable where the bit is located.
2781: - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
2782: - Value : Can be 0 (reset bit) or not 0 (set bit)
2783: The "MskBit" command allows to select some bits in a source
2784: variables and copy it in a destination var (return the value).
2785: The "ValBit" command returns the value of a bit in a char
2786: variable: the bit is reset if it returns 0 else the bit is set.
2787: This method generates not an optimised code yet.
2788: -----------------------------------------------------------------------------*/
2789: #define SetBit(VAR,Place) ( (VAR) |=
(uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
2790: #define ClrBit(VAR,Place) ( (VAR) &=
(uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
2791:
2792: #define ChgBit(VAR,Place) ( (VAR) ^=
(uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
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2793: #define AffBit(VAR,Place,Value) ((Value) ? \

2794: ((VAR) |= ((uint8_t)1<<(Place))) : \
2795: ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))
2796: #define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest))
2797:
2798: #define ValBit(VAR,Place) ((uint8_t)(VAR) &
(uint8_t)((uint8_t)1<<(uint8_t)(Place)))
2799:
2800: #define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!<
Returns the low byte of the 32-bit value */
2801: #define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!<
Returns the second byte of the 32-bit value */
2802: #define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!<
Returns the third byte of the 32-bit value */
2803: #define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!<
Returns the high byte of the 32-bit value */
2804:
2805: #define UNUSED(x) ((void)(x))
2806: /*============================== Assert Macros
====================================*/
2807: #define IS_STATE_VALUE_OK(SensitivityValue) \
2808: (((SensitivityValue) == ENABLE) || \
2809: ((SensitivityValue) == DISABLE))
2810:
2811: /*-----------------------------------------------------------------------------
2812: Method : II
2813: Description : Handle directly the bit.
2814: Comments : The idea is to handle directly with the bit name. For that, it is
2815: necessary to have RAM area descriptions (example: HW register...)
2816: and the following command line for each area.
2817: This method generates the most optimized code.
2818: -----------------------------------------------------------------------------*/
2819:
2820: #define AREA 0x00 /* The area of bits begins at address 0x10. */
2821:
2822: #define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
2823: #define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
2824: #define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
2825:
2826: /* Exported functions ------------------------------------------------------- */
2827:
2828: #endif /* __STM8S_H */
2829:
2830: /**
2831: * @}
2832: */
2833:
2834: /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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