ISO1050

SLLS983L – JUNE 2009 – REVISED OCTOBER 2023

ISO1050 Isolated CAN Transceiver

1 Features 3 Description
• Meets the requirements of ISO11898-2 The ISO1050 is a galvanically isolated CAN
• 5000-VRMS isolation (ISO1050DW) transceiver that meets the specifications of the
• 2500-VRMS isolation (ISO1050DUB) ISO11898-2 standard. The device has the logic input
• Fail-safe outputs and output buffers separated by a silicon oxide (SiO2)
• Low loop delay: 150 ns (typical), 210 ns insulation barrier that provides galvanic isolation of
(maximum) up to 5000 VRMS for ISO1050DW and 2500 VRMS
• 50-kV/μs typical transient immunity for ISO1050DUB. Used in conjunction with isolated
• Bus-fault protection of –27 V to 40 V power supplies, the device prevents noise currents on
• Driver (TXD) dominant time-out function a data bus or other circuits from entering the local
• I/O voltage range supports 3.3 V and 5 V ground and interfering with or damaging sensitive
microprocessors circuitry.
• Safety-related certifications
As a CAN transceiver, the device provides differential
– VDE approval per DIN EN IEC 60747-17 (VDE transmit capability to the bus and differential receive
0884-17) capability to a CAN controller at signaling rates up to
– UL 1577 approved 1 megabit per second (Mbps). The device is designed
– CSA approved for IEC 61010-1, IEC 60601-1 for operation in especially harsh environments, and it
– TUV Reinforced Insulation Approval for features cross-wire, overvoltage and loss of ground
EN/UL/CSA 62368-1 (ISO1050DW-Only) protection from –27 V to 40 V and overtemperature
– CQC reinforced insulation per GB4943.1 shutdown, as well as –12V to 12V common-mode
(ISO1050DW-only) range.
– Typical 25-year life at rated working voltage
(see application report SLLA197 and Life The ISO1050 is characterized for operation over the
Expectancy vs Working Voltage) ambient temperature range of –55°C to 105°C.

2 Applications Device Information(1)

PART NUMBER PACKAGE PACKAGE SIZE ((2))
• Industrial automation, control, sensors, and drive
SOP (8) 9.5 mm × 10.4 mm
systems ISO1050
• Building and climate control (HVAC) automation SOIC (16) 10.3 mm × 10.3 mm
• Security systems (1) For all available packages, see the orderable addendum at
• Transportation the end of the data sheet.
• Medical (2) The package size (length × width) is a nominal value and
• Telecom includes pins, where applicable.
• CAN bus standards such as CANopen, DeviceNet,
NMEA2000, ARINC825, ISO11783, CAN Kingdom,
CANaerospace
CANH
Isolation Capacitor

RXD
CANL

TXD

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1050
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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagram......................................... 19
2 Applications..................................................................... 1 8.3 Feature Description...................................................19
3 Description.......................................................................1 8.4 Device Functional Modes..........................................22
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 24
5 Pin Configuration and Functions...................................5 9.1 Application Information............................................. 24
6 Specifications.................................................................. 6 9.2 Typical Application.................................................... 24
6.1 Absolute Maximum Ratings........................................ 6 10 Power Supply Recommendations..............................27
6.2 ESD Ratings............................................................... 6 10.1 General Recommendations.................................... 27
6.3 Recommended Operating Conditions.........................6 10.2 Power Supply Discharging......................................27
6.4 Thermal Information....................................................7 11 Layout........................................................................... 28
6.5 Power Ratings.............................................................7 11.1 Layout Guidelines................................................... 28
6.6 Insulation Specifications............................................. 8 11.2 Layout Example...................................................... 28
6.7 Safety-Related Certifications...................................... 9 12 Device and Documentation Support..........................29
6.8 Safety Limiting Values.................................................9 12.1 Documentation Support.......................................... 29
6.9 Electrical Characteristics - DC Specification.............10 12.2 Receiving Notification of Documentation Updates..29
6.10 Switching Characteristics........................................12 12.3 Support Resources................................................. 29
6.11 Insulation Characteristics Curves............................12 12.4 Trademarks............................................................. 29
6.12 Typical Characteristics............................................ 13 12.5 Electrostatic Discharge Caution..............................29
7 Parameter Measurement Information.......................... 14 12.6 Glossary..................................................................29
8 Detailed Description......................................................19 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 19 Information.................................................................... 29

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (August 2023) to Revision L (October 2023) Page
• Updated Safety Related Certifications section .................................................................................................. 6
• Updated multiple Specifiaction sections ............................................................................................................ 6

Changes from Revision J (September 2019) to Revision K (August 2023) Page

• Changed VDE standard name to DIN EN IEC 60747-17 (VDE 0884-17), updated CSA standard to CSA
62368-1 and IEC 62368-1.................................................................................................................................. 1
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1

Changes from Revision I (September 2014) to Revision J (September 2019) Page

• Changed VDE standard name From: DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 To: DIN VDE V
0884-11:2017-01 in Section 1 ............................................................................................................................1
• Deleted 'Component Acceptance Notice 5 A' from CSA bullet in Section 1 ......................................................1
• Changed inverting output label From: CANH To: CANL in Figure 7-10 ...........................................................14
• Changed VDE standard name From: DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 To: DIN VDE V
0884-11:2017-01 in INSULATION CHARACTERISTICS table.........................................................................19
• Changed VISO PARAMETER description From: 'ISO1050DUB - Double Protection' To: 'ISO1050DUB - Single
Protection' in INSULATION CHARACTERISTICS table................................................................................... 19
• Updated Regulatory Information in REGULATORY INFORMATION table....................................................... 19
• Changed UL 1577 rating for ISO1050DUB From: '2500 VRMS Double Protection' To: '2500 VRMS Single
Protection' in REGULATORY INFORMATION table......................................................................................... 19
• Deleted UL 1577 'Double Protection' rating of 3500 VRMS for ISO1050DW in REGULATORY
INFORMATION table........................................................................................................................................ 19
• Added Section 10.2 section and SN6505 reference to Section 10 ..................................................................27
• Added SN6505x data sheet link to 'Transformer Driver for Isolated Power Supplies' in Section 12.1 section.....
..........................................................................................................................................................................29

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Changes from Revision H (June 2013) to Revision I (September 2014) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1

Changes from Revision G (March 2013) to Revision H (June 2013) Page

• Changed title From: LIFE EXPECTANCY vs WORKING VOLTAGE (ISO1050DW To: LIFE EXPECTANCY vs
WORKING VOLTAGE (ISO1050DUB)..............................................................................................................22

Changes from Revision F (January 2013) to Revision G (March 2013) Page

• Clarified clearance and creepage measurement method in ISOLATOR CHARACTERISTICS....................... 19
• Clarified test methods for voltage ratings in INSULATION CHARACTERISTICS............................................ 19
• Changed UL Single Protection Certification pending to Single Protection in REGULATORY INFORMATION
SECTION (certificate available)........................................................................................................................19

Changes from Revision E (December 2011) to Revision F (January 2013) Page

• Deleted ISO1050L device...................................................................................................................................1
• Deleted ISO1050LDW from Features list........................................................................................................... 1
• Deleted ISO1050LDW in first paragraph of DESCRIPTION.............................................................................. 1
• Added the PIN FUNCTIONS section.................................................................................................................. 5
• Added Maximum impulse voltage (VIMP) specification per DIN EN IEC 60747-17 (VDE 0884-17) ...................8
• Deleted ISO1050LDW from INSULATION CHARACTERISTICS.....................................................................19
• Deleted ISO1050LDW from REGULATORY INFORMATION...........................................................................19
• Added the FUNCTIONAL DESCRIPTION section........................................................................................... 19
• Deleted ISO1050LDW from LIFE EXPECTANCY vs WORKING VOLTAGE ...................................................22
• Deleted 40V from the CANH and CANL input diagrams and output diagrams in the EQUIVALENT I/O
SCHEMATICS ..................................................................................................................................................22
• Changed the APPLICATION INFORMATION section...................................................................................... 24
• Changed the BUS LOADING, LENGTH AND NUMBER OF NODES section..................................................24
• Added the CAN TERMINATION section...........................................................................................................25

Changes from Revision D (June 2011) to Revision E (November 2011) Page

• Added device ISO1050L.....................................................................................................................................1
• Changed (DW Package) in the Features list to (ISO1050DW)...........................................................................1
• Changed (DUB Package) in the Features list to (ISO1050DUB and ISO1050LDW)......................................... 1
• Deleted IEC 60950-1 from the CSA Approvals Feature bullet........................................................................... 1
• From: IEC 60601-1 (Medical) and CSA Approvals Pending To: IEC 60601-1 (Medical) and CSA Approved ... 1
• Added Feature - 5 KVRMS Reinforced.............................................................................................................. 1
• Changed DW Package to ISO105DW and DUB package to ISO1050DUB and ISO1050LDW in the first
paragraph of DESCRIPTION..............................................................................................................................1
• Added Note 1 to the INSULATION CHARACTERISTICS table........................................................................19
• Changed VIORM From: 8-DUB Package to ISO1050DUB and ISO1050LDW ..................................................19
• Changed VIORM From: 16-DW to ISO1050DW ................................................................................................ 19
• Changed the VISO Isolation voltage per UL section of the INSULATION CHARACTERISTICS table..............19
• Changed the IEC 60664-1 Ratings Table......................................................................................................... 19
• Changed the REGULATORY INFORMATION table......................................................................................... 19
• Changed From: File Number: 220991 (Approval Pending) To: File Number: 220991...................................... 19
• Changed in note (1) 3000 to 2500 and 6000 to 5000....................................................................................... 19
• Changed in LIFE EXPECTANCY vs WORKING VOLTAGE (8-DUB PACKAGE TO: LIFE.....(ISO1050DW and
ISO1050LDW).................................................................................................................................................. 22

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Changes from Revision C (July 2010) to Revision D (June 2011) Page

• Changed the REGULATORY INFORMATION table......................................................................................... 19

Changes from Revision B (June 2010) to Revision C (July 2010) Page

• Changed the IEC 60747-5-2 Features bullet From: DW package Approval Pending To: VDE approved for
both DUB and DW packages..............................................................................................................................1
• Changed the Minimum Internal Gap value from 0.008 to 0.014 in the Isolator Characteristics table...............19
• Changed VIORM Specification From: 1300 To: 1200 per VDE certification....................................................... 19
• Changed VPR Specification From 2438 To: 2250............................................................................................. 19
• Added the Bus Loading paragraph to the Application Information section....................................................... 24

Changes from Revision A (Sept 2009) to Revision B (June 2010) Page

• Added information that IEC 60747-5-2 and IEC61010-1 have been approved.................................................. 1
• Changed DW package from preview to production data.................................................................................... 5
• Added Insulation Characteristics and IEC 60664-1 Ratings tables.................................................................. 19
• Added IEC file number......................................................................................................................................19

Changes from Revision * (June 2009) to Revision A (Sept 2009) Page

• Added Typical 25-Year Life at Rated Working Voltage to Features....................................................................1
• Added LIFE EXPECTANCY vs WORKING VOLTAGE section.........................................................................22

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5 Pin Configuration and Functions

Figure 5-2. 8-Pin DUB Package Top View

Figure 5-1. 16-Pin DW Package Top View

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME DW DUB
VCC1 1 1 Supply Digital-side supply voltage (3 to 5.5 V)
GND1 2 — Ground Digital-side ground connection
RXD 3 2 O CAN receive data output (LOW for dominant and HIGH for recessive bus states)
NC 4 — NC No connect
NC 5 — NC No connect
TXD 6 3 I CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
GND1 7 4 Ground Digital-side ground connection
GND1 8 — Ground Digital-side ground connection
GND2 9 5 Ground Transceiver-side ground connection
GND2 10 — Ground Transceiver-side ground connection
NC 11 — NC No connect
CANL 12 6 I/O Low-level CAN bus line
CANH 13 7 I/O High-level CAN bus line
NC 14 — NC No connect
GND2 15 — Ground Transceiver-side ground connection
VCC2 16 8 Supply Transceiver-side supply voltage (5 V)

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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VCC1 Supply voltage, side 1 -0.5 6 V
VCC2 Supply voltage, side 2 -0.5 6 V
VIO Logic input voltage range (TXD) -0.5 VCC1+0.5(3) V
VBUS Voltage on bus pins (CANH, CANL) -27 40 V
IO Output current on RXD pin -15 15 mA
TJ Junction temperature -55 150 ℃
TSTG Storage temperature -65 150 ℃

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
Electrostatic discharge
V(ESD) Human body model (HBM), per ANSI/ All pins(1) ±4000 V
ESDA/JEDEC JS-001
Electrostatic discharge
V(ESD) Charged device model (CDM), per All pins(2) ±1500 V
JEDEC specification JESD22-C101
Electrostatic discharge
V(ESD) Charged machine model, ANSI/ All pins(2) ±200 V
ESDS5.2-1996

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN TYP MAX UNIT
VCC1 Supply Voltage, Side 1 3 5.5 V
VCC2 Supply Voltage, Side 2 4.75 5.25 V
VI or VIC Voltage at bus pins (separately or common mode) -12 12 V
VIH High-level input voltage (TXD) 2 5.25 V
VIL Low-level input voltage (TXD) 0 0.8 V
VID Differential input voltage -7 7 V
IOH High-Level Output current, Driver -70 mA
IOH High-Level Output current, Receiver -4 mA
IOL Low-level output current, Driver 70 mA
IOL Low-level output current, Receiver 4 mA
TA Operating ambient temperature -55 105 °C
TJ Junction temperature -55 125 °C
TJshutdown Thermal shutdown temperature 190 °C

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6.4 Thermal Information

ISO1050
THERMAL METRIC(1) DW DUB UNIT
16 PINS 8 PINS
RΘJA Junction-to-ambient thermal resistance 76.4 84.3 °C/W
RΘJC(top) Junction-to-case (top) thermal resistance 41 63.2 °C/W
RΘJB Junction-to-board thermal resistance 47.7 43 °C/W
ΨJT Junction-to-top characterization parameter 17.2 27.4 °C/W
ΨJB Junction-to-board characterization parameter 38.2 42.7 °C/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC1 = VCC2 = 5.25 V, TJ = 150°C, RL =
60 Ω
PD Maximum power dissipation (both sides) 200 mW
TXD with 5V, 500kHz 50% duty square
wave
VCC1 = VCC2 = 5.25 V, TJ = 150°C, RL =
PD1 Maximum power dissipation (side-1) 60 Ω , TXD with 5V, 500kHz 50% duty 25 mW
square wave
VCC1 = VCC2 = 5.25 V, TJ = 150°C, RL =
60 Ω
PD2 Maximum power dissipation (side-2) 175 mW
TXD with 5V, 500kHz 50% duty square
wave

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6.6 Insulation Specifications

SPECIFICATIONS
PARAMETER TEST CONDITIONS UNIT
DUB-8 DW-16
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air >6.1 >8 mm
Side 1 to side 2 distance across package
CPG External Creepage(1) >6.8 >8 mm
surface
DTI Distance through the insulation Minimum internal gap (internal clearance) >13.5 >13.5 µm
CTI Comparative tracking index IEC 60112; UL 746A >600 >600 V
Material Group According to IEC 60664-1 I I
Rated mains voltage ≤ 150 VRMS I-IV I-IV
Rated mains voltage ≤ 300 VRMS I-III I-III
Overvoltage category
Rated mains voltage ≤ 600 VRMS n/a I-II
Rated mains voltage ≤ 848 VRMS n/a I
DIN V VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 560 1200 VPK
AC voltage (sine wave); time-dependent
395 848 VRMS
VIOWM Maximum isolation working voltage dielectric breakdown (TDDB) test;
DC voltage 560 1200 VDC
VTEST = VIOTM , t = 60 s (qualification); VTEST
VIOTM Maximum transient isolation voltage 4000 4000 VPK
= 1.2 × VIOTM, t = 1 s (100% production)
Test method per IEC 62368-1, 1.2/50 µs
VIOSM Maximum surge isolation voltage(3) waveform, VTEST = 1.6 x VIOSM = 6.4 kVPK 4000 4000 VPK
(qualification)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , ≤5 ≤5
tm = 10 s
Method a: After environmental tests subgroup
qpd Apparent charge(4) 1, Vini = VIOTM, tini = 60 s; ≤5 ≤5 pC
Vpd(m) = 1.3 × VIORM , tm = 10 s
Method b: At routine test (100%
production) Vini = 1.2 x VIOTM, tini = 1 s; ≤5 ≤5
Vpd(m) = 1.5 x VIORM, tm = 1 s
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1 MHz 1 1 pF
VIO = 500 V, TA = 25°C > 1012 > 1012
RIO Insulation resistance, input to output(5) VIO = 500 V, 100°C ≤ TA ≤ 150°C > 1011 > 1011 Ω
VIO = 500 V at TS = 150°C > 109 > 109
Pollution degree 2 2
40/125/ 40/125/
Climatic category
21 21
UL 1577
VTEST = VISO , t = 60 s (qualification); VTEST =
VISO Withstand isolation voltage 2500 4243 VRMS
1.2 × VISO , t = 1 s (100% production)

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
(2) ISO1044 is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

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(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

VDE CSA UL CQC TUV
Certified according to DIN Certified according to
Certified according to IEC Certified according to Certified according to EN
EN IEC 60747-17 (VDE UL 1577 Component
60950-1 and IEC 62368-1 GB4943.1-2011 61010-1 and EN 62368-1
0884-17) Recognition Program
ISO1050DW:
ISO1050DW:
5000 VRMS Reinforced
5000 VRMS Reinforced
Insulation
Insulation,
Working voltage of 380
400 VRMS maximum
VRMS per
working
IEC 60950-1 2nd
voltage
Ed.+A1+A2 and
5000 VRMS Basic
IEC 62368-1:2014
Basic Insulation Insulation,
Working voltage of 300
Transient Overvoltage, 600 VRMS maximum
VRMS per ISO1050DW:
4000 VPK ISO1050DUB: 2500 VRMS working
IEC 61010-1 3rd Ed. Reinforced Insulation,
Surge Voltage, 4000 VPK Single Protection voltage
ISO1050DUB: Altitude ≤ 5000 m, Tropical
Maximum Working ISO1050DW: 4243 VRMS ISO1050DUB:
2500 VRMS Basic Climate, 250 VRMS
Voltage, 1200 VPK Single Protection 2500 VRMS Reinforced
Insulation maximum working voltage
(ISO1050DW) and Insulation,
Working voltage of 700
560 VPK (ISO1050DUB) 400 VRMS maximum
VRMS per
working
IEC 60950-1 2nd
voltage
Ed.+A1+A2
2500 VRMS Basic
Working voltage of 600
Insulation,
VRMS per
600 VRMS maximum
IEC 61010-1 3rd Ed. and
working
IEC
voltage
62368-1:2014
Certificate number: Master contract number: Certificate number:
Client ID number: 77311 File number: E181974
40047657 220991 CQC14001109541

6.8 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DUB-8 PACKAGE
RθJA = 84.3°C/W, VI = 5.5 V, TJ = 150°C,
IS Safety input, output, or supply current 269 mA
TA = 25°C. see Figure 6-1
RθJA = 84.3°C/W, VI = 3.6 V, TJ = 150°C,
IS Safety input, output, or supply current 411 mA
TA = 25°C. Figure 6-1
TS Maximum safety temperature 150 °C
DW-16 Package
RθJA = 76.4°C/W, VI = 5.5 V, TJ = 150°C,
IS Safety input, output, or supply current 297 mA
TA = 25°C. Figure 6-2
RθJA = 76.4°C/W, VI = 3.6 V, TJ = 150°C,
IS Safety input, output, or supply current 454 mA
TA = 25°C. Figure 6-2
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.

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6.9 Electrical Characteristics - DC Specification

Typical specifications are at VCC1 = 3.3V, VCC2 = 5V, Min/Max are over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CHARACTERISTICS
ICC1 Supply current Side 1 VI = 0 V or VCC1, VCC1 = 3.3 V 1.8 3.6 mA
ICC1 Supply current Side 1 VI = 0 V or VCC1, VCC1 = 5.0 V 2.3 3.6 mA
ICC2 Supply current Side 2 VI = 0 V, bus dominant, RL = 60 Ω 52 73 mA
ICC2 Supply current Side 2 VI = VCC1 8 12 mA
DRIVER ELECTRICAL CHARACTERISTICS
See Figure 7-1 and Figure 7-2, VI = 0 V,
Bus output voltage(Dominant), CANH 2.9 3.5 4.5 V
RL = 60 Ω
VO(DOM)
See Figure 7-1 and Figure 7-2, VI = 0 V,
Bus output voltage(Dominant), CANL 0.8 1.2 1.78 V
RL = 60 Ω
Bus output voltage(recessive), CANH and See Figure 7-1 and Figure 7-2, VI = 2 V,
VO(REC) 2.0 2.3 3.0 V
CANL RL = 60 Ω
See Figure 7-1 and Figure 7-2, VI = 0 V,
1.5 3.0 V
RL = 60 Ω
VOD(DOM) Differential output voltage(dominant)
See Figure 7-1 and Figure 7-2, VI = 0 V,
1.4 3.0 V
RL = 45 Ω, VCC > 4.8 V
See Figure 7-1 and Figure 7-2, VI = 3 V,
-120.0 12.0 mV
VOD(REC) Differential output voltage(recessive) RL = 60 Ω
VI = 3 V, No Load -500.0 50.0 mV
Common-mode output voltage
VOC(DOM) See Figure 7-8 2 2.3 3.0 V
(Dominant)
Peak-to-peak common-mode output
VOC(pp) See Figure 7-8 0.3 V
voltage
IIH High level input leakage current VI = 2 V 5 uA
IIL Low level input leakage current VI = 0.8 V -5 uA
IO(off) Power-off TXD leakage current VCC1, VCC2 at 0 V, TXD = 5 V 10 uA
See Figure 7-11, CANH = –12 V, CANL
-105 -72 mA
Open
See Figure 7-11, VCANH = 12 V, CANL
0.36 6.2 mA
Short circuit current steady state output Open
IOS(ss)
current, dominant See Figure 7-11, VCANL =–12 V, CANH
-1 -0.5 mA
Open
See Figure 7-11, VCANL = 12 V, CANH
71 105 mA
Open
CMTI Common-mode transient immunity See Figure 7-13, VI = VCC or 0 V 25 50 kV/us
RECEIVER ELECTRICAL CHARACTERISTICS
VIT+ Positive-going bus input threshold voltage 750 900.0 mV
Negative-going bus input threshold See Table 1
VIT- 500.0 650 mV
voltage
Hysteresis voltage for differential input
VHYS 150 mV
threshold
IO = -4 mA, See Figure 7-6 Vcc - 0.8 4.6 V
VOH High level output voltage with Vcc = 5 V
IO = -20 uA, See Figure 7-6 Vcc - 0.1 5 V

High level output voltage with Vcc1 = 3.3 IO = 4 mA, See Figure 7-6 Vcc - 0.8 3.1 V
VOH
V IO = 20 uA, See Figure 7-6 Vcc - 0.1 3.3 V
IO = 4 mA, See Figure 7-6 0.2 0.4 V
VOL Low level output voltage
IO = 20 uA, See Figure 7-6 0 0.1 V

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Typical specifications are at VCC1 = 3.3V, VCC2 = 5V, Min/Max are over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input capacitance to ground (CANH or
CI TXD = 3 V, VI = 0.4 sin (4e6pi*t) + 2.5 V 12 pF
CANL)
CID Differential input capacitance TXD = 3 V, VI = 0.4 sin (4e6pi*t) 8 pF
RID Differential input resistance TXD = 3 V 40 90 kΩ
RIN Input resistance (CANH or CANL) TXD = 3 V 20 45 kΩ
Input resistance matching: (1 - RIN(CANH)/
RIN(M) VCANH = VCANL -3 3 %
RIN(CANL)) x 100%
CMTI Common-mode transient immunity See Figure 7-13, VI = VCC or 0 V 25 50 kV/us

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6.10 Switching Characteristics

Typical specifications are at VCC1 = 3.3V, VCC2 = 5V, Min/Max are over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOO Total loop delay, driver input TXD to
See Figure 7-9 100 150 210 ns
P1) receiver RXD, recessive to dominant
tPROP(LOO Total loop delay, driver input TXD to
See Figure 7-9 112 150 210 ns
P2) receiver RXD, dominant to recessive
DRIVER SWITCHING CHARACTERISTICS
Propagation delay time, recessive-to-
tPLH 74 110
dominant output
Propagation delay time, dominant-to-
tPHL See Figure 7-4 82 110 ns
recessive output
tR Differential output signal rise time 20 50
tF Differential output signal fall time 52 63
tTXD_DTO Dominant time out CL = 100 pF, See Figure 7-10 1.2 4 ms
RECEIVER SWITCHING CHARACTERISTICS
Propagation delay time, low-to-high-level
tPLH 66 90 130 ns
output
Propagation delay time, high-to-low-level
tPHL TXD at 3 V, See Figure 7-6 51 80 105 ns
output
tR Output signal rise time(RXD) 3 6 ns
tF Output signal fall time(RXD) 3 6 ns
Fail-Safe output delay time from bus-side
tfs VCC1 at 5 V, See Figure 7-12 6 us
power loss

6.11 Insulation Characteristics Curves

500
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Current (mA)

400

300

200

100

0
0 50 100 150 200
Case Temperature (°C)

Figure 6-1. DUB-8 Thermal Derating Curve per VDE Figure 6-2. DW-16 Thermal Derating Curve per VDE

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6.12 Typical Characteristics

150 175
VCC1 = 3V, VCC2 = 4.75V VCC1 = 3V, VCC2 = 4.75V
145 VCC1 = 5V, VCC2 = 5V 170 VCC1 = 5V, VCC2 = 5V
VCC1 = 5.5V, VCC2 = 5.25V VCC1 = 5.5V, VCC2 = 5.25V

140 165
Loop Time - ns

Loop Time - ns
135 160

130 155

125 150

120 145

115 140
-60 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120
TA - Free-Air Temperature - C TA - Free Air Temperature - C
Figure 6-3. Recessive-to-Dominant Loop Time vs Free-Air Figure 6-4. Dominant-to-Recessive Loop Time vs Free-Air
Temperature (Across Vcc) Temperature (Across Vcc)
100 5
70 ICC1 = 5V VO = CANH
ICC2 = 5V 4.5 VO = CANL
50
ICC1 = 3.3V
ICC - Supply Current - mA

30 4

VO - Output Voltage - V
20
3.5

10 3
7
5 2.5

3 2
2
1.5

1 1
250 350 450 550 650 750 850 950 -60 -40 -20 0 20 40 60 80 100 120
Signaling Rate - kbps TA - Free Air Temperature - C
Figure 6-5. Supply Current (RMS) vs Signaling Rate (kbps) Figure 6-6. Driver Output Voltage vs Free-Air Temperature

Figure 6-7. Emissions Spectrum to 10 MHz Figure 6-8. Emissions Spectrum to 50 MHz

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7 Parameter Measurement Information

IO(CANH)
CANH
II
0 or
Vcc1 VOD RL VO(CANH) + VO(CANL)
TXD CANL
2

GND1 GND2 IO(CANL) VOC

VI

VO(CANL ) VO(CANH)

GND1 GND2

Figure 7-1. Driver Voltage, Current and Test Definitions

Dominant
» 3.5 V VO (CANH)

Recessive
» 2.5 V

» 1.5 V VO (CANL)

Figure 7-2. Bus Logic State Voltage Definitions

330 W ±1%

CANH

TXD
0V VOD 60 W ±1%
CANL +
_ -2 V < V test < 7 V

GND2
330 W ±1%
Figure 7-3. Driver VOD With Common-Mode Loading Test Circuit

Vcc
CANH VI Vcc/2 Vcc/2
TXD 0V
60 W ±1% VO CL = 100 pF
CANL ± 20% t PLH t PHL
(SEE NOTE B) VO(D)
90%
VI 0.9V
VO
(SEE NOTE A)
0.5V
10%
tr tf VO(R)

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 7-4. Driver Test Circuit and Voltage Waveforms

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CANH
IO
VI(CANH) + VI(CANL) RXD
VIC = VID
2 CANL

VI(CANH)
VO
VI(CANL)

GND2 GND1

Figure 7-5. Receiver Voltage and Current Definitions

CANH
IO
3.5 V
RXD
V 2.4 V
I 2 V
CANL 1.5 V
t pLH t pHL
CL = 15 pF V OH
VI VO 90 %
± 20 % 0.7 Vcc 1
(SEE NOTE A) 1 .5 V (SEE NOTE B) V 0.3 Vcc 1
O 10 %
V OL
tr tf
GND 2 GND 1

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 7-6. Receiver Test Circuit and Voltage Waveforms

Table 7-1. Differential Input Voltage Threshold Test

INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L
12 V 11.1 V 900 mV L
VOL
–6 V –12 V 6V L
12 V 6V 6V L
–11.5 V –12 V 500 mV H
12 V 11.5 V 500 mV H
–12 V –6 V –6 V H VOH
6V 12 V –6 V H
Open Open X H

1 nF
CANH
RXD

CANL
15 pF

1 nF
TXD
+
VI
_
GND2 GND1

The waveforms of the applied transients are in accordance

with ISO 7637 part 1, test pulses 1, 2, 3a, and 3b.

Figure 7-7. Transient Overvoltage Test Circuit

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27 W ±1 %

CANH
TXD

CANL
V (CANH) + V (CANL)
47 nF V OC O O
VI =
27 W ±1 % ± 20% 2

GND 1 GND 2

V
OC(pp)

V
OC

Figure 7-8. Peak-to-Peak Output Voltage Test Circuit and Waveform

CANH

TXD
VI 60 W ±1% Vcc

TXD Input 50%

CANL
0V
tloop t loop1
2
VOH
RXD
RXD Output 50% 50%
+
VOL
15 pF ± 20%
VO
_ GND1

Figure 7-9. tLOOP Test Circuit and Voltage Waveforms

CANL

A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 7-10. Dominant Time-out Test Circuit and Voltage Waveforms

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I OS (P) IOS (SS)

I OS
15 s
CANH
TXD 0V
0 V or VCC 1 12 V

CANL VI -12 V or 12 V VI
0V
GND2
or 10 ms

0V
VI

-12 V

Figure 7-11. Driver Short-Circuit Current Test Circuit and Waveforms

VI
VCC 2
CANH
VCC2
TXD
0V CL 60 W ±1% 2.7 V
VI
0V
CANL t fs
VOH
VO 50%
RXD
VOL
+ NOTE: CL = 100pF
VO 15pF ± 20% includes instrumentation
and fixture capacitance
GND 1 within ± 20%.

Figure 7-12. Fail-Safe Delay Time Test Circuit and Voltage Waveforms

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C = 0.1 mF VCC 1 VCC2

2.0 V ± 1%
CANH C = 0.1 mF ±1%
GND1 GND2
TXD
60 W
S1 VOH or VOL

CANL
0.8 V

RXD

VOH or VOL 1 kW
GND 1 GND 2

CL = 15 pF
(includes probe and
jig capacitance)

V TEST

Figure 7-13. Common-Mode Transient Immunity Test Circuit

CANH Spectrum Analyzer

ISO1050
6.2 kW
30 W 47nF 10 nF

30 W
TXD
500kbps CANL 6.2 kW

Figure 7-14. Electromagnetic Emissions Measurement Setup

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8 Detailed Description
8.1 Overview
The ISO1050 is a digitally isolated CAN transceiver with a typical transient immunity of 50 kV/µs. The device can
operate from 3.3-V supply on side 1 and 5-V supply on side 2. This is of particular advantage for applications
operating in harsh industrial environments because the 3.3 V on side 1 enables the connection to low-volt
microcontrollers for power preservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the
bus signals.
8.2 Functional Block Diagram
VCC1 VCC2

CANH
RXD

GALVANIC ISOLATION
CANL

TXD

GND1 GND2

8.3 Feature Description

8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node will use the TXD pin to drive the bus and will receive data from
the bus on the RXD pin. See Figure 8-1 and Figure 8-2.
Normal & Silent Mode
Typical Bus Voltage (V)

4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1

Time, t
Recessive Dominant Recessive
Logic H Logic L Logic H

Figure 8-1. Bus States (Physical Bit Representation)

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CANH

ISOLATION
GALVANIC
VCC / 2 RXD

CANL

Figure 8-2. Simplified Recessive Common Mode Bias and Receiver

8.3.2 Digital Inputs and Outputs

TXD (Input) and RXD (Output):
VCC1 for the isolated digital input and output side of the device maybe supplied by a 3.3-V or 5-V supply and thus
the digital inputs and outputs are 3.3-V and 5-V compatible.

Note
TXD is very weakly internally pulled up to VCC1. An external pullup resistor should be used to make
sure that TXD is biased to recessive (high) level to avoid issues on the bus if the microprocessor
doesn't control the pin and TXD floats. TXD pullup strength and CAN bit timing require special
consideration when the device is used with an open-drain TXD output on the CAN controller of the
microprocessor. An adequate external pullup resistor must be used to ensure that the TXD output of
the microprocessor maintains adequate bit timing input to the input on the transceiver.

8.3.3 Protection Features

8.3.3.1 TXD Dominant Time-Out (DTO)
TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or
software failure where TXD is held dominant longer than the time-out period tTXD_DTO. The TXD DTO circuit
timer starts on a falling edge on TXD. The TXD DTO circuit disables the CAN bus driver if no rising edge is seen
before the time-out period expires. This frees the bus for communication between other nodes on the network.
The CAN driver is re-activated when a recessive signal is seen on the TXD pin, thus clearing the TXD DTO
condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level
during a TXD dominant time-out.

Note
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible
transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed
immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate.
Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / tTXD_DTO.

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TXD fault stuck dominant: example PCB failure or Fault is repaired and local node
TXD INPUT

bad software transmission capability restored

TXD

%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ

CAN BUS OUTPUT

Normal CAN
communication for the whole network but
WITH TXD DTO

communication
TXD DTO prevents this and frees the bus
for communication after the time tTXD_DTO.

CAN
Bus tTXD_DTO
Signal
Communication from other Communication from
network nodes repaired local node

Figure 8-3. Example Timing Diagram for Devices With TXD DTO

8.3.3.2 Thermal Shutdown

If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the
CAN driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when
the junction temperature drops below the thermal shutdown temperature of the device. If the fault condition is
still present, the temperature may rise again and the device would enter thermal shut down again. Prolonged
operation with thermal shutdown conditions may affect device reliability.

Note
During thermal shutdown the CAN bus drivers turn off; thus no transmission is possible from TXD to
the bus. The CAN bus pins are biased to recessive level during a thermal shutdown, and the receiver
to RXD path remains operational.

8.3.3.3 Undervoltage Lockout and Fail-Safe

The supply pins have undervoltage detection that places the device in protected or fail-safe mode. This protects
the bus during an undervoltage event on VCC1 or VCC2 supply pins. If the bus-side power supply VCC2 is
lower than about 4 V, the power shutdown circuits in the ISO1050 will disable the transceiver to prevent false
transmissions due to an unstable supply. If VCC1 is still active when this occurs, the receiver output (RXD) will go
to a fail-safe HIGH (recessive) value in about 6 microseconds.
Table 8-1. Undervoltage Lockout and Fail-Safe
VCC1 VCC2 DEVICE STATE BUS OUTPUT RXD
GOOD GOOD Functional Per Device State and TXD Mirrors Bus
BAD GOOD Protected Recessive High Impedance (3-state)
GOOD BAD Protected High Impedance Recessive (Fail-Safe High)

space

Note
After an undervoltage condition is cleared and the supplies have returned to valid levels, the device
typically resumes normal operation in 300 µs

8.3.3.4 Floating Pins

Pullups and pulldowns should be used on critical pins to place the device into known states if the pins float. The
TXD pin should be pulled up through a resistor to VCC1 to force a recessive input level if the microprocessor
output to the pin floats.

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8.3.3.5 CAN Bus Short-Circuit Current Limiting

The device has several protection features that limit the short-circuit current when a CAN bus line is shorted.
These include driver current limiting (dominant and recessive). The device has TXD dominant state time out
to prevent permanent higher short-circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states with the data and control fields bits,
thus the short-circuit current may be viewed either as the instantaneous current during each bus state, or as a
DC average current. For system current (power supply) and power considerations in the termination resistors
and common-mode choke ratings, use the average short-circuit current. Determine the ratio of dominant and
recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either
recessive or dominant at certain times:
• Control fields with set bits
• Bit-stuffing
• Interframe space
• TXD dominant time-out (fault case limiting)
These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.

Note
The short-circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short-circuit currents. The average short-circuit current may be calculated with the following
formula:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive ×
IOS(SS)_REC]
Where
• IOS(AVG) is the average short-circuit current.
• %Transmit is the percentage the node is transmitting CAN messages.
• %Receive is the percentage the node is receiving CAN messages.
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages.
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages.
• IOS(SS)_REC is the recessive steady state short-circuit current.
• IOS(SS)_DOM is the dominant steady state short-circuit current.

Note
Consider the short-circuit current and possible fault cases of the network when sizing the power
ratings of the termination resistance and other network components.

8.4 Device Functional Modes

Table 8-2. Driver Function Table
INPUT OUTPUTS
DRIVEN BUS STATE
TXD(1) CANH(1) CANL(1)
L H L Dominant
H Z Z Recessive

(1) H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See Figure 8-1 and
Figure 8-2 for bus state and common mode bias information.

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Table 8-3. Receiver Function Table

CAN DIFFERENTIAL INPUTS
DEVICE MODE BUS STATE RXD PIN(1)
VID = VCANH – VCANL
VID ≥ 0.9 V Dominant L
0.5 V < VID < 0.9 V ? ?
Normal or Silent
VID ≤ 0.5 V Recessive H
Open (VID ≈ 0 V) Open H

(1) H = high level, L = low level, ? = indeterminate.

Table 8-4. Function Table

DRIVER RECEIVER
INPUTS OUTPUTS DIFFERENTIAL INPUTS OUTPUT
BUS STATE VID = CANH–CANL RXD BUS STATE
TXD CANH CANL
L(1) H L DOMINANT VID ≥ 0.9 V L DOMINANT
H Z Z RECESSIVE 0.5 V < VID < 0.9 V ? ?
Open Z Z RECESSIVE VID ≤ 0.5 V H RECESSIVE
X Z Z RECESSIVE Open H RECESSIVE

(1) Logic low pulses to prevent dominant time-out.

TXD Input RXD Output

VCC1 VCC1 VCC1

VCC1

1 M
8
500  OUT
IN
13 

CANH and CANL Inputs CANH and CANL outputs

VCC2

VCC2/2

900

35 k CANH
Input
CANL

Figure 8-4. Equivalent I/O Schematics

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

ISO1050 can be used with other components from TI such as a microcontroller, a transformer driver, and a linear
voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
SN6501 TPS76350
4 8 1 5
GND2 D2 IN OUT
3 7 3
VCC EN
2 6
2 4
GND NC
1 5
GND1 D1

ISO1050
1 16
VCC1 VCC2
2
GND1
4 14
RXD NC
3 13
NC CANH
Vdd
5 12
RXD NC CANL
L1 3.3V
6 11 Optional Bus
TXD TXD NC
N MCU protection
PSU 7 15 function
GND1
PE 0V
8 9,10
GND1 GND2
DGND
ISO
Protective Chasis Galvanic Ground
Earth Ground Isolation
Digital Barrier
Ground

Figure 9-1. Application Circuit

9.2.1 Design Requirements

Unlike optocoupler-based solution, which needs several external components to improve performance, provide
bias, or limit current, ISO1050 only needs two external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as
the ISO1050.

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Many CAN organizations and standards have scaled the use of CAN for applications outside the original
ISO11898 standard. They have made system level trade offs for data rate, cable length, and parasitic loading
of the bus. Examples of some of these specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and
NMEA200.
A CAN network design is a series of tradeoffs, but these devices operate over wide –12-V to 12-V common-
mode range. In ISO11898-2 the driver differential output is specified with a 60-Ω load (the two 120-Ω termination
resistors in parallel) and the differential output must be greater than 1.5 V. The ISO1050 is specified to meet
the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential output of 1.4 V with a 45-Ω
load. The differential input resistance of the ISO1050 is a minimum of 30 kΩ. If 167 ISO1050 transceivers are
in parallel on a bus, this is equivalent to a 180-Ω differential load. That transceiver load of 180 Ω in parallel with
the 60 Ω gives a total 45 Ω. Therefore, the ISO1050 theoretically supports over 167 transceivers on a single
bus segment with margin to the 1.2-V minimum differential input at each node. However for CAN network design
margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances,
ground offsets and signal integrity thus a practical maximum number of nodes is typically much lower. Bus length
may also be extended beyond the original ISO11898 standard of 40 m by careful system design and data rate
tradeoffs. For example, CAN open network design guidelines allow the network to be up to 1km with changes in
the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the
responsibility of good network design.
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in
a node, but if nodes may be removed from the bus, the termination must be carefully placed so that it is not
removed from the bus.

Node n
Node 1 Node 2 Node 3 (with termination)
MCU or DSP
MCU or DSP MCU or DSP MCU or DSP

CAN
CAN CAN CAN Controller
Controller Controller Controller

CAN
CAN CAN CAN Transceiver
Transceiver Transceiver Transceiver
RTERM

RTERM

Figure 9-2. Typical CAN Bus

Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be
used. (See Figure 9-3). Split termination improves the electromagnetic emissions behavior of the network by
eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.

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Standard Termination Split Termination

CANH CANH

RTERM/2
CAN CAN
RTERM
Transceiver Transceiver
CSPLIT
RTERM/2

CANL CANL

Figure 9-3. CAN Bus Termination Concepts

9.2.3 Application Curve

100
Life Expectancy – Years

28 Years VIORM at 560 V

10
0 120 250 500 750 880 1000

VIORM – Working Voltage – V

G001

Figure 9-4. Life Expectancy vs Working Voltage (ISO1050DUB)

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10 Power Supply Recommendations

10.1 General Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-µF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side using Texas Instruments' SN6505 and SN6501 based power supply solution.
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6505 and SN6501 data sheets (SLLSEP9, SLLSEA0).
10.2 Power Supply Discharging
To ensure normal re-initialization time after a power down, the power supply for the ISO1050 needs to discharge
below 0.3 V, and as closely to 0 V as possible, to ensure that a communication delay does not occur. Figure 10-1
illustrates various scenarios of power-supply ramp-down and its effect on the communication delay.

Longer than normal re-initialization time Normal re-initialization time

VCC2 VCC2
5V 5V CAN H

Communication Delay

CAN H
2.5 V 2.5 V

1.3 V Brownout 1.3 V

Window Brownout
Window
0.3 V 0.3 V

Time Time
Normal re-initialization time Normal re-initialization time
VCC2 VCC2
5V CAN H 5V CAN H

2.5 V 2.5 V

1.3 V 1.3 V
Brownout Brownout
Window Window
0.3 V
0.3 V
Time Time

Figure 10-1. Power Supply Ramp-Down and Communication Delay Behavior

The brownout window, 0.3 V to 1.3 V (typical), represents the range of voltage in which a longer than normal re-
initialization time may occur if VCC2 powers up from this voltage. The ISO1042, an upgraded device with higher
isolation rating, CAN FD speeds of 5 Mbps, higher bus fault-protection voltage, stronger EMC performance, and
smaller package options does not exhibit this behavior. For all new isolated CAN designs, it is recommended to
use the ISO1042. If the ISO1050 must be used, ensure that VCC2 discharges to 0 V so that a longer than normal
re-initialization time does not exist. If the power supplies cannot be configured in such a way that VCC2 discharge
below 0.3 V on their own, implement a bleed resistor between VCC2 and GND2. The bleed resistor value should
be selected such that it ensures VCC2 goes below the brownout window fast enough for any power interruption
or power down sequence the system may permit. The lower the resistance, the faster VCC2 will discharge to 0V
with the tradeoff of consuming power. For many systems, a bleed resistor value of 2 KΩ is sufficient.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: ISO1050
ISO1050
SLLS983L – JUNE 2009 – REVISED OCTOBER 2023 www.ti.com

11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-
frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths
of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its
self-extinguishing flammability-characteristics.
11.2 Layout Example

High-speed traces
10 mils
Ground plane
Keep this
space free FR-4
40 mils from planes, 0r ~ 4.5
traces, pads,
and vias
Power plane
10 mils
Low-speed traces
Figure 11-1. Recommended Layer Stack

28 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISO1050

 ISO1050
www.ti.com SLLS983L – JUNE 2009 – REVISED OCTOBER 2023

12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
• Texas Instruments, High-Voltage Lifetime of the ISO72x Family of Digital Isolatorsapplication report
• Texas Instruments, SN6505x Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Isntruments, Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, Digital Isolator Design Guide application report
• Texas Instruments, Isolation Glossary application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: ISO1050
ISO1050
SLLS983L – JUNE 2009 – REVISED OCTOBER 2023 www.ti.com

PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com

30 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISO1050

 ISO1050
www.ti.com SLLS983L – JUNE 2009 – REVISED OCTOBER 2023

EXAMPLE BOARD LAYOUT

DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31

Product Folder Links: ISO1050
ISO1050
SLLS983L – JUNE 2009 – REVISED OCTOBER 2023 www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com

32 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: ISO1050

 PACKAGE OPTION ADDENDUM

www.ti.com 3-Oct-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO1050DUB LIFEBUY SOP DUB 8 50 RoHS & Green NIPDAU Level-4-260C-72 HR -55 to 105 ISO1050
ISO1050DUBR ACTIVE SOP DUB 8 350 RoHS & Green NIPDAU Level-4-260C-72 HR -55 to 105 ISO1050 Samples

ISO1050DW LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 105 ISO1050
ISO1050DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 105 ISO1050 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 3-Oct-2023

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO1050DUBR SOP DUB 8 350 330.0 24.4 13.1 9.75 6.0 16.0 24.0 Q1
ISO1050DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO1050DUBR SOP DUB 8 350 367.0 367.0 45.0
ISO1050DWR SOIC DW 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ISO1050DUB DUB SOP 8 50 532.13 13.51 7.36 6.91
ISO1050DUB DUB SOP 8 50 532.13 13 7300 6.6
ISO1050DW DW SOIC 16 40 506.98 12.7 4826 6.6

Pack Materials-Page 3
 PACKAGE OUTLINE
DUB0008A SCALE 1.200
SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE

C
10.7
TYP SEATING PLANE
10.1

A PIN 1 ID
0.1 C

8
1

6X 2.54

9.55 2X
9.02 7.62
NOTE 3
4X
(1.524)

4
5
0.555
4X (0.99) 8X
6.87 0.355
B
6.37 0.1 C A B

6.82
6.32
TOP MOLD

0.355
TYP
0.204

SEE DETAIL A

4.85 MAX
0.635
GAGE PLANE

1.45 0.38 MIN

0 -8 1.15

DETAIL A
TYPICAL

4222355/G 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.254 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DUB0008A SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE

8X (2.35) 8X (2.35)
SYMM SYMM
1 1
8 8
(R0.05) (R0.05)
8X (0.65) 8X (0.65)
TYP TYP

SYMM SYMM

6X (2.54) 6X (2.54)

5 5
4 4

(9.1) (9.45)

IPC-7351 NOMINAL HV / ISOLATION OPTION

6.75 mm CLEARANCE/CREEPAGE 7.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLES

EXPOSED METAL SHOWN
SCALE:5X

METAL UNDER SOLDER MASK

SOLDER MASK METAL SOLDER MASK OPENING
OPENING

0.07 MAX EXPOSED METAL 0.07 MIN EXPOSED METAL

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4222355/G 04/2019
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DUB0008A SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE

8X (2.35) SYMM 8X (2.35) SYMM

1 1
8 8
(R0.05) (R0.05)
8X (0.65) TYP 8X (0.65) TYP

SYMM SYMM

6X (2.54) 6X (2.54)

5 5
4 4

(9.1) (9.45)

IPC-7351 NOMINAL HV / ISOLATION OPTION

6.75 mm CLEARANCE/CREEPAGE 7.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:5X

4222355/G 04/2019
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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