ISO6520, ISO6521

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ISO652x General Purpose Dual-Channel Functional Isolators

1 Features 3 Description
• Dual channel, CMOS output functional isolators The ISO652x devices are high-performance, dual-
• 50Mbps data rate channel functional isolators designed for cost
• Robust SiO2 isolation barrier with ±150kV/μs sensitive, space constrained applications that require
typical CMTI isolation for non-safety applications. The isolation
• Functional Isolation (8-REU): barrier supports a working voltage of 200VRMS /
– 200VRMS, 280VDC working voltage 280VDC and transient over voltages of 570VRMS /
– 570VRMS, 800VDC transient voltage (60s) 800VDC.
• Functional Isolation (8-D): The devices provide high electromagnetic immunity
– 450VRMS, 637VDC working voltage and low emissions at low power consumption, while
– 707VRMS, 1000VDC transient voltage (60s) isolating CMOS or LVCMOS digital I/Os. Each
• Available in a compact 8-REU package with isolation channel has a logic input and output buffer
>2.2mm creepage separated by TI's double capacitive silicon dioxide
• Wide supply range: 1.71V to 1.89V and 2.25V to (SiO2) insulation barrier. ISO6520 has two isolation
5.5V channels with both channels in the same direction.
• 1.71V to 5.5V level translation ISO6521 has two isolation channels with one channel
• Default output High (ISO652x) and Low in each direction. In the event of input power or signal
(ISO652xF) Options loss, the default output is high for devices without
• Wide temperature range: –40°C to 125°C suffix F and low for devices with suffix F. See Device
• 1.8mA per channel typical at 1Mbps at 3.3V Functional Modes section for further details.
• Low propagation delay: 11ns typical at 3.3V
• Robust electromagnetic compatibility (EMC) These devices help prevent noise currents on data
– System-Level ESD, EFT, and surge immunity buses, such as UART, SPI, RS-485, RS-232, and
– Ultra-low emissions CAN from damaging sensitive circuitry. Through chip
design and layout techniques, the electromagnetic
• Leadless-DFN (8-REU) package and Narrow- compatibility of the devices have been significantly
SOIC (8-D) package options enhanced to ease system-level ESD and emissions
compliance.
2 Applications
• Power supplies Package Information
• Grid, Electricity meter PART NUMBER PACKAGE (1) PACKAGE SIZE(2)
• Motor drives ISO6520, ISO6520F
DFN (8-REU) 3.0mm x 2.0mm
• Factory automation ISO6521, ISO6521F
• Building automation ISO6520, ISO6520F
• Lighting D (8) 4.9mm x 6.0mm
ISO6521, ISO6521F
• Appliances
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) The package size (length × width) is a nominal value and
VCCI VCCO includes pins, where applicable.

Series Isolation
Capacitors
INx OUTx

GNDI GNDO
Copyright © 2016, Texas Instruments Incorporated

VCCI=Input supply, VCCO=Output supply

GNDI=Input ground, GNDO=Output ground

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6 Parameter Measurement Information.......................... 14
2 Applications..................................................................... 1 7 Detailed Description......................................................15
3 Description.......................................................................1 7.1 Overview................................................................... 15
4 Pin Configuration and Functions...................................3 7.2 Functional Block Diagram......................................... 15
5 Specifications.................................................................. 4 7.3 Feature Description...................................................16
5.1 Absolute Maximum Ratings........................................ 4 7.4 Device Functional Modes..........................................16
5.2 ESD Ratings............................................................... 4 8 Application and Implementation.................................. 18
5.3 Recommended Operating Conditions.........................4 8.1 Application Information............................................. 18
5.4 Thermal Information....................................................5 8.2 Typical Application.................................................... 18
5.5 Package Characteristics............................................. 5 9 Power Supply Recommendations................................19
5.6 Electrical Characteristics—5-V Supply....................... 6 10 Layout...........................................................................19
5.7 Supply Current Characteristics—5-V Supply.............. 6 10.1 Layout Guidelines................................................... 19
5.8 Electrical Characteristics—3.3-V Supply.................... 7 10.2 Layout Example...................................................... 20
5.9 Supply Current Characteristics—3.3-V Supply........... 7 11 Device and Documentation Support..........................21
5.10 Electrical Characteristics—2.5-V Supply ................. 8 11.1 Documentation Support.......................................... 21
5.11 Supply Current Characteristics—2.5-V Supply......... 8 11.2 Receiving Notification of Documentation Updates.. 21
5.12 Electrical Characteristics—1.8-V Supply.................. 9 11.3 Support Resources................................................. 21
5.13 Supply Current Characteristics—1.8-V Supply......... 9 11.4 Trademarks............................................................. 21
5.14 Switching Characteristics—5-V Supply...................10 11.5 Electrostatic Discharge Caution.............................. 21
5.15 Switching Characteristics—3.3-V Supply................10 11.6 Glossary.................................................................. 21
5.16 Switching Characteristics—2.5-V Supply................11 12 Revision History.......................................................... 21
5.17 Switching Characteristics—1.8-V Supply................11 13 Mechanical, Packaging, and Orderable
5.18 Typical Characteristics............................................ 12 Information.................................................................... 22

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4 Pin Configuration and Functions

VCC1 1 8 VCC2 VCC1 1 8 VCC2

ISOLATION

ISOLATION
INA 2 7 OUTA OUTA 2 7 INA

INB 3 6 OUTB INB 3 6 OUTB

GND1 4 5 GND2 GND1 4 5 GND2

Not to scale Not to scale

Figure 4-1. ISO6520 D Package 8-Pin SOIC Top Figure 4-2. ISO6521 D Package 8-Pin SOIC Top
View View

VCC1 VCC2 VCC1 VCC2

ISOLATION

ISOLATION
INA OUTA OUTA INA

INB OUTB INB OUTB

GND1 GND2 GND1 GND2

Figure 4-3. ISO6520 DFN Package 8-Pin REU Top Figure 4-4. ISO6521 DFN Package 8-Pin REU Top
View View

Table 4-1. Pin Functions

(1)
NAME PIN TYPE Description
ISO6520 ISO6521
GND1 4 4 - Ground connection for
VCC1
GND2 5 5 - Ground connection for
VCC2
INA 2 7 I Input, channel A
INB 3 3 I Input, channel B
OUTA 7 2 O Output, channel A
OUTB 6 6 O Output, channel B
VCC1 1 1 P Power supply, VCC1
VCC2 8 8 P Power supply, VCC2

(1) I = Input, O = Output, P = Power

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5 Specifications
5.1 Absolute Maximum Ratings
See(1)
MIN MAX UNIT
VCC1 to GND1 -0.5 6
Supply Voltage (2) V
VCC2 to GND2 -0.5 6

Input/Output INx to GNDx -0.5 VCCX + 0.5 (3)

V
Voltage OUTx to GNDx -0.5 VCCX + 0.5 (3)
Output Current Io -15 15 mA
Operating junction temperature, TJ 150 °C
Temperature
Storage temperature, Tstg -65 150 °C

Transient Isolation AC Voltage, t=60s 570 VRMS

Voltage (REU-8) DC Voltage, t=60s 800 VDC

Transient Isolation AC Voltage, t=60s 707 VRMS

Voltage (SOIC-8) DC Voltage, t=60s 1000 VDC

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
(3) Maximum voltage must not exceed 6 V.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/
±6000
ESDA/JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge Charged device model (CDM), per V
JEDEC specification JESD22-C101, all ±1500
pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

TEST CONDITIONS MIN NOM MAX UNIT
VCC1 (1) Supply Voltage Side 1 VCC = 1.8 V (3) 1.71 1.89 V
VCC1 (1) Supply Voltage Side 1 VCC = 2.5 V to 5 V (3) 2.25 5.5 V
VCC2 (1) Supply Voltage Side 2 VCC = 1.8 V (3) 1.71 1.89 V
VCC2 (1) Supply Voltage Side 2 VCC = 2.5 V to 5 V (3) 2.25 5.5 V
VCC
UVLO threshold when supply voltage is rising 1.53 1.71 V
(UVLO+)
VCC
UVLO threshold when supply voltage is falling 1.1 1.41 V
(UVLO-)
Vhys
Supply voltage UVLO hysteresis 0.08 0.13 V
(UVLO)
0.7 x VCCI
VIH High level Input voltage (2) VCCI V

VIL Low level Input voltage 0 0.3 x VCCI V

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TEST CONDITIONS MIN NOM MAX UNIT

VCCO (2) =5V -4 mA
VCCO = 3.3 V -2 mA
IOH High level output current
VCCO = 2.5 V -1 mA
VCCO = 1.8 V -1 mA
VCCO = 5 V 4 mA
VCCO = 3.3 V 2 mA
IOL Low level output current
VCCO = 2.5 V 1 mA
VCCO = 1.8 V 1 mA
DR Data Rate 0 50 Mbps
TA Ambient temperature -40 25 125 °C

Functional Isolation Working AC Voltage (sine wave) 200 VRMS

VIOWM
Voltage (REU-8) DC Voltage 280 VDC

Functional Isolation Working AC Voltage (sine wave) 450 VRMS

VIOWM
Voltage (SOIC-8) DC Voltage 637 VDC

(1) VCC1 and VCC2 can be set independent of one another

(2) VCCI = Input-side VCC; VCCO = Output-side VCC
(3) The channel outputs are in undetermined state when 1.89 V < VCC1, VCC2 < 2.25 V and 1.05 V < VCC1, VCC2 < 1.71 V

5.4 Thermal Information

ISO652x
(1)
THERMAL METRIC DFN (REU-8) D (SOIC-8) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 143.4 104.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 70.0 48.9 °C/W
RθJB Junction-to-board thermal resistance 78.3 52.9 °C/W
ψJT Junction-to-top characterization parameter 4.2 7.9 °C/W
ψJB Junction-to-board characterization parameter 77.7 52.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

5.5 Package Characteristics

VALUE VALUE
PARAMETER TEST CONDITIONS UNIT
8-REU 8-D
CLR External clearance(1) Shortest pin to pin distance through air >2.2 >4 mm
Shortest pin to pin distance across the
CPG External creepage(1) >2.2 >4 mm
package surface
CTI Comparative tracking index IEC 60112; UL 746A >400 >400 V
Material Group According to IEC 60664-1 II II
CIO Capacitance, input to output(2) VIO = 0.4 × sin (2 πft), f = 1 MHz ≅0.5 ≅0.5 pF
RIO Resistance, input to output(2) TA = 25°C >1012 >1012 Ω

(1) Creepage and clearance requirements must be applied according to the specific equipment isolation standards of an application. Care
must be taken to maintain the creepage and clearance distance of a board design to verify that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) All pins on each side of the barrier tied together creating a two-pin device.

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5.6 Electrical Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -4 mA; See Figure 6-1 VCCO - 0.4 V
VOL Low-level output voltage IOL = 4 mA; See Figure 6-1 0.4 V
VIT+(IN) Rising input switching threshold 0.7 x VCCI (1) V
VIT-(IN) Falling input switching threshold 0.3 x VCCI V
VI(HYS) Input threshold voltage hysteresis 0.1 x VCCI V
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
VI = VCC or 0 V, VCM = 700V ;
CMTI Common mode transient immunity 100 150 kV/μs
See Figure 6-3
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
Ci Input Capacitance (2) 2.8 pF
MHz, VCC = 5 V

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) Measured from input pin to same side ground.

5.7 Supply Current Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO6520

VI = VCCI (1) (ISO6520), VI = 0 V (ISO6520 with F ICC1 1.1 1.7

suffix) ICC2 1.3 2.2
Supply current - DC
signal (2) ICC1 3.2 4.6
VI = 0V (ISO6520), VI = VCC1 (ISO6520 with F suffix)
ICC2 1.4 2.3
ICC1 2.1 3.1
1 Mbps mA
ICC2 1.5 2.4

Supply current - AC All channels switching with square ICC1 2.2 3.2
10 Mbps
signal (3) wave clock input; CL = 15 pF ICC2 2.7 3.6
ICC1 2.5 3.6
50 Mbps
ICC2 7.9 9.5
ISO6521
VI = VCCI (1) (ISO6521); VI = 0 V (ISO6521 with F
Supply current - DC ICC1, ICC2 1.2 2.2
suffix)
signal (2)
VI = 0 V (ISO6521); VI = VCCI (ISO6521 with F suffix) ICC1, ICC2 2.3 3.5
mA
1 Mbps ICC1, ICC2 1.9 2.9
Supply current - AC All channels switching with square
10 Mbps ICC1, ICC2 2.5 3.6
signal (3) wave clock input; CL = 15 pF
50 Mbps ICC1, ICC2 5.2 6.7

(1) VCCI = Input-side VCC

(2) Supply current valid for ENx = VCCx and ENx = 0V
(3) Supply current valid for ENx = VCCx

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5.8 Electrical Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -2mA; See Figure 6-1 VCCO - 0.2 V
VOL Low-level output voltage IOL = 2mA; See Figure 6-1 0.2 V
VIT+(IN) Rising input switching threshold 0.7 x VCCI (1) V
VIT-(IN) Falling input switching threshold 0.3 x VCCI V
Input threshold voltage
VI(HYS) 0.1 x VCCI V
hysteresis
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
Common mode transient VI = VCC or 0 V, VCM = 700V ;
CMTI 100 150 kV/μs
immunity See Figure 6-3
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
Ci Input Capacitance(2) 2.8 pF
MHz, VCC = 3.3 V

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) Measured from input pin to same side ground.

5.9 Supply Current Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO6520

VI = VCCI (1) (ISO6520), VI = 0 V (ISO6520 with F ICC1 1.1 1.6

suffix) ICC2 1.3 2.2
Supply current - DC
signal (2) ICC1 3.2 4.5
VI = 0V (ISO6520), VI = VCC1 (ISO6520 with F suffix)
ICC2 1.4 2.3
ICC1 2.1 3.1
1 Mbps mA
ICC2 1.4 2.3

Supply current - AC All channels switching with square ICC1 2.2 3.1
10 Mbps
signal (3) wave clock input; CL = 15 pF ICC2 2.3 3.2
ICC1 2.4 3.4
50 Mbps
ICC2 6 7.3
ISO6521
VI = VCCI (1) (ISO6521); VI = 0 V (ISO6521 with F
ICC1, ICC2 1.2 2.2
Supply current - DC suffix)
signal (2) VI = 0 V (ISO6521);
ICC1, ICC2 2.3 3.5
VI = VCCI (ISO6521 with F suffix)
mA
1 Mbps ICC1, ICC2 1.8 2.9
Supply current - AC All channels switching with square
10 Mbps ICC1, ICC2 2.3 3.4
signal (3) wave clock input; CL = 15 pF
50 Mbps ICC1, ICC2 4.2 5.5

(1) VCCI = Input-side VCC

(2) Supply current valid for ENx = VCCx and ENx = 0V
(3) Supply current valid for ENx = VCCx

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5.10 Electrical Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -1mA ; See Figure 6-1 VCCO - 0.1 V
VOL Low-level output voltage IOL = 1mA ; See Figure 6-1 0.1 V
VIT+(IN) Rising input switching threshold 0.7 x VCCI (1) V
VIT-(IN) Falling input switching threshold 0.3 x VCCI V
Input threshold voltage
VI(HYS) 0.1 x VCCI V
hysteresis
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
Common mode transient VI = VCC or 0 V, VCM = 700V ;
CMTI 100 150 kV/μs
immunity See Figure 6-3
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
Ci Input Capacitance(2) 2.8 pF
MHz, VCC = 2.5 V

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) Measured from input pin to same side ground.

5.11 Supply Current Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO6520

VI = VCCI (1) (ISO6520), VI = 0 V (ISO6520 with F ICC1 1.1 1.6

suffix) ICC2 1.3 2.1
Supply current - DC
signal (2) ICC1 3.1 4.5
VI = 0V (ISO6520), VI = VCC1 (ISO6520 with F suffix)
ICC2 1.4 2.3
ICC1 2.1 3.1
1 Mbps mA
ICC2 1.4 2.3

Supply current - AC All channels switching with square ICC1 2.1 3.1
10 Mbps
signal (3) wave clock input; CL = 15 pF ICC2 2 2.9
ICC1 2.3 3.3
50 Mbps
ICC2 4.8 6
ISO6521
VI = VCCI (1) (ISO6521); VI = 0 V (ISO6521 with F
Supply current - DC ICC1, ICC2 1.2 2.2
suffix)
signal (2)
VI = 0 V (ISO6521); VI = VCCI (ISO6521 with F suffix) ICC1, ICC2 2.3 3.5
mA
1 Mbps ICC1, ICC2 1.8 2.9
Supply current - AC All channels switching with square
10 Mbps ICC1, ICC2 2.1 3.2
signal (3) wave clock input; CL = 15 pF
50 Mbps ICC1, ICC2 3.6 4.9

(1) VCCI = Input-side VCC

(2) Supply current valid for ENx = VCCx and ENx = 0V
(3) Supply current valid for ENx = VCCx

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5.12 Electrical Characteristics—1.8-V Supply

VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -1mA; See Figure 6-1 VCCO - 0.1 V
VOL Low-level output voltage IOL = 1mA; See Figure 6-1 0.1 V
VIT+(IN) Rising input switching threshold 0.7 x VCCI (1) V
VIT-(IN) Falling input switching threshold 0.3 x VCCI V
VI(HYS) Input threshold voltage hysteresis 0.1 x VCCI V
IIH High-level input current VIH = VCCI (1) at INx 10 µA
IIL Low-level input current VIL = 0 V at INx -10 µA
VI = VCC or 0 V, VCM = 700V ;
CMTI Common mode transient immunity 100 150 kV/μs
See Figure 6-3
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
Ci Input Capacitance(2) 2.8 pF
MHz, VCC = 1.8 V

(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

(2) Measured from input pin to same side ground.

5.13 Supply Current Characteristics—1.8-V Supply

VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT
ISO6520

VI = VCCI (1) (ISO6520), VI = 0 V (ISO6520 with F ICC1 0.8 1.5

suffix) ICC2 1.2 2.1
Supply current - DC
signal (2) ICC1 2.8 4.3
VI = 0V (ISO6520), VI = VCC1 (ISO6520 with F suffix)
ICC2 1.3 2.3
ICC1 1.8 2.9
1 Mbps mA
ICC2 1.3 2.3

Supply current - AC All channels switching with square ICC1 1.8 2.9
10 Mbps
signal (3) wave clock input; CL = 15 pF ICC2 1.8 2.7
ICC1 2 3.1
50 Mbps
ICC2 3.8 4.9
ISO6521
VI = VCCI (1) (ISO6521); VI = 0 V (ISO6521 with F
Supply current - DC ICC1, ICC2 1.1 2.1
suffix)
signal (2)
VI = 0 V (ISO6521); VI = VCCI (ISO6521 with F suffix) ICC1, ICC2 2.1 3.4
mA
1 Mbps ICC1, ICC2 1.6 2.7
Supply current - AC All channels switching with square
10 Mbps ICC1, ICC2 1.9 3
signal (3) wave clock input; CL = 15 pF
50 Mbps ICC1, ICC2 3 4.2

(1) VCCI = Input-side VCC

(2) Supply current valid for ENx = VCCx and ENx = 0V
(3) Supply current valid for ENx = VCCx

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5.14 Switching Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 6-1 11 18 ns
tP(dft) Propagation delay drift 8 ps/℃
tUI Minimum pulse width See Figure 6-1 20 ns
PWD Pulse width distortion(1) |tPHL – tPLH| See Figure 6-1 0.2 7 ns
Channel-to-channel output skew time
tsk(o) (2) Same direction channels 6 ns

tsk(p-p) Part-to-part skew time (3) 6 ns

tr Output signal rise time 2.6 4.5 ns
See Figure 6-1
tf Output signal fall time 2.6 4.5 ns
tPU Time from UVLO to valid output data 300 μs
Default output delay time from input Measured from the time VCC goes
tDO 0.1 0.3 μs
power loss below 1.2V. See Figure 6-2
tie Time interval error 216 – 1 PRBS data at 50 Mbps 1 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

5.15 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 6-1 11 18 ns
tP(dft) Propagation delay drift 9.2 ps/℃
tUI Minimum pulse width See Figure 6-1 20 ns
PWD Pulse width distortion(1) |tPHL – tPLH| See Figure 6-1 0.5 7 ns
Channel-to-channel output skew time
tsk(o) (2) Same direction channels 6 ns

tsk(p-p) Part-to-part skew time (3) 6 ns

tr Output signal rise time 1.6 3.2 ns
See Figure 6-1
tf Output signal fall time 1.6 3.2 ns
tPU Time from UVLO to valid output data 300 μs
Default output delay time from input Measured from the time VCC goes
tDO 0.1 0.3 μs
power loss below 1.2V. See Figure 6-2
tie Time interval error 216 – 1 PRBS data at 50 Mbps 1 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

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5.16 Switching Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 6-1 12 20.5 ns
tP(dft) Propagation delay drift 14.3 ps/℃
tUI Minimum pulse width See Figure 6-1 20 ns
PWD Pulse width distortion(1) |tPHL – tPLH| See Figure 6-1 0.6 7.1 ns
Channel-to-channel output skew
tsk(o) Same direction channels 6 ns
time(2)
tsk(p-p) Part-to-part skew time(3) 6.1 ns
tr Output signal rise time 2 4 ns
See Figure 6-1
tf Output signal fall time 2 4 ns
tPU Time from UVLO to valid output data 300 μs
Default output delay time from input Measured from the time VCC goes
tDO 0.1 0.3 μs
power loss below 1.2V. See Figure 6-2
tie Time interval error 216 – 1 PRBS data at 50 Mbps 1 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

5.17 Switching Characteristics—1.8-V Supply

VCC1 = VCC2 = 1.8 V ± 5% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 7-1 15 25.1 ns
tP(dft) Propagation delay drift 15.2 ps/℃
tUI Minimum pulse width See Figure 7-1 20 ns
PWD Pulse width distortion(1) |tPHL – tPLH| See Figure 7-1 0.7 8.2 ns
Channel-to-channel output skew
tsk(o) Same direction channels 6 ns
time(2)
tsk(p-p) Part-to-part skew time(3) 8.8 ns
tr Output signal rise time 2.7 5.3 ns
See Figure 7-1
tf Output signal fall time 2.7 5.3 ns
tPU Time from UVLO to valid output data 300 μs
Default output delay time from input Measured from the time VCC goes
tDO 0.1 0.3 μs
power loss below 1.2V. See Figure 6-2
tie Time interval error 216 – 1 PRBS data at 50 Mbps 1 ns

(1) Also known as pulse skew.

(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.

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5.18 Typical Characteristics

7.5 4
ICC1 at 1.8V ICC1 at 1.8V
ICC1 at 2.5V ICC1 at 2.5V
3.5 ICC1 at 3.3V
6 ICC1 at 3.3V ICC1 at 5V
ICC1 at 5V ICC2 at 1.8V
Supply Current (mA)

Supply Current (mA)

ICC2 at 1.8V ICC2 at 2.5V
ICC2 at 2.5V 3 ICC2 at 3.3V
4.5 ICC2 at 3.3V ICC2 at 5V
ICC2 at 5V 2.5
3
2

1.5
1.5

0 1
0 10 20 30 40 50 0 10 20 30 40 50
Data rate (Mbps) Data Rate (Mbps)

TA = 25°C CL = 15 pF TA = 25°C CL = 15 pF

Figure 5-1. ISO6520 Supply Current vs Data Rate Figure 5-2. ISO6520 Supply Current vs Data Rate
(With 15-pF Load) (With No Load)
7.5 4
ICC1 at 1.8V ICC1 at 1.8V
ICC1 at 2.5V ICC1 at 2.5V
ICC1 at 3.3V 3.5 ICC1 at 3.3V
6
ICC1 at 5V ICC1 at 5V
Supply Current (mA)

Supply Current (mA)

ICC2 at 1.8V ICC2 at 1.8V
ICC2 at 2.5V 3 ICC2 at 2.5V
4.5 ICC2 at 3.3V ICC2 at 3.3V
ICC2 at 5V 2.5 ICC2 at 5V

3
2

1.5
1.5

0 1
0 10 20 30 40 50 0 10 20 30 40 50
Data rate (Mbps) Data rate (Mbps)

TA = 25°C CL = 15 pF TA = 25°C CL = No Load

Figure 5-3. ISO6521 Supply Current vs Data Rate Figure 5-4. ISO6521 Supply Current vs Data Rate
(With 15-pF Load) (With No Load)
8 7.5
VCC at 1.8V ICC1 at 1.8V
7.2 VCC at 2.5V ICC1 at 2.5V
VCC at 3.3V ICC1 at 3.3V
High-Level Output Voltage (V)

6.4 6
VCC at 5V ICC1 at 5V
Supply Current (mA)

5.6 ICC2 at 1.8V

ICC2 at 2.5V
4.8 4.5 ICC2 at 3.3V
4 ICC2 at 5V

3.2 3
2.4
1.6 1.5
0.8
0 0
-15 -13 -11 -9 -7 -5 -3 -1 0 10 20 30 40 50
High-Level Output Current (mA) Data rate (Mbps)

TA = 25°C TA = 25°C

Figure 5-5. High-Level Output Voltage vs High-level Figure 5-6. Low-Level Output Voltage vs Low-Level
Output Current Output Current

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1.6 19
1.575
17.5
Power Supply UVLO Threshold (V)

1.55

Propagation Delay Time (ns)

1.525 16
1.5
14.5
1.475
1.45 13
1.425
11.5
1.4
1.375 VCC1- 10
1.35 VCC1+ tPHL at 1.8V tPHL at 5V tPLH at 3.3V
VCC2- 8.5 tPHL at 2.5V tPLH at 1.8V tPLH at 5V
1.325 VCC2+ tPHL at 3.3V tPLH at 2.5V
1.3 7
-55 -5 45 95 125 -40 10 60 110
Free Air Temperature (C) Free Air Temperature (C)

Figure 5-7. Power Supply Undervoltage Threshold Figure 5-8. Propagation Delay Time vs Free-Air
vs Free-Air Temperature Temperature

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6 Parameter Measurement Information

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns,
ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. The 50 Ω resistor is not needed in the actual
application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 6-1. Switching Characteristics Test Circuit and Voltage Waveforms

VI See Note B

VCC VCC
VI 1.4 V
Isolation Barrier

0V
IN = 0 V (Devices without suffix F) IN OUT
VO tDO
IN = VCC (Devices with suffix F)
default high
VOH
CL
See Note A VO 50%
VOL
default low

A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

B. Power Supply Ramp Rate = 10 mV/ns

Figure 6-2. Default Output Delay Time Test Circuit and Voltage Waveforms

VCCI VCCO

C = 0.1 µF ±1% C = 0.1 µF ±1%

Pass-fail criteria:
The output must
Isolation Barrier

remain stable.
IN OUT
S1
+

VOH or VOL
CL
See Note A ±

GNDI + VCM ± GNDO

A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 6-3. Common-Mode Transient Immunity Test Circuit

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7 Detailed Description
7.1 Overview
The ISO652x family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices
also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 7-1, shows a functional block diagram of a typical channel.
7.2 Functional Block Diagram

Transmitter Receiver

OOK
Modulation
TX IN SiO2 based
TX Signal Capacitive RX Signal Envelope RX OUT
Conditioning Isolation Conditioning Detection
Barrier

Emissions
Oscillator Reduction
Techniques

Figure 7-1. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 7-2 shows a conceptual detail of how the OOK scheme works.

TX IN

Carrier signal through

isolation barrier

RX OUT

Figure 7-2. On-Off Keying (OOK) Based Modulation Scheme

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7.3 Feature Description

family of devices is available in two channel configurations and default output state options to enable a variety of
application uses. lists the device features of the devices.
Table 7-1. Device Features
PART NUMBER MAXIMUM DATA RATE CHANNEL DIRECTION DEFAULT OUTPUT STATE PACKAGE
ISO6520 50 Mbps 2 Forward, 0 Reverse High REU-8
ISO6520F 50 Mbps 2 Forward, 0 Reverse Low REU-8
ISO6521 50 Mbps 1 Forward, 1 Reverse High REU-8
ISO6521F 50 Mbps 1 Forward, 1 Reverse Low REU-8

7.4 Device Functional Modes

Table 7-2 lists the functional modes for the devices.
Table 7-2. Function Table
(1) INPUT OUTPUT
VCCI VCCO COMMENTS
(INx)(2) (OUTx)
H H
Normal Operation: A channel output assumes the logic state of the input.
L L
PU PU
Default mode: When INx is open, the corresponding channel output goes to
Open Default
the default logic state. The default is High for and Low for with F suffix.
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for and Low for
with F suffix.
PD PU X Default When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined(3).
X PD X Undetermined When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input

(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71V); PD = Powered down (VCC ≤ 1.05 V); X = Irrelevant;
H = High level; L = Low level
(2) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3) The outputs are in undetermined state when 1.89 V < VCCI, VCCO < 2.25 V and 1.05 V < VCCI, VCCO < 1.71 V

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7.4.1 Device I/O Schematics

Input (Devices without F suffix) Input (Devices with F suffix)

VCCI VCCI VCCI VCCI VCCI VCCI VCCI

1.5 M

985 985
INx INx

1.5 M

Output
VCCO

~20
OUTx

Figure 7-3. Device I/O Schematics

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant the accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The ISO652x devices are high-performance, dual-channel digital isolators. The devices use single-ended
CMOS-logic switching technology. The supply voltage range is from 1.71 V to 5.5 V for both supplies, VCC1
and VCC2. Since an isolation barrier separates the two sides, each side can be sourced independently with any
voltage within the recommended operating conditions. As an example, supplying VCC1 with 3.3 V (which is within
1.71 V to 1.89 V and 2.25 V to 5 V) and VCC2 with 5 V (which is also within 1.71 V to 1.89 V and 2.25 V to 5
V) is possible. The digital isolator can be used as a logic-level translator in addition to providing isolation. When
designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators
do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL
digital signal lines. The isolator is typically placed between the data controller (that is, MCU or FPGA), and a
data converter or a line transceiver, regardless of the interface type or standard.

Note
ISO652x is a functional isolator, and is not certified for isolation by standard bodies. For applications
that require certified isolation by standard bodies, customers must choose ISO672x, ISO772x or
ISO782x families of digital isolators.

8.2 Typical Application

ISO652x can be used with Texas Instruments' mixed signal microcontroller, voltage regulator and GaN with
integrated drivers in several power supply designs. ISO652x helps isolate high voltage power MOSFETs from
sensitive logic control circuitry.
VOUT,SENSE

VOUT = +48 V

VOUT2
VOUT2 = 5V
0.1uF
0.1uF COUT
VOUT1 3.3V
LDO
-48 V
VCC VCC1 VCC2 VDD
/Q
ISOLATION

RSENSE
PWM1 INA OUTA
ISENSE PWM1 LMG1210
UCC3138
INB OUTB PWM2
PWM2
Q VSENSE to
GND EN GND1 GND2 GND
ISENSE
-48 V

SW
VOUT1
FB LM5169F

GND VIN
CIN

VOUT2
VIN = -48 V

Figure 8-1. ISO6520 for Level shifting PWM signals from controller referenced to Ground to the FET
driver in an Inverted Buck Boost Topology

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8.2.1 Design Requirements

To design with these devices, use the parameters listed in Table 8-1.
Table 8-1. Design Parameters
PARAMETER VALUE
Supply voltage, VCC1 and VCC2 1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1 0.1 µF
Decoupling capacitor from VCC2 and GND2 0.1 µF

9 Power Supply Recommendations

To provide reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors must be placed as close to the supply
pins as possible. If only a single primary-side power supply is available in an application, isolated power
can be generated for the secondary-side with the help of a transformer driver. For industrial applications,
please use Texas Instruments' SN6501 or SN6505B. For such applications, detailed power supply design
and transformer selection recommendations are available in SN6501 Transformer Drivers for Isolated Power
Supplies or SN6505B-Q1 Low-noise, 1-A Transformer Drivers for Isolated Power Supplies.
10 Layout
10.1 Layout Guidelines
A minimum of two layers is required to accomplish a cost optimized and low EMI PCB design. To further improve
EMI, a four layer board can be used. Layer stacking for a four layer board must be in the following order
(top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of the
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• Bypass the VCC pin to ground with a low-ESR ceramic bypass capacitor. The typical recommended bypass
capacitance is 0.1 μF when using a ceramic capacitor with an X5R- or X7R-rated dielectric. The capacitor
must be placed as close to the VCC pin as possible in the PCB layout and on the same layer. The capacitor
must have a voltage rating greater than the VCC voltage level.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep the planes symmetrical. This design makes the stack mechanically stable and prevents
warping. Also the power and ground plane of each power system can be placed closer together, thus increasing
the high-frequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
10.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.

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10.2 Layout Example

2 mm 2 mm
maximum maximum
from VCC1 from VCC2

VCC1 VCC2

0.1uF 0.1uF

GND1 GND2

Solid ground islands help

dissipate heat through PCB

Figure 10-1. Layout Example

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11 Device and Documentation Support

11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary, application note
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies, data sheet
• Texas Instruments, SN6505x Low-Noise 1-A Transformer Drivers for Isolated Power Supplies, data sheet
• Texas Instruments, SN6507 Low-Emissions, 36-V Push-Pull Transformer Driver with Duty Cyle Control for
Isolated Power Supplies, data sheet
• Texas Instruments, LMG341xR070 600-V 70-mΩ GaN with Integrated Driver and Protection, data sheet
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (December 2023) to Revision B (April 2024) Page

• Updated the number formatting for tables, figures, and cross-references throughout the document................ 1
• Added information about the ISO6521F variant throughout the document ....................................................... 1

Changes from Revision * (August 2023) to Revision A (December 2023) Page

• Updated device status to Production Data......................................................................................................... 1
• Updated Typical Application Diagram...............................................................................................................18

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ISO6520DR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6520 Samples

ISO6520FDR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6520F Samples

ISO6520FREUR ACTIVE VSON REU 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6520F Samples

ISO6520REUR ACTIVE VSON REU 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6520 Samples

ISO6521DR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6521 Samples

ISO6521FDR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6521F Samples

ISO6521FREUR ACTIVE VSON REU 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6521F Samples

ISO6521REUR ACTIVE VSON REU 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 6521 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO6520DR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO6520FDR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO6521DR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO6521FDR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ISO6521FREUR VSON REU 8 3000 180.0 12.4 2.3 3.3 1.2 4.0 12.0 Q2

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ISO6520DR SOIC D 8 3000 353.0 353.0 32.0
ISO6520FDR SOIC D 8 3000 353.0 353.0 32.0
ISO6521DR SOIC D 8 3000 353.0 353.0 32.0
ISO6521FDR SOIC D 8 3000 353.0 353.0 32.0
ISO6521FREUR VSON REU 8 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
REU0008A SCALE 5.000
VSON - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1
B A
2.9

PIN 1 INDEX AREA

2.1
1.9

0.01
0.00
(0.2)

DETAIL A
A40.000

TYPICAL

1.05
0.95 C

SEATING PLANE

0.08 C

SYMM SEE DETAIL A

4
5

SYMM
2X 1.5

6X 0.5
(38 )
8
1
0.3
PIN 1 ID 8X
(0.125) 0.2
0.5 0.1 C A B
8X
0.3
0.05 C

4229400/A 02/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
REU0008A VSON - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

8X (0.6)

8X (0.25) SYMM
SEE SOLDER MASK
DETAIL
1 8

SYMM
6X (0.5)

(R0.05) TYP
4 5

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 25X

0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND

METAL UNDER
METAL EDGE SOLDER MASK

SOLDER MASK
EXPOSED METAL OPENING EXPOSED SOLDER MASK
METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4229400/A 02/2023
NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

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 EXAMPLE STENCIL DESIGN
REU0008A VSON - 1.05 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

8X (0.6)

8X (0.25) SYMM

1 8

SYMM
6X (0.5)

(R0.05) TYP
4 5

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 25X

4229400/A 02/2023

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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