This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPWRD.2015.2477106, IEEE Transactions on Power Delivery

Bridge Type Solid State Fault Current Limiter

Based on AC/DC Reactor

Hamid Radmanesh, Member, IEEE, Seyed Hamid Fathi, Member, IEEE, G.B.Gharehpetian, Senior
Member, IEEE, Amir Heidary
 device such as fuse [5]. This equipment is a self-triggering,
Abstract— This paper proposes a novel Bridge Type Solid cheap and has a small size which can interrupt fault currents
State Fault Current Limiter (BSSFCL) based on one series without using sensors and actuators. But, it is single-use
reactor which operates both in AC and DC modes. The device and needs manually replacement [6]. Also, a circuit
proposed BSSFCL includes a rectifier bridge with a reactor. breaker (CB) is a protective equipment and can be
This reactor is used as a DC reactor in normal operation mode
automatically tripped. But, CBs with high-current
and as an AC reactor in fault condition. The advantages of the
proposed BSSFCL over the existing DC reactor type FCLs are
interrupting capabilities are expensive devices [6]. In recent
its negligible impedance in normal operation mode and its high years, novel schemes for limiting the magnitude of the fault
impedance during fault interval using a simple and novel current have been proposed. The fault current limiter (FCL)
switching. In other word, during the normal operation mode, is the best solution for the fault current limitation as
the proposed BSSFCL is operated in DC mode and in fault compared to the previously presented limiting schemes.
interval its topology is changed to the AC mode. This switching Regarding FCLs protective reaction, they can be considered
decreases the switching transient recovery voltage (TRV) and in two types. One type limits the fault current to an
introduces considerable impedance during the fault period. acceptable level, suitable to be safely interrupted by circuit
The MATLAB/Simulink software is used for simulations and
breaker (CB). The other type acts as a breaker and interrupts
also a prototype is designed and tested for results verification,
and to show the performance of the proposed BSSFCL. the fault current itself. In this paper, the first type, i.e. non-
Index Terms— Bridge Type Solid State Fault Current Limiter, interrupting FCL, is investigated. Due to the type of the
Series Reactor, Point of Common Coupling, Switching reactor, FCLs can be categorized in two types. One type
Overvoltage employs the DC reactor and other one uses AC reactor to
I. INTRODUCTION limit the fault current to an acceptable level. One of the
n response to consumption growth, new power generation power electronics based FCLs is Bridge-type FCL (BFCL)

I plants should be installed. Developing networks and their

interconnections may increase the fault current levels,
that are classified in single-phase and three-phase four-wire
configurations [7-10]. Usually these BFCLs employ a
which are more than the maximum short-circuit capacity of rectifier bridge and a DC reactor for limiting the fault
circuit breakers. The increased fault current level can cause current. The basic structure of BFCL presented in [11] has a
severe damages to the network. Among different faults in simple structure and acts inherently in the instant of fault
distribution network, the short-circuit fault is the most usual inception so it does not require control circuit. However,
one and can cause serious damages such as overvoltage this DC reactor-type FCL cannot withstand against the fault
transients, loss of synchronization, isolations failure and current for a long period. Evoking a high DC voltage across
may cause explosion of equipment containing insulating oil. the DC reactor during fault period increases the system
To prevent these problems, some solutions are used such as; losses and leads to use a bulky and expensive cooling
upgrading the switchgear and other related components [1], system. To mitigate the basic BFCL problems, some
connecting the power electronic converter interface between modification were made by the authors. In [12-14], a
networks and newly installed distributed generator (DG) [2], damping resistor with an Integrated Gate-Bipolar Transistor
power system reconfiguration [3], connecting high (IGBT) switch in series with the DC reactor is used to
impedance transformers for increasing impedance of the control the fault current amplitude. During fault, the
network [4] and also new solution like the application of the controller has an on-off duration for IGBT and inserts the
Unified Interphase Power Controller (UIPC) for fault damping resistor in the fault current path which decreases
current control in interconnected systems [5]. But these the fault current amplitude to an acceptable level. This
methods need high power ratings, weight and cost. A cheap controllable damping resistor can decrease the fault current
and reliable solution may be the application of a protection level and improve the voltage profile up to an acceptable
voltage level, but overvoltage on the IGBT is considerable
so using the bulky and expensive cooling system is
Hamid Radmanesh is with the Electrical Engineering Department of
unavoidable. A high performance DC reactor type FCL
Aeronautical University of Science and Technology, Tehran, Postal Code:
1384674153, Iran (e-mail: Hamid.radmanesh@aut.ac.ir) and also with the where FCL components are places on the secondary side of
Electrical Engineering Department of Amirkabir University of Technology an isolation transformer is proposed in [15]. This FCL is
(Tehran Polytechnic), Tehran, Postal Code: 158754413, Iran based on BFCL concept where its DC reactor includes two
S. H. Fathi, G.B. Gharehpetian and Amir Heidary are with the coils. The main coil of the DC reactor is connected in series
Electrical Engineering Department of Amirkabir University of Technology with a damping resistor in parallel with an IGBT the same
(Tehran Polytechnic), Tehran, and Postal Code: 158754413, Iran. (e-mail:
fathi@aut.ac.ir, grptian@aut.ac.ir, amir.powersys@gmail.com)
as the previous FCL structure of [12-14]. The
supplementary coil of it is connected to the bypass switches.

0885-8977 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPWRD.2015.2477106, IEEE Transactions on Power Delivery

The bypass switches are controlled the DC reactor to lower current and voltage stresses. This paper organized
impedance in order to suppress transient inrush current or is as follows:
limit the fault current. If the fault current exceeds the In Section II, the system topology including BSSFCL
thresholds level, the controller inserts the damping resistor structure is discussed. Then, in section III, the analytical
in the fault current path via turning-off the IGBT. Although analysis of the BSSFCL operation in DC and AC modes and
this FCL acts better than other DC reactor types FCLs but it BSSFCL power losses are studied. In section IV, the
has some problems including conduction losses, switching concept of the control system is discussed. In section V, the
overvoltage, complicated control strategy and using cooling design consideration of the proposed BSSFCL components
system is unavoidable. The DC reactor type FCLs have less is given. The MATLAB software is applied to investigate
voltage drop during normal mode, but they can withstand the operational behavior of the BSSFCL and related
only a limited period of fault current. Redundant volt- simulation results are discussed in section VI. In section
second on the DC reactor during the fault period saturates VII, experimental results are presented and finally
the core and the FCL will lose the current limiting conclusion is given.
capability. II. PROPOSED BSSFCL CONFIGURATION
AC reactor based FCLs use power electronics or mechanical In this study, a novel BSSFCL configuration includes a
switches to bypass the AC reactor during the normal rectifier bridge in normal operation mode, two antiparallel
operation mode [16]. Some topologies employ a series switches in fault operation mode and a single reactor that is
resonance LC tank in their structures [17]. The series used to feed the load in normal and fault operation modes is
resonance FCLs are invisible during normal operation mode introduced. The basic solution of the proposed BSSFCL
because the series AC reactor and capacitor are in resonance operation is based on changing the operation mode of the
condition and their total impedance is negligible. During the BSSFCL from DC mode (normal operation mode) to AC
fault, the power electronic switches bypass the series mode (fault operation mode) by switching. Fig. 1 shows the
capacitor and de-tuned the series resonance LC tank. Then, network with two feeders including suggested BSSFCL
the AC reactor impedance limits the fault current. These structure. It is assumed that the feeder F1 supplies a
FCLs have good capability to decrease the fault current but sensitive load and the feeder F2 delivers power to other
their on-state power losses and switching overvoltage are loads.
not acceptable. Some of them use an arrester in parallel with PCC
CB Feeder F1
the power electronics switches to decreases the switching Transformer
overvoltages. In series/parallel resonance structures, the T3 D
D1 2
equivalent resistance of the LC tank is quite significant

Sensitive Load
CB Feeder F2 Ld CT
rs
problems which represent considerable losses. Recently
Ls
solid state circuit breakers have been introduced in T1 T4 T2

Load
literatures [18-19]. These devices act as a circuit breaker Vs(t)=Vmsin(ωt) Fault
RL

faster than the traditional mechanical circuit breakers. BSSFCL LL

T1
The DC reactor types FCLs have good performance during T2
T3
Control
circuit
the normal operation mode but they cannot control the fault T4

current successfully. On the other hand, AC reactor types Fig. 1. Proposed BSSFCL configuration in two feeders network
FCLs can successfully decrease the fault current to an (a)
acceptable level but they have a considerable losses during
T3
the normal operation mode. Also, switching between normal
and fault condition causes high overvoltages on the power
electronics switches. Furthermore, in order to have a proper
FCL, it is recommended to combine the DC and AC reactor D1 Ld D2
iac idc iac
based FCLs with superior advantages.
In this paper, a novel and simple Bridge type Solid State
Fault Current Limiter (BSSFCL) structure based on AC/DC
reactor is presented that overcomes most of the FCLs
drawbacks outlined previously. In fact, the newly proposed T4
BSSFCL is a DC reactor type FCL during normal operation (b)
mode which avoids the undesirable saturation of DC reactor
and it is an AC reactor type FCL during the fault period. In
other word, in the DC reactor type FCL the current in the D1 D2
limiting impedance is always DC, for the normal operation iac Ld iac
and for the fault condition. In the proposed BSSFCL, the
current in the reactance is DC during normal operation and iac
becomes AC during the fault operation. Employing single
reactor in both application (DC and AC operation) causes T1 T2
negligible power loss in the normal operation, inserting
large impedance in the current path during the fault Fig. 2. BSSFCL operation modes a) normal operation mode (DC operation
condition, quick response and fast recovery after fault mode) and b) fault current limiting mode (AC operation mode)
removal. The proposed BSSFCL can withstand against long The novel BSSFCL circuit uses six switching elements
fault current and its power electronics switches are subject instead of four in the older bridge type FCL circuits. The

0885-8977 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPWRD.2015.2477106, IEEE Transactions on Power Delivery

BSSFCL operation is divided in two modes including 2

Plosses 2rd I Line 2rd rd I 2 Line
normal and fault operation modes. During normal operation K    (1)
mode, the BSSFCL configuration is a DC reactor type FCL
Pload rL I 2line rL U L I L cos 
where T3 and T4 are turned-on and by participation of D1 where,
and D2, they form a rectifier bridge as shown in Fig. 2(a). I2
Pload  rL line (2)
The induced DC voltage via rectifier bridge charges the DC 2
reactor with the DC current. Then, the rectifier bridge As an example, in a distribution feeder with 250A line
switches (D1 and D2 for positive half cycles and T3 and T4 current, PF=0.9, rd=0.1Ω and UL=20kV, the value of K is
for negative half cycles) start conducting and short- equal to 0.13%. Furthermore, the power losses in DC
circuiting the DC reactor by free-wheeling action. In this reactor resistance are very small percentage of the feeder
case, the series reactor is used as a DC one and BSSFCL is power and it is negligible for most of the practical
invisible with negligible effect on the network power applications. Neglecting the DC reactor resistance (rd), idc(t)
quality. During fault, the BSSFCL configuration should at t4 can be expressed by (3).
change from DC reactor type FCL to the AC reactor type didc t 
VDS  Ld (3)
FCL. To meet this requirement, T3 and T4 are turned off and dt
T1 and T2 are turned on. In this case, the rectifier bridge where, the initial value of idc(t) at t4 is Ipeak, VDS is the series
configuration is changed to into two pair antiparallel power reactor voltage and we have:
electronic switches (D1 in parallel with T1 and D2 in parallel V
with T2) and feeds the reactor with AC current. Then, the idc  t   DS  t  t4   I peak (4)
Ld
reactor's AC impedance (XL) decreases the amplitude of the
fault current. The BSSFCL configuration in fault operation Fig. 3 (a) shows the expand view of one cycle of the line
mode is shown in Fig. 2(b). and DC reactor currents during the normal operation mode.
This figure shows the effect of DC reactor resistance on the
III. ANALYTICAL APPROACH OF THE BSSFCL peak of the line current. Neglecting the small voltage drop
In this section, the analytical approach of the BSSFCL is of semiconductor devices, the total voltage drop across the
explained for DC mode (normal operation) and AC mode BSSFCL is almost zero. So, the BSSFCL has negligible
(fault operation). For analyzing the BSSFCL behavior, the effect on the normal operation mode.
configuration of Fig.2 (a) for normal operation mode is State2: Fault interval (from t4 to t8). The fault occurs at t4,
studied. Then, the BSSFCL operation in AC mode (Fig. fault current increases and Ld starts to be charged. In this
2(b)) during the fault interval is investigated. case, the DC reactor withstands against the fault current
A. DC operation mode where charging and discharging modes occur.
In this case, the BSSFCL operates as a rectifier bridge that It has been shown that the DC reactor current increases
induces DC voltage on the series reactor and short circuits it gradually after fault inception and the first peak of the fault
by free-wheeling action. In fault inception, the increased current decreases as shown with dotted curve in Fig. 3 (b).
fault current reaches to the threshold current level (iL) and After fault occurrence, there are two charching and
after iL, the controller changes the BSSFCL topology to AC discharging interval is as follows:
mode. To compute the line current value in normal and fault Interval 1: Charging mode (between t4 and t5 and between t6
operation modes before changing the BSSFCL topology and t7) as shown with dotted curve in Fig. 3 (b) where the
from DC mode to AC mode, two states are considered as line current can be obtained by solving the equation (5).
follows: di  t 
State1: Pre-fault condition (before t4). In the normal Vm sin t   ri  t   L L  2V (5)
operation mode, the semiconductor switches (D1 and D2 for L dt DF
positive half cycles and T3 and T4 for negative half cycles)  V 2V  V 2V
iL  t   e r / L t t4  i4  m sin t4     DF   m sin t     DF
are in ON state and in this case, Ld is charged with DC  Z r  Z r
current up to the peak value of the line current and forms a
short-circuit. According to the polarity of the line current, (6)
D1 and D2 conduct in positive half cycles, while T3 and T4 where, r  rs  rf  rd , L  Ls  L f  Ld , iL  t   id  t   i t  ,
conduct in negative half cycles as shown in Fig. 2(a). The
tan 1  L 
reactor includes losses and usually these losses are modeled Z  r 2   L  ,   , and i4  i  t4  . Also, Ld,
2

with a series resistance. Due to reference [20], the maximum r

ohmic resistance of the inductance are estimated as 1% of its rd, Lf, rf and VDF are DC reactor inductance and resistance,
50 Hz reactance and it cannot be neglected for real fault inductance and resistance and voltage drop across the
application. This is a common value found in literature [21]. power electronic switches, respectively.
In this paper, the DC reactor optimized inductance value for Interval 2: Discharging mode (between t5 and t6 and between
BSSFCL application is about 0.1H. By this inductance, it is t7 and t8) as shown in Fig. 3 (b) where the DC reactor
possible to decrease the DC current ripple (ir,p–p) to very low current is more than line current, so its current freewheels
values while the DC reactor resistance has a maximum value through the rectifier bridge and we have:
of 0.1Ω [21]. In order to determine the reactor power losses, di  t 
the ratio of power losses of the reactor to active power of Vm sin t   riL  t   L L (7)
dt
the electrical load is defined by the parameter K and can be
where, r  rs  rf and L  Ls  L f .
derived as follows:
Using equation (7), the following equation can be obtained
for the line current in discharging mode.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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 Vm  Vm C. Power loss calculations

iL  t   e i5  Z sin t5     Z sin t   
  r / L   t  t5 
(8) The BSSFCL power losses in the normal operation mode
 
(DC mode) include losses of the rectifier bridge and DC
where, i5  i  t5  and the value of Z and φ have been given reactor. In each cycle of the network frequency, the rectifier
in the previous case. After t6, another charging mode bridge diodes are ON in a half cycle and bypass the series
(between t6 and t7) and discharging mode (between t7 and t8) reactor by free-wheeling action. So, the BSSFCL power
still exist. losses on the normal mode are calculated as follows:
(a)
Ploss , BSSFCL  PLoss , RB  P L  2VDF I average  rd  I dc 
2
(10)
Imax d

320 I where, PLoss,BSSFCL is the BSSFCL total power losses, and

2
310 I0 PLoss,RB is the rectifier bridge power losses. VDF is the
Current (A)

300 voltage drop on each diode, rd is the equivalent resistance of

290
the DC reactor, Idc is DC side current, which is equal to peak
Charging Discharging
period period of line current and Iaverage is the diodes current average in
280
t3 each cycle of the network frequency. Due to equation (10),
270 there is negligible voltage drop across the BSSFCL
DC reactor current
260 t0 t1 t2 Line current components. It is obvious that the power losses of the
175 Time (msec) 195 BSSFCL mostly include losses of the reactor. Therefore, it
(b) is a small percentage of the transmitted power of the feeder
4000 DC mode
X: 0.2238 DC&AC mode and it can be ignored for the most of practical applications.
2000 IL Y: 1686 X: 0.31 IV. DESIGN CONSIDERATION OF THE BSSFCL
Current (A)

X: 0.1861 Y: 1073
Y: 317.3 This section emphasis on the BSSFCL components and their
0 design requirement for the medium-voltage level (2–36 kV).
X: 0.1751
Y: -312.5 Among the BSSFCL components, accessibility of the power
-2000 Expand
view t5 t7 electronic switches and series reactor in such rating is a
Fig. 3(a) t4 t6 t8 toff main challenge that should be investigated.
-4000
160 180 200 220 240 260 280 300 320 340 360 A. Power Electronics Switches
Time (msec)
High rating power electronic switches are commercially
Fig. 3. a) Expand view of line and reactor current and b) Line current
during normal and fault operation mode while operation of BSSFCL in DC available. In addition, available power electronic switches
mode is shown with dotted curve and operation of BSSFCL in DC mode have rather high blocking voltage and current ratings and
(normal operation mode) and AC mode (fault operation mode) is shown are relatively easy to parallel and string. At medium-voltage
with solid curve level, the use of snubber circuits is mandatory while it is not
B. AC operation modes necessary for low-voltage level. The suggested BSSFCL can
When fault current increases and reaches to iL, the controller employ the self-turn off switch for switching implementation
changes the BSSFCL topology from DC mode to AC mode just in a short time. This makes the suggested BSSFCL cost-
and we have third state as follows: effective and reliable for distribution network application.
State3: Changing the BSSFCL switching topology form DC For BSSFCL application in high power networks, the proper
mode to AC mode (from t8 till the completely fault removal balancing between switches modules and press-packs must
instant (toff)). In this case, the peak of the line current be kept. In addition, power losses and voltage drop on
reaches to per-defined value (IL) and the controller changes switches during the fault must be taken into account. IGBT
the BSSFCL topology form DC mode to AC mode. In this is a suitable power electronic switch to use in low power
case, D1 with T1 and D2 with T2 form two antiparallel applications and available voltage levels up to 6.5kV are
switches that feed the reactor with AC voltage as shown in exist both in press-pack and modules [22]. In addition,
Fig. 2 (b). Similarly, T3 and T4 are turning off at first zero IGCTs are also available in the voltage levels between
crossing current and the new circuit topology induces an AC 2.5kV to 10 kV and current level up to 9kA. The IGCTs on-
voltage on the Ld. By this switching pattern in fault interval, states power losses are low so it can be used in high power
the impedance of the AC reactor increases and the fault applications. However, the power electronic diodes and
current amplitude decreases to the specified level as shown passive components are accessible in different ratings.
in Fig.3 (b) with solid curve. So, from t8 till toff, the BSSFCL B. Series Reactor Design
is operated in AC mode. The circuit behavior in AC The design consideration of the series reactor is more
operation mode can be expressed by (7), but the value of R important. This reactor are able to limit short-circuit
and L is different from the previous case. In this state, the currents and it is a main component of the BSSFCL. In
AC reactor inductance and resistance are considered in the order to design the series reactor into present power
equation and the electrical load is short-circuited. So we systems, costs are a decisive factor. The series reactor
have: design offers some degree of freedom, which gives the
Vm Vm    L   (9)
R
  t t 
iL (t )  e L  sin  t  tan 1 
8

 opportunity to design BSSFCL at minimal costs. The series

R   L 
2 2
R 2   L 
2
  R 
reactor should be invisible during normal operation that the
where, Vm is the amplitude of the distribution network influence on the grid is minimized. However, a small reactor
source. The equation (9) is composed of exponential and resistance is unavoidable. Using the series reactor with big
sinusoidal parts as shown in Fig. 3 (b) from t8 till toff. The inductance can decrease the fault current to the desired
exponential part causes a transient in the line current and value but the large reactor has a considerable power loss and
duration of this transient depends on the system time it is not acceptable. In addition, a larger reactor is much
constant. more complicated to build and it increases the total time

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constant. For analyzing the system behavior during the V. CONTROL STRATEGY
steady state condition and studying the effect of the reactor Control block diagram of the BSSFCL is shown in Fig. 5. In
on the fault current, the equivalent circuit of the system order to proper control of the BSSFCL, line current (iline) is
shown in Fig. 4 is used. sampled via a Current Transformer (CT) and sent to the
control circuit. Before comparing iLine with the maximum
id rd Ld permissible current level (IL+), it is passed from a 50Hz band
pass filter and its value is applied to comparator (1).
Monitoring the instantaneous value of the line current
increases the controller respond speed in limiting the fault
Zd current at the instant of fault inception.
VDS=(2/π )Vm Iline 50Hz Band
NOT
T3 Driver
ig3
Pass Filter
Comp.(1) NOT
A/D BPF + Step
Reset T4 Driver
Generator ig4
IL+
T1 Driver
Comp.(2) ig1
Fig. 4. Equivalent circuit of system during fault condition RMS
+
Delay
In this model, the source and fault impedances are ignored T2 Driver
because its value in comparison with the reactor inductance IR ig2
is very small and can be neglected. In addition, for obtaining Fig. 5. Control system block diagram
the DC reactor current, the value of the electrical source is In normal operating mode iLine is in marginal level and the
modeled by its mean value on the DC side. For obtaining the step generator output pulses turn the T3 and T4 on. So, the
DC reactor current, it is necessary to design the value of the BSSFCL configures a rectifier bridge that feeds the reactor
DC reactor inductance. The differential equation of the with DC voltage and BSSFCL shows negligible impedance
equivalent circuit shown in Fig. 4 is given in equation (3). in the feeder. At fault inception, as iline exceeds iL+ in
By solving equation (3), the DC reactor current is obtained positive half cycles, the control circuit detects abnormal
as given in equation (4). The effect of the DC reactor losses condition and the step generator turns the T3 and T4 off and
(rd) is not considered in (4), because its value in comparison T1 and T2 on. In this case, the new configuration of the
with Ld, is very small. In addition, we have: BSSFCL induces AC voltage on the series reactor and
i4  id  t  t4   I d (11)
inserts the considerable impedance in the current path,
resulting in the fault current limitation. The control system
where, t4 is the instant of the fault inception and it is also includes evaluation of Root Mean Square (RMS) value
assumed that the controller changes the BSSFCL topology of the line current. In this loop, the line current is applied to
from DC mode to the AC mode at t4. The reactor inductance a RMS block to calculate RMS value of the line current.
value during normal operation mode should be considered Then, this value is compared with the reference current level
enough, where the current flow through the reactor being the (iR). At the fault removal inception, while the BSSFCL
same as the normal flow of the AC current through the configuration is AC mode, the RMS value of line current
transmission line. On the other hand, with respect to the decreases rapidly below the reference value iR. Then, the
nominal values of the power network equipment, the value detector circuit sends reset signal to the step generator block
of the reactor inductance should be considered suitable that and this block generates the command signal for thyristors
it can decrease the fault current level to an acceptable level after one cycle delay. As a result, the system returns to its
and the circuit breaker successfully opens the faulty line. normal operation mode and BSSFCL configuration changes
However, increasing the reactor inductance increases the to DC mode. During one cycle delay, both electrical load
time of its discharge after fault clearance and also increases and AC reactor are connected to the source and the stored
the system operation delay. By considering t8 as the energy on the reactor is discharged to the load.
necessary time for changing the BSSFCL switching VI. SIMULATION RESULTS
topology after fault inception and its corresponding current The simulation results are obtained using 20kV network
with iL+, we can solve the equation (3) to obtain the equation data as listed in Table I. Also, single-phase to ground fault
(12) for fault occurrence mode. is considered for studying the fault current in the proposed
Ld r i   VDS network.
t 8  t4  Ln d L (12) TABLE I
rd rd i4  VDS ELECTRICAL NETWORK PARAMETERS USED FOR SIMULATION STUDY
In equation (12), iL+ is determined via controller alignment
Symbol Description Value
and its capability to changing the BSSFCL topology from
DC mode from AC mode. On the other hand, the value of Vs(Simulation) Source Voltage (rms) 20kV
iL+ is determined according to the maximum current values rs Source Resistance 0.5Ω
of the distribution network equipment. In addition, the time Ls Source Inductance 0.01H
rL Line Resistance 1Ω
between t8 and t4 (t8-t4) is the BSSFCL time performance LL Line Inductance 0.01H
before the current of the power electronic diodes exceeds f Network Frequency 50Hz
from iL+. Furthermore, by determining the rectifier bridge VTh
Voltage Drop Across
2V
output voltage (VDS), t4 and t8, it is possible to design the Thyristor
VD Voltage Drop Across Diode 2V
reactor inductance and resistance. rd Reactor Resistance 0.1 Ω
Ld Reactor Inductance 0.1H
rf Fault Resistance 0.01 Ω

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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Lf Fault Inductance 0H the fault interval is 200msec. The performance of the

Distribution feeders Feeder F1 0.314j Ω proposed BSSFCL is examined with different value of the
data Feeder F2 0.157j Ω
Sensitive Load 10+j15.7 Ω series reactor. The results show that the reactor with bigger
Load data inductance decreases the fault current better but the system
Load of F2 48.4Ω
The electrical network including the proposed BSSFCL is delay and total losses increases as well. So, the inductance
simulated in this section. Fig. 6 shows the line current in value of the reactor and its design procedure should be
normal and fault operation modes while there is no installed considered carefully based on the special network
BSSFCL in the feeder. So, at fault inception, the line current requirements. In current case study, the value of the reactor
increases and reaches to 6.8kA. After fault clearance, the inductance is considered to be 100mH.
line current decreases and reaches to the pre-fault value. 20
Normal mode Load voltage Normal mode
Line current without BSSFCL effect X: 0.1456
6000 X: 0.1686 10 Y: 1.524e+004

Voltage (kV)
Y: 6888
4000 During fault
X: 0.1628
IL 0
Current (A)

Y: 1695
2000 X: 0.2635
Y: 0.02529
0 -10
-2000 one cycle delay
First cycle
-4000 -20
0 50 100 150 200 250 300 350 400 450 500
t4 toff Time (msec)
0 50 100 150 200 250 300 350 400 450 500
Time (msec) Fig. 8. Electrical load voltage during normal and fault operation modes
Fig. 6. Line current during normal and fault operation without using wile the proposed BSSFCL is connected in series with the feeder
BSSFCL Fig. 8 shows the load voltage during normal and fault
Fig. 7 shows the line and series reactor currents in in normal operation modes while the proposed BSSFCL is connected
operation (DC) mode, during fault (AC) mode, and after in series with the feeder. Before fault, the BSSFCL is in DC
fault removal (DC) mode while the proposed BSSFCL is mode so there is no voltage drop on its equipment but the
connected in series with the feeder. During normal operation first cycle of the load voltage after the instant of CB
mode, the BSSFCL is in DC mode and feeds the series energization is not sinusodial. After bypassing the DC
reactor with DC voltage. In this case, the BSSFCL shows reactor, the load voltage has a good quality and the BSSFCL
negligible impedance and DC reactor current is DC with utelization has negligible effect on it. At the fault inception,
small ripple as shown with dotted curve in this figure. After the load voltage decreases to zero. At t=360msec the short
fault occurrence, the line current increases with smooth circuit fault is cleared but the controller changes the
slope and reach to iL at t8. During t4 till t8, the BSSFCL is in BSSFCL topology from AC mode to DC mode after one
DC mode and the DC reactor limits the fault current. By cycle delay. During this delay, both electrical load and AC
comparing the first peak of the fault current shown in Fig. 6 reactor are connected to the network and the amplitude of
with first peak of the limited fault current in Fig. 7, it is the load voltage is decreased during this cycle. At toff system
clearly obvious that the DC topology of the BSSFCL can returns to the pre-fault condition and the electical network
decrease the fault current amplitude from 6.8kA to 1.6kA. feeds the load with sinosudial voltage.
This value is the maximum permissible current level
6000 X: 0.168 (a)
(1.6kA) and increasing the fault current from this current (b)
Y: 6812 (c)
level (iL) causes to change the BSSFCL topology from DC 4000 I
L X: 0.1912
Current (A)

Y: 1688 X: 0.2894
mode to AC mode. 2000 Y: 690.1
0
4000 Line current
Reactor current -2000
X: 0.36
2000 IL -4000 Y: -4696
Current (A)

t t toff
4 on
150 200 250 300 350 400
0
X: 0.16 X: 0.36 X: 0.38 Time (msec)
Y: -20.98 Y: -95.54 Y: -155.2
-2000
Fig. 9. Line current in normal and fault operation modes a) without using
current BSSFCL, b) BSSFCL operation in DC mode both in normal and fault
ripple
-4000
t4 t8 t9 toff conditions and c) BSSFCL operation in DC mode (normal operation
0 50 100 150 200 250 300 350 400 450 500 mode) and AC mode (fault operation mode)
Time (msec) Fig. 9 compares the line current in three cases including the
Fig. 7. Line and series reactor currents during normal and fault operation fault current without using BSSFCL, the limited fault
modes affected by proposed BSSFCL
current via rectifier bridge and DC reactor and the limited
The system is simulated for 500msec and fault occurs at
fault current via suggested BSSFCL in DC and AC
t4=160msec. Before the fault inception, the reactor current is
operation modes. Curve (a) illustrates the fault current when
idc as shown with dotted curve and the reactor is short-
there is no any FCL in the line. In this case the fault current
circuited. But at t4 the fault current increases and DC reactor
amplitude reaches to 6.8kA. By connecting the bridge type
impedance limits its amplitude until t8. At t8 the new
FCL with DC reactor to the line, the fault current decreases
BSSFCL topology forces the DC reactor to the AC mode
as shown with curve (b). The dotted curve shows the
and the impedance of the reactor increases as well. At
suggested FCL performance on the fault current that has
t9=360msec, the fault is cleared and the line current
been previously introduced in [7, 8, 11-15]. In these papers
decreases, accordingly. So, the control circuit returns the
some types of the bridge type FCL with DC reactor have
BSSFCL topology to the DC mode after one cycle delay at
been introduced. These FCLs employ a DC reactor with the
toff and the DC reactor current is returned to the pre-fault
rectifier bridge to control the fault current. In [12-15], the
value which causes to short circuit the reactor. In this study,

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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basic bridge type FCL has been modified and these papers Using a start/stop switch, a single line to ground fault is
have been added a damping resistor with controllable IGBT modeled. The controlling circuit includes a current sensor
switch in parallel with this damping resistor to control the (LTS25-NP) which is connected in series with the line for
fault current. The result of these FCLs is like a curve (b) but monitoring the line current during normal and fault
the amplitude of the limited fault current is fixed to the pre- conditions. The output of this sensor is applied to the
determined value. However, the effect of suggested microcontroller for analyzing the line current and producing
BSSFCL on the fault current is shown with curve (c). The the command signals for thyristors. There are four thyristors
performance of the suggested BSSFCL during the normal gate drivers. Their output is applied to the thyristors for
operation mode is the same as the suggested FCLs in [12- proper operation of the BSSFCL in normal and fault modes.
15]. But, after fault inception the suggested BSSFCL Oscilloscope
employs the AC reactor to control the fault current and its DC power
Autotransformer
supply
performance is completely different with the DC reactor Multi-meter DC/AC reactor
type FCLs. The goal of this figure is to show the BSSFCL Fault
effect on the fault current in comparison with the ordinary LTS25-NP
SW D1
bridge type FCLs effect on the fault current. Comparing T4
curve b with curve c, shows that the suggested BSSFCL can T2
D2
decrease the fault current to an acceptable level while curve T3
b shows the line current “line current with DC reactor T1
operation” in red color is growing more and more and after
some milliseconds, it can cause FCL failure which is not
acceptable. Therefore, this is a big problem for the DC
reactor type FCLs [11-15] and this problem is solved
Control system
successfully by designing the suggested BSSFCL. The
suggested BSSFCL employs the DC reactor only during Electrical load
normal operation mode and it works as an AC reactor Fig. 12. Laboratory prototype of BSSFCL
during the fault period. Then, during the fault, we have an TABLE II
AC reactor without any growing current. This is an EXPERIMENTAL SETUP PARAMETERS
important privilege of the suggested BSSFCL over other DC Symbol Description Value
reactor type FCLs. The limited fault current, i.e. the curve
(c) in Fig.9, clearly shows the effectiveness of the suggested Vs(Exprimental) Source Voltage (rms) 110V
f Power System Frequency 50Hz
BSSFCL. rd Reactor Resistance 1Ω
Also, the switching overvoltage in the suggested structure is Ld Reactor Inductance 0.1H
considerably decreased as shown in Figs. 10 and 11. Rload Load Resistance 48.4 Ω
Voltage 1200V
(a) Diode SKN 26/12
Voltage (kV) Current (A)

400
Current 24A
200 Thyristor Voltage 1200V
0
SKT24/12D
Current 24A
3
(b)
2 Fig. 13 shows the line current and load voltage before and
OFF-state OFF-state
1 ON-state
after fault occurrence. The fault occurs at instant (a) and is
0
removed at instant (b). Before the fault occurrences, the line
0 50 100 150 200 250 300 350 400 450 500 current amplitude is 1Ap-p and the load voltage is 110Vrms.
Time (msec)
Fig. 10. a) Current and b) voltage of T1 or T2 during normal and fault The load voltage and line current are sinusoidal and the
operation modes system works under normal operation mode. The lower and
400
(a)
Current (A)

upper waveforms of figure are in fair agreement with Figs. 7

OFF-state
200 and 8, respectively. After fault removal, the fault current is
decreased to the normal current and the BSSFCL topology
0
is changed to DC mode. In solidly grounded fault, the
20 (b)
ON-state amplitude of the fault current increases rapidly and its peak
Voltage (kV)

ON-state
value depends on the source voltage amplitude and the
0
circuit impedance. In electrical laboratory, we cannot test
-20
one cycle delay the solid ground fault with 110V source voltage, because the
0 50 100 150 200 250 300 350 400 450 500
Time (msec) amplitude of the fault current can reach to 110A for a 1Ω
Fig. 11. a) Current and b) voltage of T3 or T4 during normal and fault resistance and this current level is higher than the current
operation modes
rating of the laboratory. However, we have tested the fault
VII. EXPERIMENTAL RESULTS
condition with a resistance equals to 5Ω. In this case, the
The prototype of the BSSFCL shown in Fig. 1, is studied in
fault current amplitude reaches to 22A and the suggested
this section. The prototype parameters are listed in Table II
BSSFCL can successfully decrease the prospective fault
and the built one is shown in Fig. 12. This prototype
current to 5A. This means that it can reduce the fault current
consists of two power electronic diodes, four thyristors and
amplitude to 23% of its initial value.
a reactor. Also the control circuit is used for changing the
Fig. 14 shows the line and series reactor currents during
BSSFCL topology from DC to AC mode and vice versa.
normal and fault operation modes. Before fault inception,
the reactor current is DC with a small ripple. After fault

0885-8977 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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occurrence, the BSSFCL topology changes the DC reactor triggering pulse to T1 and T2 in negative half cycle. So, the
to the AC one and its current is an AC limited fault current switching is soft, and there is no transient overvoltage on
because the AC reactor impedance is inserted in series with thyristors. At first zero-crossing, T1 and T2 conduct the line
the faulty line. After fault removal, the control circuit current in negative half cycle, while T3 and T4 are OFF. This
calculates the current fall and changes the BSSFCL switching pattern is a main advantage of the suggested
topology to the DC mode after one cycle delay. Upper BSSFCL because it can employ thyristors in its structure
waveform of Figs. 14 is in agreement with solid curve of without experiencing any transient overvoltage. Fig. 15
Fig. 7 and lower waveform of Fig. 14 is in agreement with shows T1 and T2 voltage drop during normal and fault
dotted curve of Fig. 7. operation modes. Fig. 16 shows T3 and T4 voltage drop
during normal and fault operation modes. Figs. 15 and 16
Voltage (V)

are in agreement with Figs. 10 and 11, respectively.

During fault
Fault mode

Current (A)
Normal Normal
mode mode
(b)
IL T1 and T2 T1 and T2
turning off turning on
Current (A)

instant instant
On-state During off state On-state

Voltage (V)
(a)

Three cycle delay

Time (msec)
Fig. 13. BSSFCL effect on line current before and after fault occurrence
(instant of fault inception at (a) and removal at (b)) (lower waveform
(current/division=2A with probe X1 and time/division=50ms)) and load
voltage (upper waveform (voltage/division=2V with probe X100 and
Time (msec)
time/division=50ms))
Fig. 15. T1 and T2 voltage drop (lower waveform) and current (upper
Rector current (A) Line current (A)

Fault mode waveform) during normal mode (BSSFCL in DC mode) and fault mode
(a) (b) (BSSFCL in AC mode), (current/division=5A with probe X1 and
voltage/division=100V with probe X1 and time/division=50ms)

Fault mode
Current (A)

Normal Normal
BSSFCL switching recovery from mode mode
AC mode to DC mode
Switching
transition time

T3 and T4 turning T3 and T4 turning

DC DC on instant off instant
AC current
Voltage (V)

OFF state OFF state

During on state
Time (msec)
Fig. 14. Line and reactor current in normal and fault operation modes
(upper waveform is line current and lower waveform is reactor current
(current/division =5A with probe X1 and time/division=50ms))
One of the main advantages of the suggested BSSFCL is its
switching topology from DC mode (normal operation mode)
to AC mode (fault operation mode), while the BSSFCL Time (msec)
switching is soft. In the other word, at fault inception, the Fig. 16. T3 and T4 voltage drop (lower waveform) and current (upper
BSSFCL topology is a rectifier bridge, which feeds the DC waveform) during normal mode (BSSFCL DC operation) and fault mode
reactor with DC voltage. In this case, D1 and D2 in positive (BSSFCL AC operation), (current/division=5A with probe X1,
voltage/division=100V with probe X1 and time/division=50ms)
half cycle, T3 and T4 in negative half cycle conduct and the
The comparative study of the suggested BSSFCL with the
fault current decreases via the DC reactor impedance. After
FCLs in [7-15] shows its superior characteristics over other
limiting the first peak of the fault current, the controller
FCLs. The advantages of the proposed BSSFCL in
changes the BSSFCL topology from DC mode to AC mode,
comparison with other DC reactor type FCLs, can be stated
when the line current is in positive half cycle. It should be
as follows:
noted that in positive half cycles, all thyristors are in OFF
 Comparing the BSSFCL with other FCLs presented in [7-
state and power electronic diodes are conducting the line
15], the proposed BSSFCL uses only one reactor to
current. In other word, the switching of thyristors happens,
control the fault current amplitude with its high
when the diodes are conducting. Therefore, all of the
inductance, which enables better operation by changing
thyristors are in OFF state and the controller sends the

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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the switching topology from DC mode to the AC mode, [5] Pourhossein, J.; Gharehpetian, G.B.; Fathi, S.H., "Unified Interphase
Power Controller (UIPC) Modeling and Its Comparison with IPC and
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reliable. Gharehpetian, "Series transformer based diode-bridge-type solid state
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operation modes and available power electronic Current Limiter for Microgrid," IEEE Transactions on Power
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[9] Hamid Radmanesh, S.H. Fathi, G.B. Gharehpetian, Novel high
considerably decreased. performance DC reactor type fault current limiter, Electric Power
In addition, the proposed BSSFCL offers the following Systems Research, vol.122, pp.198-207, May 2015.
advantages that warrant it over the DC reactor type FCLs, [10] Rashid, G.; Ali, M.H., "A Modified Bridge-Type Fault Current
SCFCL and Is-limiters. Limiter for Fault Ride-Through Capacity Enhancement of Fixed
Speed Wind Generator," IEEE Transactions on Energy Conversion,
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capability is higher. Controllable resistive type fault current limiter (CR-FCL) with
frequency and pulse duty-cycle, International Journal of Electrical
Development of the proposed single-phase BSSFCL to
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three-phase BSSFCL is easy. The three-phase version [14] Firouzi, M.; Gharehpetian, G.B., "Improving Fault Ride-Through
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPWRD.2015.2477106, IEEE Transactions on Power Delivery

Hamid Radmanesh (M’15) was born in 1981. He

received his B.Sc., M.Sc. and Ph.D. degrees in
electrical engineering in 2006, 2009 and 2015 from
Malek- Ashtar University of Technology, Tehran,
Iran, Shahed University, Tehran, Iran and Amirkabir
University of Technology (AUT), Tehran,
Iran, respectively. Currently, he is an Assistant
Professor of electrical engineering department at
aeronautical university of science& technology,
Tehran, Iran. He teaches high voltage insulation technology, transient in
power system and apparatus. He is the author of more than 50 journal and
conference papers. His research interests include design and modeling of
power electronic converters, FCLs, drives, and transient in power system,
chaos in power system apparatus.
Seyed Hamid Fathi (M’12) received the B.Sc. degree
in electrical engineering from the Amirkabir University
of Technology (AUT), Tehran, Iran, in 1984, the M.Sc.
degree in electrical engineering from the Iran University
of Science and Technology, Tehran, in 1987, and the
Ph.D. degree in electrical engineering from the
University of Newcastle upon Tyne, Newcastle Upon
Tyne, U.K., in 1991. Afterward, he joined AUT, where
he is currently an Associate Professor with the Department of Electrical
Engineering. His research interests include power quality, flexible ac
transmission systems, power electronics, and electric drives.
G.B.Gharehpetian (M’2013) received his BS, MS
and Ph.D. degrees in electrical engineering in 1987,
1989 and 1996 from Tabriz University, Tabriz, Iran
and Amirkabir University of Technology (AUT),
Tehran, Iran and Tehran University, Tehran, Iran,
respectively, graduating all with First Class Honors.
He has been holding the Assistant Professor position
at AUT from 1997 to 2003, the position of Associate
Professor from 2004 to 2007 and has been Professor
since 2007. He is the author of more than 700 journal and conference
papers. His teaching and research interest include Smart Grid, DGs,
Monitoring of Power Transformers, FACTS Devices, HVDC Systems and
Power System Transients.

Amir Heidary was born in 1984 in Iran. He received the

B.Sc. degrees from the Electrical Eng. Dept. of Islamic
Azad University, Abhar Branch, Iran, in 2010. His
especial fields of interest include transient in power
systems, Power Quality in power systems and Fault
Current Limiters.

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