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DSDLAB5

The document is a lab report submitted by Jawad Irfan for Digital System Design, focusing on a BCD to Seven Segment Decoder. It includes code for two tasks: the first task decodes a 4-bit binary input to a 7-segment display output, while the second task adds two 4-bit inputs and displays the sum. The report adheres to academic integrity guidelines.

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Jawad irfan
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19 views6 pages

DSDLAB5

The document is a lab report submitted by Jawad Irfan for Digital System Design, focusing on a BCD to Seven Segment Decoder. It includes code for two tasks: the first task decodes a 4-bit binary input to a 7-segment display output, while the second task adds two 4-bit inputs and displays the sum. The report adheres to academic integrity guidelines.

Uploaded by

Jawad irfan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lab Report #5

Digital System Design LAB

Submitted By: JAWAD IRFAN

Registration No: 21PWCSE2009

Section: B

Submitted To: Shahzada Fahim Jan

“On my honor , as student of University of Engineering and


Technology, I have neither given nor received unauthorized
assistance on this academic work”

Student Signature:

JAWAD IRFAN

Department of Computer Systems Engineering

University of Engineering and Technology Peshawar


LAB # 5
BCD to Seven Segment Decoder
TASK 1:
CODE:
module labt1(

output [6:0]out,

output dp,

input [3:0] in,

input en

);

assign dp = en;

assign out = (in == 4'b0000)? 7'b1000000:

(in == 4'b0001)? 7'b1111001:

(in == 4'b0010)? 7'b0100100:

(in == 4'b0011)? 7'b0110000:

(in == 4'b0100)? 7'b0011001://4

(in == 4'b0101)? 7'b1010010://5

(in == 4'b0110)? 7'b0000010://6

(in == 4'b0111)? 7'b1111000://7

(in == 4'b1000)? 7'b0000000://8

7'b0011000;

endmodule
OUTPUT:
TASK2:
CODE:

// Create Date: 13:37:01 03/20/2024

// Design Name:

// Module Name: labt2

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module lab6t2(

output[6:0]out,

output dp,
input [3:0] A,

input [3:0] B,

input en

);

wire [3:0] sum;

assign sum = A+B;

assign dp = en;

assign out = (sum == 4'b0000)? 7'b1000000://0

(sum == 4'b0001)? 7'b1111001://1

(sum == 4'b0010)? 7'b0100100://2

(sum == 4'b0011)? 7'b0110000://3

(sum == 4'b0100)? 7'b0011001://4

(sum == 4'b0101)? 7'b1010010://5

(sum == 4'b0110)? 7'b0000010://6

(sum == 4'b0111)? 7'b1111000://7

(sum== 4'b1000)? 7'b0000000://8

7'b0011000.

endmodule
OUTPUT:
At 0100 0100 the both 4 add to each other and will store in sum.

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