EXPERIMENT NO.
6
BCD TO 7 SEGMENT DECODER & BCD ADDER
Learning Outcomes
1) Know the workings of a 7-segment display
2) Study the operation of a BCD to 7-segment decoder
3) Construct and test a BCD Adder
Components Required
7447 – BCD to 7-segment decoder 7483 – 4-bit parallel adder
7408 – Quad 2-input AND 7432 – Quad 2-input OR
FND 507 – 7 segment display
Experiment
A seven segment Display is used for displaying any one of the decimal digits from 0 through
9. When the decimal digit is available in BCD, a BCD to seven-segment decoder converts the
BCD number to the corresponding seven-segment code.
Run #01: BCD to 7 segment Decoder
IC 7447 is a BCD to seven-segment decoder/driver with active low outputs. The diagram
below shows how to connect the IC to a common cathode seven-segment LED display unit –
FND 507. These connections are already made on the kit.
Now give the inputs to the IC 7447. Observe the display pattern and note your observations
in the table.
Table 6.1 : Observation table for Run #01
Inputs (D C B A) Display pattern Inputs (D C B A) Display pattern
0 0 0 0 1 0 0 0
0 0 0 1 1 0 0 1
0 0 1 0 1 0 1 0
0 0 1 1 1 0 1 1
0 1 0 0 1 1 0 0
0 1 0 1 1 1 0 1
0 1 1 0 1 1 1 0
0 1 1 1 1 1 1 1
Now apply logic ‘0’ to the LT pin of IC 7447. What happens to the display?
Q: What can you infer about the LT (Lamp Test) Pin?
Run #02: BCD Adder using Verilog Data Flow Modelling Instantiation and
FPGA kit implementation
In Experiment 5(previous Experiment) we have already learned how to use instantiation in gate level
modelling. Use that knowledge and follow up with the same 4-bit adder for implementing the BCD
Adder.
Here are the steps given (as a revision) regarding the instantiation in gate level modelling: -
Step 1: Come up with Verilog code for 1-bit full adder using dataflow modelling. A Partial code is
given below.
Complete the code and test its functionality by writing the test bench.
Concatenation Operator:
The concatenation operator "{ , }" combines (concatenates) the bits of two or more operands
separated by commas to form a larger vector. To understand the concept of concatenation, first, we
need to understand the declaration of vectors.
Vectors are multiple-bit width input or output data type variables that can be declared by specifying
their range.
Example: input [3:0] a, output [3:0] b
Step 2: In the Xilinx tool, specify the vectors in the “New Source Wizard” window as shown in the
screenshot below
From the above screenshot, it is clear that “a” is defined as a 4-bit input vector and f3, f2, f1, and f0
are defined as 1-bit outputs.
By clicking Next and Finish, the following piece of code is generated .
It is seen that indeed the variable “a” is given as a 4-bit vector (3 down to 0).
Step 3: Now that vector concept is understood. To understand concatenation, use the following
piece of code and understand concatenation.
In the above Verilog code, the 4-bit input vector “a” is continuously assigned to the outputs f3, f2, f1,
and f0. Since the input variable “a” is 4-bit, it can be assigned to only output variables of 4-bit type.
But because we have four 1-bit outputs, we can concatenate them and form 4-bit output as shown
in the above piece of code. The bit specified first in the concatenation operators becomes the MSB
and the bit specified at the last becomes the LSB.
The student should also note that each bit of a vector can be accessed. In the 4-bit input variable
[3:0] a, each of the signals can be accessed by “a[n]” where n is 0 to 3. To access the MSB, we type
a[3] and similarly to access LSB, we type a[0].
Step 4: Now let us combine the concept of concatenation and arithmetic operators and come up
with the design of a 1-bit full adder at the dataflow level.
We know that there are arithmetic operators in Verilog and they can be used to get the
1-bit full adder. In the above piece of code “a + b + cin” gives out the addition of three 1-bit
variables. We know that the output of the addition of three 1-bit variables can result in an extra bit
(carry). This extra bit can be assigned with the help of the concatenation operator as shown above.
Step 5: Implement a 4-bit full adder using dataflow modeling. This is very similar to the
above example except for the fact that the variables a,b, and sum will be 4-bit and cin and
carry remain 1-bit. Test this adder by using a test bench.
Step 6: Instantiating the 4-bit full adder modules created in step 5 and implement the BCD adder .
The partial code is shown below:
Table 6.2: Observation table for Run #02
BCD 1 BCD 2 Carry in MSD(C) LSD
(A0A1A2A3) (B0B1B2B3)
(S0S1S2S3)
8 4 0
2 3 1
9 9 1
8 2 0
6 8 0
7 7 1
Optional Exercise:
Run #03: BCD Adder on Trainer Kit
This run aims at designing and implementing a single digit BCD adder and displaying the
two-digit sum on seven segment displays.
Q: Can 7483 be directly used to produce a sum in BCD?
Q: What is the least possible sum on adding two single digit BCD numbers?
Q: What is the largest possible sum on adding two single digit numbers (assume input carry is
also available)? What is its BCD representation?
Figure 6.3 : Circuit diagram for BCD Adder (RUN # 03)
The maximum sum of two BCD numbers can contain 2 digits (MSD and LSD). Connect the outputs of
the above circuit diagram to two IC 7447s (BCD to seven-segment decoders) so that the outputs are
displayed as digits on the two seven-segment displays.
Figure 6.3: Placement of ICs for Run #03
Table 6.3: Observation table for Run #03
BCD 1 BCD 2 Carry in MSD(C) LSD
(A0A1A2A3) (B0B1B2B3)
(S0S1S2S3)
8 4 0
2 3 1
9 9 1
8 2 0
6 8 0
7 7 1
